CN109003985A - Memory construction and forming method thereof - Google Patents
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- CN109003985A CN109003985A CN201810890862.4A CN201810890862A CN109003985A CN 109003985 A CN109003985 A CN 109003985A CN 201810890862 A CN201810890862 A CN 201810890862A CN 109003985 A CN109003985 A CN 109003985A
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- 230000015654 memory Effects 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000010276 construction Methods 0.000 title claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 149
- 238000009792 diffusion process Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000003860 storage Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 45
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910021389 graphene Inorganic materials 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- -1 tin alkene Chemical class 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 230000003197 catalytic effect Effects 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 150000001336 alkenes Chemical class 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000004575 stone Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 175
- 230000008569 process Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000009413 insulation Methods 0.000 description 8
- 239000002346 layers by function Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
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- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of memory construction and forming method thereof, the memory construction includes: semiconductor substrate；Storage stack structure in the semiconductor substrate, including the insulating layer being stacked with and control gate layer；Through the channel structure of the storage stack structure to the semiconductor substrate；The control gate layer includes grid and the diffusion barrier layer between the grid and channel structure, insulating layer, and the diffusion barrier layer includes at least one layer of two-dimentional barrier layer using two-dimentional conductive material.The performance of the memory construction is improved.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of memory construction and forming method thereof.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
In 3D NAND flash memory structure, control grid includes barrier layer and metal gates, and the barrier layer is for stopping
The metallic atom of metal gates is to external diffusion.The control grid resistance of the prior art is larger, leads to biggish RC retardation ratio, influences 3D
The performance of nand flash memory.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of memory constructions and forming method thereof, can be improved and deposit
The performance of reservoir.
The present invention provides a kind of memory construction, comprising: semiconductor substrate；Memory heap in the semiconductor substrate
Stack structure, including the insulating layer being stacked with and control gate layer；Through the storage stack structure to the semiconductor substrate
Channel structure；The control gate layer includes grid and the diffusion between the grid and channel structure, insulating layer
Barrier layer, the diffusion barrier layer include at least one layer of two-dimentional barrier layer using two-dimentional conductive material.
Optionally, the diffusion barrier layer further includes at least one layer of metal barrier.
Optionally, the two-dimentional barrier layer is between the metal barrier and grid or the metal barrier
Between the two-dimentional barrier layer and grid.
Optionally, the conductivity on the two-dimentional barrier layer is greater than the conductivity of the metal barrier.
Optionally, the material of the metal barrier includes at least one in Ti, Ta, TiN, TaN, Co, CoWP and TiW
Kind.
Optionally, the material on the two-dimentional barrier layer includes at least one of graphene and tin alkene.
Optionally, the two-dimentional barrier layer with a thickness of 0.3 nanometer to 3 nanometers.
To solve the above-mentioned problems, a specific embodiment of the invention also provides a kind of forming method of memory construction,
It include: offer semiconductor substrate, the semiconductor substrate surface is formed with initial stacked structure and channel structure, the initial heap
Stack structure includes the insulating layer and sacrificial layer being successively stacked with, and the channel structure runs through the initial stacked structure；It is formed
Through the grid line separate slot of the initial stacked structure；The sacrificial layer is removed along the grid line separate slot, is formed and is located at adjacent insulation
Opening between layer；Form the diffusion barrier layer of the covering opening inner wall and the grid positioned at the diffusion barrier layer surface
Pole；The diffusion barrier layer includes at least one layer of two-dimentional barrier layer using two-dimentional conductive material.
Optionally, the diffusion barrier layer further includes at least one layer of metal barrier.
Optionally, the two-dimentional barrier layer is between the metal barrier and grid or the metal barrier
Between the two-dimentional barrier layer and grid.
Optionally, the conductivity on the two-dimentional barrier layer is greater than the conductivity of the metal barrier.
Optionally, the material of the metal barrier includes at least one in Ti, Ta, TiN, TaN, Co, CoWP and TiW
Kind.
Optionally, the material on the two-dimentional barrier layer includes at least one of graphene and tin alkene.
Optionally, using chemical vapor deposition process, silicon carbide epitaxial growth method, metal catalytic epitaxial growth method or atom
Layer depositing operation forms the two-dimentional barrier layer.
Optionally, the two-dimentional barrier layer with a thickness of 0.3 nanometer to 3 nanometers.
In memory construction of the invention, control gate layer includes diffusion barrier layer and grid.The diffusion barrier layer is extremely
It less include one layer of two-dimentional barrier layer, the material on the two dimension barrier layer is two-dimentional conductive material, and resistance is lower, can reduce RC and prolongs
Late, the programming time that can shorten memory improves the performance of memory；And two-dimentional conductive material thickness is low, is capable of increasing
The process window for forming grid, improves the quality of grid.
Detailed description of the invention
Fig. 1 to Fig. 7 is the structural schematic diagram of the memory construction forming process of a specific embodiment of the invention.
Specific embodiment
The specific embodiment of memory construction provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
Fig. 1 to Fig. 7 is please referred to, is the structural schematic diagram of the storage organization forming process of the embodiment of the invention.
Referring to FIG. 1, providing semiconductor substrate 100,100 surface of semiconductor substrate is formed with initial stacked structure
110 and channel structure 120, the initial stacked structure 110 includes the insulating layer 111 and sacrificial layer 112 being successively stacked with, institute
Channel structure 120 is stated through the initial stacked structure 110.
The semiconductor substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to device
Actual demand, can choose suitable semiconductor substrate 100, be not limited thereto.It is described partly to lead in the specific embodiment
Body substrate 100 is monocrystalline silicon wafer crystal.
The initial stacked structure 110 includes insulating layer 111 and sacrificial layer 112.The sacrifice of the initial stacked structure 110
112 material of layer can be silicon nitride, and 111 material of insulating layer can be silica.
The channel structure 120 includes the substrate epitaxial layer 123 and covering channel hole side wall for being formed in channel hole bottom
Functional layer 121 and positioned at 121 surface of functional layer and fill the channel dielectric layer 122 in full channel hole.The functional layer
121 further comprise barrier layer, electric charge capture layer, tunnel layer and the channel stacked from channel hole sidewall surfaces according to 7~166 times
Layer.In the specific embodiment, the functional layer 121 is the compound of O-N-O-P (oxide-nitride-oxide-polysilicon)
Layer structure.The material of the channel dielectric layer 122 can be silica.
Referring to FIG. 2, forming the grid line separate slot 200 for running through the initial stacked structure 110.
Patterned masking layer, the figure of the Patterned masking layer are formed in the top surface of the initial stacked structure 110
The positions and dimensions of Shape definition grid line separate slot to be formed are sequentially etched described initial using the Patterned masking layer as exposure mask
Stacked structure 110 forms the grid line separate slot 200 to semiconductor substrate 100.200 side wall of grid line separate slot exposes sacrifice
Layer 112.
Referring to FIG. 3, removing the sacrificial layer 112 along the grid line separate slot 200, formed between adjacent insulating layer
Opening 300.
The sacrificial layer 112 can be removed using wet-etching technology, specifically, the quarter that the wet-etching technology uses
Losing solution can be hot phosphoric acid solution.
After removing the sacrificial layer 112, source is formed in the semiconductor substrate 100 of 200 bottom of grid line separate slot
Doped region 201；And oxide layer 202 is formed on 100 surface of semiconductor substrate of 200 bottom of grid line separate slot.
In the specific embodiment, ion implanting is carried out to the bottom of the grid line separate slot 200, forms source dopant region 201.
The ion implanting uses n-type doping ion P.In other specific embodiments, according to the transistor in memory construction
Doping type demand, the ion implanting use p-type Doped ions B.After forming the source dopant region 201, to the grid
100 surface of semiconductor substrate of 200 bottom of line separate slot carries out oxidation processes, forms oxide layer 202.The oxidation processes can be
The oxidation technologies such as moisture-generation process in situ or thermal oxide.
Referring to FIG. 4, forming the diffusion barrier layer of covering 300 inner walls of the opening.
In the specific embodiment, the diffusion barrier layer is the two-dimentional barrier layer 301 using two-dimentional conductive material.Two dimension
The electronics of conductive material conducts in two-dimensional surface, therefore the conductivity of two-dimentional conductive material is usually above three-dimensional conductive material,
Resistance is lower, the resistance of control grid can be reduced, to reduce RC retardation ratio.
In the specific embodiment, the material on the two dimension barrier layer 301 is graphene.The electric conductivity of graphene is very high,
And have diffusion barrier effect for metallic atom, the grid atom being subsequently formed can either be stopped to external diffusion, and can reduce
Control the resistance of grid.
Chemical vapor deposition process, silicon carbide epitaxial growth method, metal catalytic epitaxial growth method or atomic layer can be used
Depositing operation forms the two dimension on barrier layer 301.The thickness on the two dimension barrier layer 301 is excessive to be will lead under electric conductivity
Drop；The thickness on the two dimension barrier layer 301 can not be too small, to avoid the lower problem of the deposition quality on two-dimentional barrier layer 301.
In the specific embodiment, the two dimension barrier layer 301 includes the two-dimensional graphene layer of 1~10 layer of monoatomic layer structure.It is described
Two-dimentional barrier layer 301 with a thickness of 0.3 nanometer to 3 nanometers.
In other specific embodiments, the two dimension barrier layer 301 can also be other two-dimentional conductive materials, such as tin
Alkene etc..In other specific embodiments, diffusion layer between the grid 302 and insulating layer 111 can also include two layers with
On two-dimentional barrier layer 301.
It is located at 301 surface of diffusion barrier layer referring to FIG. 5, being formed and fills full 300 (please referring to Fig. 4) of the opening
Grid 302.
The material of the grid 302 is W, can deposit the grid 302 using atom layer deposition process, described to ensure
The deposition quality with higher of grid 302 in opening 300 avoids the problems such as cavity occur in control grid 302.In other tools
In body embodiment, the material of the grid 302 can also be other conductions such as polysilicon, Al, Cu, Co, Ag, metal silicide
Material can also form the grid 302 using chemical vapor deposition process.
The grid 302 and two-dimensional diffusion barrier layer 301 constitute control gate layer, and the two dimension barrier layer 301 is located at institute
It states between grid 302 and channel structure 200, insulating layer 111, the control gate layer is alternately stacked to be formed and deposit with insulating layer 111
Store up stacked structure.
Referring to FIG. 6, the schematic diagram of the memory construction for another specific embodiment of the present invention.
In the specific embodiment, the diffusion barrier layer between the grid 302 and insulating layer 111 further includes metal barrier
Layer 303.The metal barrier 303 is located between the two-dimentional barrier layer 301 and grid 302.The metal barrier 303
Material is TiN, the ability of barrier metal with higher diffusion, can further avoid the metallic atom of the grid 302 to
External diffusion.In other specific embodiments, the material of the metal barrier 203 can also be include Ti, Ta, TiN, TaN,
At least one of Co, CoWP and TiW.
The metal barrier 203 can be formed using chemical vapor deposition, atom layer deposition process or sputtering technology.
In the specific implementation, after forming the two-dimentional barrier layer 301, the metal barrier 303 is formed, the grid is re-formed
302。
In other specific embodiments, the metal barrier 303 can also be located at the two-dimentional barrier layer 301 with absolutely
Between edge layer 111.In other specific embodiments, the diffusion layer between the grid 302 and insulating layer 111 can also include
Two layers or more of metal barrier 303, the two dimension barrier layer 301 can be between double layer of metal barrier layer 303.
The conductivity on the two dimension barrier layer 301 is greater than the conductivity of the metal barrier 303, also, due to described
The material on two-dimentional barrier layer 301 is two-dimensional material, and thickness is lower, compared with metal barrier, under identical blocking capability, has
Lower thickness and lower resistance can reduce RC retardation ratio and improve the process window of grid 302.
Referring to FIG. 7, forming insulation side wall in the sidewall surfaces of the grid line separate slot 200 on the basis of Fig. 5 structure
401 and fill the common source 402 of the full grid line separate slot 200.
It, can be in the side wall of the grid line separate slot 200 during forming the grid 302 and two-dimentional barrier layer 301
Surface is also deposited with grid material and two-dimentional barrier material, formed the insulation side wall 401 and common source 402 it
Before, first remove the grid material and two-dimentional barrier material in the grid line separate slot 200.
The forming method of the insulation side wall 401 and common source 402 includes: heavy in 200 inner wall surface of grid line separate slot
After product spacer material layer, using side wall etching technics, removal is located at the spacer material of 200 bottom of grid line separate slot, is formed
Cover the insulation side wall 401 of 200 sidewall surfaces of grid line separate slot；Source electrode material is filled simultaneously in the grid line separate slot 200 again
It is planarized, forms the common source 402 for filling the full grid line separate slot 200.The material of the insulation side wall 401 is oxidation
The dielectric materials such as silicon, silicon oxynitride, hafnium oxide.In the specific embodiment, the material of the common source 402 is W.Other are specific
In embodiment, the material of the common source 402 can also be other conductions such as polysilicon, Al, Cu, Co, Ag, metal silicide
Material.
In the forming method of the memory construction of above-mentioned specific embodiment, after removal sacrificial layer forms opening,
Diffusion barrier layer and grid are formed in opening as control grid.The diffusion barrier layer includes at least one layer of two-dimentional barrier layer,
The material on the two dimension barrier layer is two-dimentional conductive material, and resistance is lower, can reduce RC retardation ratio, can shorten the volume of memory
The journey time improves the performance of memory.And two-dimentional conductive material thickness is low, is capable of increasing the process window to form grid, mentions
The deposition quality of high grid.
A specific embodiment of the invention also provides a kind of memory construction.
Referring to FIG. 7, the structural schematic diagram of the memory construction for the embodiment of the invention.
The memory construction includes: semiconductor substrate 100；Storage stack knot in the semiconductor substrate 100
Structure, the storage stack structure include the insulating layer 111 being stacked with and control gate layer；Extremely through the storage stack structure
The channel structure 120 of the semiconductor substrate 100.
The semiconductor substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to device
Actual demand, can choose suitable semiconductor substrate 100, be not limited thereto.It is described partly to lead in the specific embodiment
Body substrate 100 is monocrystalline silicon wafer crystal.
The channel structure 120 includes the substrate epitaxial layer 123 and covering channel hole side wall for being formed in channel hole bottom
Functional layer 121 and positioned at 121 surface of functional layer and fill the channel dielectric layer 122 in full channel hole.The functional layer
121 further comprise barrier layer, electric charge capture layer, tunnel layer and the channel layer stacked gradually from channel hole sidewall surfaces.It should
In specific embodiment, the functional layer 121 is the composite layer knot of O-N-O-P (oxide-nitride-oxide-polysilicon)
Structure.The material of the channel dielectric layer 122 can be silica.
111 material of insulating layer can be the insulating dielectric materials such as silica.
The control gate layer include grid 302 and be located at the grid 302 and channel structure 200, insulating layer 111 it
Between diffusion barrier layer, the diffusion barrier layer includes at least one layer of two-dimentional barrier layer 301 using two-dimentional conductive material.
In the specific embodiment, the diffusion barrier layer includes a two-dimentional barrier layer 301.Due to two-dimentional conductive material
Electronics conducts in two-dimensional surface, therefore the conductivity of two-dimentional conductive material is usually above three-dimensional conductive material, and resistance is lower, can
To reduce the resistance of control grid, to reduce RC retardation ratio.
In the specific embodiment, the material on the two dimension barrier layer 301 is graphene.The electric conductivity of graphene is very high,
And have diffusion barrier effect for metallic atom, the grid atom being subsequently formed can either be stopped to external diffusion, and can reduce
Control the resistance of grid.
The thickness on the two dimension barrier layer 301 is excessive to will lead to electric conductivity decline；The thickness on the two dimension barrier layer 301
Can not be too small, to avoid the lower problem of the deposition quality on two-dimentional barrier layer 301.The two dimension barrier layer 301 includes 1~10
The two-dimensional graphene layer of layer monoatomic layer structure.It is described two dimension barrier layer 301 with a thickness of 0.3 nanometer to 3 nanometers.
In other specific embodiments, the two dimension barrier layer 301 can also be other two-dimentional conductive materials, such as tin
Alkene etc..In other specific embodiments, diffusion layer between the grid 302 and insulating layer 111 can also include two layers with
On two-dimentional barrier layer 301.
In the specific embodiment, the material of the grid 302 is W；In other specific embodiments, the grid
302 material can also be other conductive materials such as polysilicon, Al, Cu, Co, Ag, metal silicide.
The grid 302 and two-dimensional diffusion barrier layer 301 constitute control gate layer, and the two dimension barrier layer 301 is located at institute
It states between grid 302 and channel structure 200, insulating layer 111, the control gate layer is alternately stacked to be formed and deposit with insulating layer 111
Store up stacked structure.
Referring to FIG. 6, the diffusion barrier layer of the memory construction also wraps in another embodiment of the present invention
Include metal barrier 303.The metal barrier 303 is located between the two-dimentional barrier layer 301 and grid 302.The metal
The material on barrier layer 303 is TiN, and the ability of barrier metal diffusion with higher can further avoid the grid 302
Metallic atom is to external diffusion.In other specific embodiments, the material of the metal barrier 203 can also be include Ti,
At least one of Ta, TiN, TaN, Co, CoWP and TiW.
In other specific embodiments, the metal barrier 303 can also be located at the two-dimentional barrier layer 301 with absolutely
Between edge layer 111.In other specific embodiments, the diffusion layer between the grid 302 and insulating layer 111 can also include
Two layers or more of metal barrier 303.The two dimension barrier layer 301 can be between double layer of metal barrier layer 303.
The conductivity on the two dimension barrier layer 301 is greater than the conductivity of the metal barrier 303, also, due to described
The material on two-dimentional barrier layer 301 is two-dimensional material, and thickness is lower, compared with metal barrier, under identical blocking capability, has
Lower thickness and lower resistance can reduce RC retardation ratio and improve the process window of grid 302.
With continued reference to FIG. 6, the memory construction further includes common source configuration.The common source configuration is deposited through described
Stacked structure is stored up, the common source of the full grid line separate slot of insulation side wall 401 and filling including covering grid line separate slot side wall
402.In the semiconductor substrate 100 of the common source configuration bottom also have source dopant region 201, the common source configuration bottom with
Also there is oxide layer 202 between the semiconductor substrate 100.
The material of the insulation side wall 401 is the dielectric materials such as silica, silicon oxynitride, hafnium oxide.The specific embodiment party
In formula, the material of the common source 402 is W.In other specific embodiments, the material of the common source 402 can also be more
Other conductive materials such as crystal silicon, Al, Cu, Co, Ag, metal silicide.
In the memory construction of above-mentioned specific embodiment, control gate layer includes diffusion barrier layer and grid.The expansion
It dissipates barrier layer and includes at least one layer of two-dimentional barrier layer, the material on the two dimension barrier layer is two-dimentional conductive material, and resistance is lower, energy
RC retardation ratio is enough reduced, the programming time of memory can be shortened, improve the performance of memory.And two-dimentional conductive material thickness
It is low, it is capable of increasing the process window to form grid, improves the quality of grid.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (15)
1. a kind of memory construction characterized by comprising
Semiconductor substrate；
Storage stack structure in the semiconductor substrate, including the insulating layer being stacked with and control gate layer；
Through the channel structure of the storage stack structure to the semiconductor substrate；
The control gate layer includes grid and the diffusion barrier layer between the grid and channel structure, insulating layer,
The diffusion barrier layer includes at least one layer of two-dimentional barrier layer using two-dimentional conductive material.
2. memory construction according to claim 1, which is characterized in that the diffusion barrier layer further includes at least one layer of gold
Belong to barrier layer.
3. memory construction according to claim 2, which is characterized in that the two dimension barrier layer is located at the metal barrier
Between layer and grid or the metal barrier is located between the two-dimentional barrier layer and grid.
4. memory construction according to claim 2, which is characterized in that the conductivity on the two dimension barrier layer is greater than described
The conductivity of metal barrier.
5. memory construction according to claim 2, which is characterized in that the material of the metal barrier include Ti, Ta,
At least one of TiN, TaN, Co, CoWP and TiW.
6. memory construction according to claim 1 or 2, which is characterized in that the material on the two dimension barrier layer includes stone
At least one of black alkene and tin alkene.
7. memory construction according to claim 1, which is characterized in that it is described two dimension barrier layer with a thickness of 0.3 nanometer
To 3 nanometers.
8. a kind of forming method of memory construction characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate surface is formed with initial stacked structure and channel structure, the initial heap
Stack structure includes the insulating layer and sacrificial layer being successively stacked with, and the channel structure runs through the initial stacked structure；
Form the grid line separate slot for running through the initial stacked structure；
The sacrificial layer is removed along the grid line separate slot, forms the opening between adjacent insulating layer；
Form the diffusion barrier layer of the covering opening inner wall and the grid positioned at the diffusion barrier layer surface；
The diffusion barrier layer includes at least one layer of two-dimentional barrier layer using two-dimentional conductive material.
9. the forming method of memory construction according to claim 8, which is characterized in that the diffusion barrier layer further includes
At least one layer of metal barrier.
10. the forming method of memory construction according to claim 9, which is characterized in that the two dimension barrier layer is located at
Between the metal barrier and grid or the metal barrier is located between the two-dimentional barrier layer and grid.
11. the forming method of memory construction according to claim 9, which is characterized in that the electricity on the two dimension barrier layer
Conductance is greater than the conductivity of the metal barrier.
12. the forming method of memory construction according to claim 9, which is characterized in that the material of the metal barrier
Material includes at least one of Ti, Ta, TiN, TaN, Co, CoWP and TiW.
13. the forming method of memory construction according to claim 8 or claim 9, which is characterized in that the two dimension barrier layer
Material includes at least one of graphene and tin alkene.
14. the forming method of memory construction according to claim 8, which is characterized in that use chemical vapor deposition work
Skill, silicon carbide epitaxial growth method, metal catalytic epitaxial growth method or atom layer deposition process form the two-dimentional barrier layer.
15. the forming method of memory construction according to claim 8, which is characterized in that the thickness on the two dimension barrier layer
Degree is 0.3 nanometer to 3 nanometers.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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