CN107331646A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN107331646A CN107331646A CN201610274387.9A CN201610274387A CN107331646A CN 107331646 A CN107331646 A CN 107331646A CN 201610274387 A CN201610274387 A CN 201610274387A CN 107331646 A CN107331646 A CN 107331646A
- Authority
- CN
- China
- Prior art keywords
- side wall
- grid
- layer
- forming method
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes：Substrate is provided；Grid is formed on substrate；The first side wall and the second side wall are sequentially formed on the side wall of the grid, the dielectric constant of first side wall is less than the dielectric constant of second side wall；The filled media layer between the grid；Attachment plug is formed in the dielectric layer.The present invention is less than the dielectric constant of second side wall by sequentially forming the first side wall and the second side wall, the dielectric constant of first side wall on gate lateral wall.Because the dielectric constant of first side wall is smaller, therefore compared with prior art, technical solution of the present invention can effectively reduce the dielectric constant of material between the grid and attachment plug, so as to reduce the parasitic capacitance between the grid and attachment plug, improve device performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
As integrated circuit develops to super large-scale integration, the current densities of IC interior are more next
It is bigger, comprising component number it is also more and more, the size of component also reduces therewith.With half
The raceway groove of device shortens therewith in the reduction of conductor structure size, semiconductor structure.Due to channel shortening,
Gradual channel is approximately no longer set up, and highlights various unfavorable physical effects (particularly short-channel effect),
This causes device performance and reliability to degenerate, and limits the further diminution of device size.
In order to control short-channel effect, the further diminution of device size requires the further increasing of grid capacitance
Greatly.The increase of grid capacitance can be realized by the way that the thickness of gate dielectric layer is thinned.But gate medium thickness
The reduction of degree can cause the increase of grid leakage current.For suppressor grid leakage current, metal gate structure quilt
It is introduced into semiconductor structure.Metal gate structure includes metal electrode and high-K dielectric layer.Metal gates knot
Structure can effectively improve grid capacitance, while being capable of effective suppressor grid leakage current.
Meanwhile, the increase of current densities, crystal column surface can not provide enough areas to manufacture connecting line.
In order to meet interconnection line between the interconnection needs after component reduces, two layers and more than two layers of multiple layer metal
Be designed to very large scale integration technology frequently with one of method.Different metal layer or metal level
Realized between semiconductor devices by attachment plug and be connected conducting.
But the semiconductor structure formed in prior art, the parasitic capacitance between grid and attachment plug
It is excessive, it have impact on the performance of formed semiconductor structure.
The content of the invention
The present invention solve the problem of be to provide a kind of semiconductor structure and forming method thereof, with reduce grid with
Parasitic capacitance between attachment plug, improves the performance for forming semiconductor structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided；Grid is formed on substrate；The first side wall is sequentially formed on the side wall of the grid
With the second side wall, the dielectric constant of first side wall is less than the dielectric constant of second side wall；Institute
State filled media layer between grid；Attachment plug is formed in the dielectric layer.
Optionally, in the step of forming first side wall and second side wall, first side wall
Material includes fluorinated graphene or graphene, and the material of second side wall includes silica.
Optionally, in the step of forming first side wall, first side wall includes 10 layers to 30 layers fluorine
Graphite alkene.
Optionally, the material of first side wall is fluorinated graphene, the step of forming first side wall
Including：Graphene layer is formed on the gate lateral wall；Fluorination treatment is carried out to the graphene layer.
Optionally, the step of forming the graphene layer includes：In institute by way of chemical vapor deposition
State and graphene layer is formed on gate lateral wall.
Optionally, in the step of graphene layer is formed by way of chemical vapor deposition, used
Process gas include methane and hydrogen.
Optionally, in the step of carrying out fluorination treatment to the graphene, the fluorination treatment makes described the
Side within the walls fluorine atom and carbon atom atomic quantity ratio be less than 1.
Optionally, the forming method is also wrapped after the gate formation before first side wall is formed
Include：Adhesion layer is formed on the gate lateral wall；In the step of forming first side wall, described first
Side wall covers the attachment layer surface.
Optionally, in the step of forming the adhesion layer, the material of the adhesion layer includes germanium silicon.
Optionally, the step of forming adhesion layer includes, and the adhesion layer is formed by way of epitaxial growth.
Optionally, in the step of forming grid, the grid is dummy grid；The forming method is being formed
Formed after the dielectric layer before attachment plug, in addition to：Remove the grid formation opening；Institute
State in opening and form metal gates.
Optionally, it is also formed with adhesion layer between the grid and first side wall；Form the step of opening
Suddenly include：Carry out the first etching and remove the grid, expose the adhesion layer；The second etching is carried out to remove
The adhesion layer, exposes first side wall.
Optionally, one or two step in first etching and the described second etching includes：Using
The mode of wet etching is performed etching.
Optionally, in the step of carrying out the first etching, the grid are removed using tetramethyl ammonium hydroxide solution
Pole.
Optionally, the material of the adhesion layer includes germanium silicon；In the step of carrying out the second etching, using ammonia
Water or hydrochloric acid solution remove the adhesion layer.
Optionally, the forming method after first side wall and the second side wall is formed in filled media
Before layer, in addition to：Lightly doped drain injection is carried out to the substrate of grid both sides.
Accordingly, the present invention provides a kind of semiconductor structure, including：
Substrate；Grid on the substrate；Be sequentially located at the first side wall on the gate lateral wall and
Second side wall, the dielectric constant of first side wall is less than the dielectric constant of second side wall；It is filled in
Dielectric layer between the grid；Attachment plug in the dielectric layer.
Optionally, the material of first side wall includes fluorinated graphene or graphene, second side wall
Material include silica.
Optionally, first side wall includes 10 layers to 30 layers of fluorinated graphene.
Optionally, in first side wall of fluorinated graphene material fluorine atom and carbon atom atomic quantity
Than less than 1.
Compared with prior art, technical scheme has advantages below：
The present invention on gate lateral wall by sequentially forming the first side wall and the second side wall, first side wall
Dielectric constant be less than second side wall dielectric constant.Due to first side wall dielectric constant compared with
It is small, therefore compared with prior art, technical solution of the present invention can effectively reduce the grid and be inserted with being connected
The dielectric constant of material between plug, so as to reduce the parasitic capacitance between the grid and attachment plug, changes
Kind device performance.
In alternative of the present invention, first side wall is formed using fluorinated graphene material.The fluorination
The dielectric constant of graphene material is smaller, and with higher breakdown field strength.Therefore in same thickness
In the case of, the dielectric constant of material between grid and attachment plug can be effectively reduced, reduces grid and company
Patch the parasitic capacitance between plug.And fluorinated graphene material can also keep higher at relatively high temperatures
Resistivity, therefore using fluorinated graphene material formed first side wall can also improve to be formed partly
The reliability of conductor structure.Further, fluorinated graphene material has good barrier properties, Neng Gouyou
Effect barrier metal ion extends the electric isolution performance for suppressing the influence dielectric layer into the dielectric layer.Cause
The use of this side wall of fluorinated graphene material first can improve the stability of semiconductor structure.
Brief description of the drawings
Fig. 1 is a kind of cross-sectional view of semiconductor structure；
Fig. 2 to Fig. 8 is each step intermediate structure of the embodiment of method for forming semiconductor structure one of the present invention
Diagrammatic cross-section.
Embodiment
From background technology, there is the problem of parasitic capacitance is excessive in semiconductor structure of the prior art.
The reason for its parasitic capacitance problems of too being analyzed in conjunction with semiconductor structure of the prior art：
With reference to Fig. 1, a kind of cross-sectional view of semiconductor structure is shown.
As shown in figure 1, the semiconductor structure includes substrate 10；Gold on the surface of substrate 10
Belong to and be formed with side wall 60 on grid 50, the side wall of the metal gates 50；Positioned at the metal gates 50
Source region or drain region 20 in both sides substrate 10；Metal plug 40 positioned at source region or the surface of drain region 20；Fill out
The dielectric layer 30 filled between the metal plug 40 and metal gates 50.
With the diminution of dimensions of semiconductor devices, the reduction of device channel length, the source region or drain region 20
It is less and less with the distance between the metal gates 50.So the metal plug 40 and the metal
The distance between grid 50 also reduces therewith.
Due to the side wall 60 and the material of dielectric layer 30 between metal plug 40 and the metal gates 50
Often oxide or nitride.The dielectric constant of oxide or nitride is of a relatively high, therefore metal is inserted
Parasitic capacitance C between plug 40 and the metal gates 5054Increase rapidly with the reduction of distance, shadow
The performance that semiconductor devices is formed by the semiconductor structure is rung.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided；Grid is formed on substrate；The first side wall is sequentially formed on the side wall of the grid
With the second side wall, the dielectric constant of first side wall is less than the dielectric constant of second side wall；Institute
State filled media layer between grid；Attachment plug is formed in the dielectric layer.
The present invention on gate lateral wall by sequentially forming the first side wall and the second side wall, first side wall
Dielectric constant be less than second side wall dielectric constant.Due to first side wall dielectric constant compared with
It is small, therefore compared with prior art, technical solution of the present invention can effectively reduce the grid and be inserted with being connected
The dielectric constant of material between plug, so as to reduce the parasitic capacitance between the grid and attachment plug, changes
Kind device performance.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Referring to figs. 2 to Fig. 8, show in each step of the embodiment of method for forming semiconductor structure one of the present invention
Between structure diagrammatic cross-section.
With reference to Fig. 2, substrate 100 is provided first.
The substrate 100 is used to provide operating platform for subsequent technique.The material of the substrate 100 is selected from
Monocrystalline silicon, polysilicon or non-crystalline silicon；The substrate 100 can also be selected from silicon, germanium, GaAs or germanium
The compounds such as silicon；The substrate 100 can also be other semi-conducting materials.In addition, the substrate 100
It is also selected from silicon materials on epitaxial layer or epitaxial layer.In the present embodiment, to form planar transistor
Grid structure exemplified by illustrate, therefore, the substrate 100 be monocrystalline substrate.
With continued reference to Fig. 2 there is provided the substrate 100 after, on the substrate 100 formed grid 200.
In the present embodiment, the surface of substrate 100 is also covered with protective layer 101, to prevent Subsequent semiconductor
Technique causes damage to substrate 100.Specifically, the material of the protective layer 101 is silica.Therefore
There is provided after substrate 100, before the grid 200 is formed, the forming method is additionally included in described
The surface of substrate 100 forms protective layer 101.
So, the step of forming grid 200 on the substrate 100 includes, in the protective layer
101 surfaces form the grid 200.In the present embodiment, it is to be based on high-K metal to form semiconductor structure
The semiconductor structure of grid (High-K Metal Gate, HKMG) transistor.Therefore the grid 200 is
Pseudo- grid, for defining follow-up size and the position for forming metal gates.But the grid 200 is puppet
The way of grid is only an example.In other embodiments of the invention, the grid can also be formed partly to lead
The grid of body structure.
The step of forming grid 200 includes：Gate material layers are formed on the surface of protective layer 101；
In the grid material layer surface the first patterned layer of formation, first patterned layer is described for defining
The size of grid 200 and position；Using first patterned layer as mask, the gate material layers are etched
Form grid 200.
First patterned layer can be patterned photoresist layer, using coating process and photoetching process
Formed.In addition, in order to reduce the follow-up size for forming grid structure, diminution forms semiconductor devices
Size, first patterned layer can also be formed using multiple graphical masking process.It is described multiple
Pattern mask technique includes：Self-alignment duplex pattern (Self-aligned Double Patterned, SaDP)
Technique, triple graphical (the Self-aligned Triple Patterned) techniques of autoregistration or the multigraph of autoregistration four
Shape (Self-aligned Double Double Patterned, SaDDP) technique.
With reference to Fig. 3, the first side wall 210 and the second side wall 220 are sequentially formed on the side wall of grid 200,
The dielectric constant of first side wall 210 is less than the dielectric constant of second side wall.
First side wall 210 and second side wall 220 are used to realize the electric isolution between different components.
Specifically, because the dielectric constant of first side wall 210 is less than the dielectric constant of the second side wall 220,
With in the prior art only with half guide structure of the second side wall 220 compared with, technical solution of the present invention is formed
Semiconductor structure between grid and attachment plug dielectric material dielectric constant it is smaller.Therefore it is of the invention
Technical scheme can effectively reduce the parasitic capacitance between grid and attachment plug.
Specifically, the material of first side wall 210 includes graphene or fluorinated graphene, described second
The material of side wall 220 includes silica.In the present embodiment, the material of first side wall 210 is fluorination
Graphene.The dielectric constant of fluorinated graphene material is smaller (about 1.2 or so), and fluorinated graphene
Material has higher breakdown field strength (breakdown field strength is up to 12MV/cm to 20MV/cm).
Therefore in the case of same thickness, forming first side wall 210 using fluorinated graphene material can have
Effect reduces the dielectric constant realized and be electrically isolated dielectric material, it is possible to increase the electrical insulating property between device.
In addition fluorinated graphene material can also keep higher resistivity at a higher temperature.Therefore fluorine
First side wall 210 of graphite alkene material can also improve the reliability of formed semiconductor structure performance.
Further, fluorinated graphene material also has good barrier properties, therefore uses fluorinated graphene material
First side wall 210 of material can effectively stop that the metal ion of the metal gates subsequently formed is situated between to second
Diffusion in matter layer is so that the electric isolution performance of influence second dielectric layer, raising forms the steady of semiconductor structure
It is qualitative.
If the thickness of first side wall 210 is too thin, the work(for reducing parasitic capacitance can not be effectively realized
Energy；If the thickness of first side wall 210 is too thick, easily causes waste of material and improve technique hardly possible
Degree.In the present embodiment, first side wall 210 includes 10 layers to 30 layers of fluorinated graphene.
Because the material of first side wall 210 is fluorinated graphene, therefore form first side wall 210
The step of include：First graphene layer is formed on the side wall of grid 200；The graphene layer is entered again
Row fluorination treatment.
Specifically, the step of graphene layer is formed on the side wall of grid 200 includes：Pass through chemical gas
Mutually the mode of deposition forms graphene layer on the side wall of grid 200.In the present embodiment, pass through chemistry
In the step of mode of vapour deposition forms graphene layer on the side wall of grid 200, the work used
Skill gas includes methane and hydrogen, and technological temperature is at 950 DEG C or so.
After the graphene layer is formed, fluorination treatment is carried out to the graphene layer, to form fluorination
First side wall 210 of graphene.Specifically, to the graphene by way of fluorine plasma doping
Layer is fluorinated.
If Funing tablet is too high in the fluorinated graphene material, waste of material is easily caused, increases work
Skill difficulty.Therefore in the present embodiment, in the first side wall 210 of the fluorinated graphene, the fluorine atom
It is less than 1 with the atomic quantity ratio of carbon atom.
Specifically, during carrying out fluorination treatment to the graphene layer, the process gas bag used
Carbon tetrafluoride is included, gas pressure is about 5mTorr, and technological temperature is at 200 DEG C or so；Carry out fluorination treatment
Time in the range of 40min to 60min.
It should be noted that the company in order to improve formed first side wall 210 and the grid 200
Intensity is connect there is provided the quality for forming the first side wall 210, the grid 200 is being formed in the present embodiment
Afterwards, before first side wall 210 is formed, the sidewall surfaces of grid 200 is additionally included in and are formed
Adhesion layer 211.Therefore in the step of forming the first side wall 210, first side wall 210 covers institute
State the surface of adhesion layer 211.
The adhesion layer 210 as first side wall 210 growth substrates.It is described in the present embodiment
The material of first side wall 210 is fluorinated graphene, therefore the material of the adhesion layer 211 includes germanium silicon material
Material.It can effectively be improved and be formed on the surface of adhesion layer 211 using the adhesion layer 211 of germanium silicon material
Graphene layer quality, the fault of construction of the graphene layer is reduced, so as to improve fluorographite
The performance of first side wall 210 of alkene material.Specifically, can be by way of epitaxial growth in the grid
The adhesion layer 211 of the sidewall surfaces formation germanium silicon material of pole 200.The thickness of the adhesion layer 211 is more than
Second side wall 220 is additionally operable to protect the channel region in the substrate 100, it is to avoid follow-up half
Semiconductor process causes damage to the raceway groove of formed semiconductor structure, is also used for reducing forming semiconductor junction
The appearance of structure source region and drain region punch through.So second side wall 220 and gate electrode side in existing structure
Wall is similar, can be the side wall that is formed by the dielectric material such as silica or silicon nitride or by aoxidizing
The side wall of the laminated construction such as layer-nitride-oxide formation.
Specifically, the step of forming the second side wall 220 includes：Formed the covering substrate 100 with
And the spacer material layer on the surface of grid 200；Removed by way of anisotropic dry etch described
Spacer material layer on the surface of substrate 100 and the top surface of the grid 200, forms and is located at the grid
The second side wall 220 on the side wall of pole 200.
With reference to Fig. 4, the filled media layer 300 between the grid 200.
It should be noted that after second side wall 220 is formed, filling the dielectric layer 300
Before, the forming method also includes：Lightly doped drain is carried out to the substrate 100 of the both sides of grid 200
Inject (Lightly Doped Drain, LDD).Lightly doped drain injection can be in the surface shape of substrate 100
Into amorphous state, Doped ions are combined with beneficial to shallow junction is maintained with surface amorphous, are conducive to suppressing raceway groove leakage
Electric current.
The dielectric layer 300 is used to realize device isolation.In the present embodiment, the material of the dielectric layer 300
Expect for silica.Therefore first side wall 210, second side wall 220 and the dielectric layer are passed through
300 realize the way that device is electrically isolated, and can reduce the dielectric constant of electric isolution dielectric material between device, subtract
Parasitic capacitance between small grid and attachment plug, improves the performance for forming semiconductor structure.
The dielectric layer 300 can be formed by way of chemical vapor deposition between the grid 200.
With the reduction of device size, the size in gap accordingly reduces between the adjacent grid 200 so that phase
The depth-to-width ratio increase in gap between the adjacent grid 200, in order that the dielectric layer 300 can be filled out fully
In the gap filled between the adjacent grid 200, the present embodiment, it is vapor-deposited by fluid chemistry
The mode of (Flowable Chemical Vapor Deposition, FCVD) forms the dielectric layer 300.
With reference to Fig. 5 to Fig. 8, attachment plug 500 is formed in the dielectric layer 300.
It is the semiconductor based on high-K metal gate transistor due in the present embodiment, forming semiconductor structure
In structure, the step of forming grid 200, the grid 200 is dummy grid.Therefore institute is being formed
State after dielectric layer 300, before attachment plug 500 is formed, the forming method also includes：Remove
The grid 200 is (as shown in Figure 4) to form metal gates 400 (as shown in Figure 7).
With reference to Fig. 5 to Fig. 7, the formation of the metal gates 400 is described in detail.
Combine first and refer to Fig. 5, remove the formation of grid 200 opening 310.
Before the grid 200 is removed, in the present embodiment, the forming method also includes：To described
Dielectric layer 300 carries out planarization process, to expose the top surface of the grid 200 (Fig. 4).Specifically
, planarization process can be carried out to the dielectric layer 300 by way of cmp.
In the present embodiment, adhesion layer 211 is also formed between the grid 200 and first side wall 210,
Therefore the step of forming the opening 310 includes：Carry out the first etching and remove the grid 200, expose institute
State adhesion layer 211；Carry out the second etching and remove the adhesion layer 211, expose first side wall 210.
One or two step in first etching and the described second etching includes：Using wet etching
Mode perform etching.In the present embodiment, first etching and the described second etching are carved using wet method
The mode of erosion is carried out.
Specifically, the present embodiment, the material of the grid 200 is polysilicon.Therefore wet etching is used
Mode carry out it is described first etching the step of in, TMAH can be used
(Tetramethylammonium hydroxide, TMAH) solution removes the grid 200.The attachment
Layer 211 material be germanium silicon, so using carried out by the way of wet etching it is described second etching the step of in,
Ammonia can be used for water (NaH4) or hydrochloric acid (HCl) removes the adhesion layer 211 OH.
Then, with reference to Fig. 6 and Fig. 7, metal gates 400 are formed in the opening 310.
It should be noted that in the present embodiment, the semiconductor structure formed is brilliant based on high-K metal gate
The semiconductor structure of body pipe.Therefore before metal gates 400 are formed, the forming method also includes：
Gate dielectric layer 410 is formed in 310 bottoms of the opening.
As shown in fig. 6, the gate dielectric layer 410 includes oxide layer 411 and high-K dielectric layer 412.Institute
The step of to form gate dielectric layer 410, is sequentially located at the oxidation on the surface of substrate 100 including being formed
Nitride layer 411 and high-K dielectric layer 412.
There is provided after substrate 100, formed before grid 200, the forming method is additionally included in the lining
The surface of bottom 100 forms the protective layer 101 of silica material.Therefore remove after the grid 200, it is described to open
Expose the surface of the protective layer 101 in 310 bottoms of mouth.In the present embodiment, using the protective layer 101
It is used as oxide skin(coating) 411.This way can simplify processing step, improve producing efficiency.
But in other embodiments of the present invention, can also when removing the grid and forming the opening,
The bottom of the opening is set to expose the surface of the substrate；Re-form institute in the open bottom again afterwards
State oxide layer.
The material of the high-K dielectric layer 412 includes the material that dielectric constant is more than 3.9, specifically includes oxygen
Change hafnium, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide
Titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminum oxide etc..
In the present embodiment, before the high-K dielectric layer 412 is formed, in addition to the opening 310
The oxide layer 411 that bottom is exposed is passivated processing.In the table of oxide skin(coating) 411 of passivated processing
Face, which forms high-K dielectric layer 412, can reduce the defect in the high-K dielectric layer 412, improve the height
The performance of K dielectric layer.Specifically, the plasma for including halogen can be used to the oxide skin(coating)
It is passivated processing.
It should be noted that in the present embodiment, the high-K dielectric layer 412 also covers the opening 310
Side wall.
With reference to Fig. 7, the filling metal material formation metal gates 400 in the opening 310.
Specifically, the metal material can include aluminium, copper, silver, gold, platinum, nickel, titanium, titanium nitride,
Nitrogenize thallium, thallium, carbonization thallium, nitrogen silication thallium, tungsten, tungsten nitride, the one or more of tungsten silicide.Formed
The method of the metal gates 400 is the known technology of those skilled in the art, be will not be described in detail herein.
With reference to Fig. 8, after metal gates 400 are formed, attachment plug is formed in the dielectric layer 300
500。
The attachment plug 500 is used to realize the electrical connection between different layers metal or different layer devices.
Specifically, the step of forming attachment plug 500 includes：The is formed on the surface of dielectric layer 300
Two patterned layers, the second graphical layer is used for the positions and dimensions for defining the attachment plug 500；
With second graphical layer for mask, the dielectric layer 300 is etched, is formed in the dielectric layer 300
Through hole；Conductive material is filled into the through hole, to form attachment plug 500.
The present invention on gate lateral wall by sequentially forming the first side wall and the second side wall, first side wall
Dielectric constant be less than second side wall dielectric constant.Due to first side wall dielectric constant compared with
It is small, therefore compared with prior art, technical solution of the present invention can effectively reduce the grid and be inserted with being connected
The dielectric constant of material between plug, so as to reduce the parasitic capacitance between the grid and attachment plug, changes
Kind device performance.
Accordingly, the present invention also provides a kind of semiconductor structure, including：
Substrate；Grid on the substrate；Be sequentially located at the first side wall on the gate lateral wall and
Second side wall, the dielectric constant of first side wall is less than the dielectric constant of second side wall；It is filled in
Dielectric layer between the grid；Attachment plug in the dielectric layer.
With reference to Fig. 8, the cross-sectional view of the embodiment of semiconductor structure one of the present invention is shown.
As shown in figure 8, the semiconductor structure includes：Substrate 100.
The substrate 100 is used to provide operating platform for subsequent technique.The material of the substrate 100 is selected from
Monocrystalline silicon, polysilicon or non-crystalline silicon；The substrate 100 can also be selected from silicon, germanium, GaAs or germanium
The compounds such as silicon；The substrate 100 can also be other semi-conducting materials.In addition, the substrate 100
It is also selected from silicon materials on epitaxial layer or epitaxial layer.In the present embodiment, to form planar transistor
Grid structure exemplified by illustrate, therefore, the substrate 100 be monocrystalline substrate.
Grid on the substrate 100.
In the present embodiment, the surface of substrate 100 is also covered with protective layer 101, to prevent Subsequent semiconductor
Technique causes damage to substrate 100.Specifically, the material of the protective layer 101 is silica.Therefore
The grid is located at the surface of the protective layer 101.
In the present embodiment, formed semiconductor structure be based on high-K metal gate (High-K Metal Gate,
HKMG) the semiconductor structure of transistor.Therefore the grid is metal gates 400.So the metal
Also there is gate dielectric layer 410 between grid 400 and the substrate 100.The gate dielectric layer 410 include according to
Secondary oxide layer 411 and high-K dielectric layer 412 positioned at the surface of substrate 100.
In the present embodiment, protective layer 101 of the surface of substrate 100 covered with oxide material.So this
Using the conduct of the protective layer 101 between the metal gates 400 and the substrate 100 in embodiment
The oxide layer 411 of the metal gates 400.
It should be noted that in order to reduce the defect in the high-K dielectric layer 412, improving the high K
The performance of dielectric layer, the oxide layer 411 is passivated oxide layer.Specifically, the oxide layer 411
For the oxide layer of passivated plasma passivation, wherein the passivation plasma includes halogen.
The material of the high-K dielectric layer 412 includes the material that dielectric constant is more than 3.9, specifically includes oxygen
Change hafnium, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide
Titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminum oxide etc..
The material of the metal gates 400 can include aluminium, copper, silver, gold, platinum, nickel, titanium, nitridation
Titanium, nitridation thallium, thallium, carbonization thallium, nitrogen silication thallium, tungsten, tungsten nitride, the one or more of tungsten silicide.
The semiconductor structure also includes：It is sequentially located at the first side wall 210 on the side wall of grid 200
With the second side wall 220, the dielectric constant of first side wall 210 is less than the dielectric of second side wall 220
Constant.
First side wall 210 and second side wall 220 are used to realize the electric isolution between different components.
Specifically, because the dielectric constant of first side wall 210 is less than the dielectric constant of the second side wall 220,
With in the prior art only with half guide structure of the second side wall 220 compared with, technical solution of the present invention is formed
Semiconductor structure between grid and attachment plug dielectric material dielectric constant it is smaller.Therefore it is of the invention
Technical scheme can effectively reduce the parasitic capacitance between grid and attachment plug.
Specifically, the material of first side wall 210 includes graphene or fluorinated graphene, described second
The material of side wall 220 includes silica.In the present embodiment, the material of first side wall 210 is fluorination
Graphene.The dielectric constant of fluorinated graphene material is smaller (about 1.2 or so), and fluorinated graphene
Material has higher breakdown field strength (breakdown field strength is up to 12MV/cm to 20MV/cm).
Therefore in the case of same thickness, forming first side wall 210 using fluorinated graphene material can have
Effect reduces the dielectric constant realized and be electrically isolated dielectric material, it is possible to increase the electrical insulating property between device.
In addition fluorinated graphene material can also keep higher resistivity at a higher temperature.Therefore fluorine
First side wall 210 of graphite alkene material can also improve the reliability of formed semiconductor structure performance.
Further, fluorinated graphene material also has good barrier properties, therefore uses fluorinated graphene material
First side wall 210 of material can effectively stop that the metal ion of the metal gates subsequently formed is situated between to second
Diffusion in matter layer is so that the electric isolution performance of influence second dielectric layer, raising forms the steady of semiconductor structure
It is qualitative.
If the thickness of first side wall 210 is too thin, the work(for reducing parasitic capacitance can not be effectively realized
Energy；If the thickness of first side wall 210 is too thick, easily causes waste of material and improve technique hardly possible
Degree.In the present embodiment, first side wall 210 includes 10 layers to 30 layers of fluorinated graphene.
If Funing tablet is too high in the fluorinated graphene material, waste of material is easily caused, increases work
Skill difficulty.Therefore in the present embodiment, in the first side wall 210 of the fluorinated graphene, the fluorine atom
It is less than 1 with the atomic quantity ratio of carbon atom.
It should be noted that second side wall 220 is additionally operable to protect the channel region in the substrate 100
Domain, it is to avoid Subsequent semiconductor technique causes damage to the raceway groove of formed semiconductor structure, is also used for reducing
The appearance of formed semiconductor structure source region and drain region punch through.
It is filled in the dielectric layer 300 between the grid 200.
It should be noted that in the present embodiment, the semiconductor structure also includes being located at the grid 200
Lightly doped district 310 in the substrate of both sides.Be formed with amorphous state in the lightly doped district 310, Doped ions with
Surface amorphous combination can effectively suppress channel leakage stream.
The dielectric layer 300 is used to realize device isolation.In the present embodiment, the material of the dielectric layer 300
Expect for silica.Therefore first side wall 210, second side wall 220 and the dielectric layer are passed through
330 realize the way that device is electrically isolated, and can reduce the dielectric constant of electric isolution dielectric material between device, subtract
Parasitic capacitance between small grid and attachment plug, improves the performance for forming semiconductor structure.
Attachment plug 500 in the dielectric layer 300.
Specifically, the attachment plug 500 is used to realize between different layers metal or different layer devices
Electrical connection.The material of the attachment plug 500 be conductive material, specifically can include aluminium, copper, silver,
Gold, platinum, nickel, titanium, titanium nitride, nitridation thallium, thallium, carbonization thallium, nitrogen silication thallium, tungsten, tungsten nitride,
The one or more of tungsten silicide.
To sum up, the present invention is on gate lateral wall by sequentially forming the first side wall and the second side wall, and described the
The dielectric constant of one side wall is less than the dielectric constant of second side wall.Due to the dielectric of first side wall
Constant is smaller, therefore compared with prior art, technical solution of the present invention can effectively reduce the grid with
The dielectric constant of material between attachment plug, so as to reduce the parasitism electricity between the grid and attachment plug
Hold, improve device performance.In addition in alternative of the present invention, form described using fluorinated graphene material
First side wall.The dielectric constant of the fluorinated graphene material is smaller, and with higher breakdown potential field strength
Degree.Therefore in the case of same thickness, the dielectric of material between grid and attachment plug can be effectively reduced
Constant, reduces the parasitic capacitance between grid and attachment plug.And fluorinated graphene material can also be
Higher resistivity is kept under higher temperature, therefore first side wall is formed using fluorinated graphene material
The reliability of formed semiconductor structure can also be improved.Further, fluorinated graphene material has good
Barrier properties, effectively the suppression influence medium can be extended into the dielectric layer by barrier metal ion
The electric isolution performance of layer.Therefore the use of the side wall of fluorinated graphene material first can improve semiconductor structure
Stability.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
Substrate is provided；
Grid is formed on substrate；
The first side wall and the second side wall, Jie of first side wall are sequentially formed on the side wall of the grid
Electric constant is less than the dielectric constant of second side wall；
The filled media layer between the grid；
Attachment plug is formed in the dielectric layer.
2. forming method as claimed in claim 1, it is characterised in that form first side wall and described the
In the step of two side walls, the material of first side wall includes fluorinated graphene or graphene, and described the
The material of two side walls includes silica.
3. forming method as claimed in claim 2, it is characterised in that in the step of forming first side wall,
First side wall includes 10 layers to 30 layers fluorinated graphene.
4. forming method as claimed in claim 2, it is characterised in that the material of first side wall is fluorination
Graphene, the step of forming first side wall includes：
Graphene layer is formed on the gate lateral wall；
Fluorination treatment is carried out to the graphene layer.
5. forming method as claimed in claim 4, it is characterised in that the step of forming the graphene layer is wrapped
Include：By way of chemical vapor deposition graphene layer is formed on the gate lateral wall.
6. forming method as claimed in claim 5, it is characterised in that the shape by way of chemical vapor deposition
Into in the step of the graphene layer, the process gas used includes methane and hydrogen.
7. forming method as claimed in claim 4, it is characterised in that fluorination treatment is carried out to the graphene
The step of in, the fluorination treatment makes the atomic quantity ratio of fluorine atom and carbon atom in first side wall
Less than 1.
8. forming method as claimed in claim 1, it is characterised in that the forming method formed grid it
Afterwards before first side wall is formed, in addition to：Adhesion layer is formed on the gate lateral wall；
In the step of forming first side wall, first side wall covers the attachment layer surface.
9. forming method as claimed in claim 8, it is characterised in that in the step of forming the adhesion layer,
The material of the adhesion layer includes germanium silicon.
10. forming method as claimed in claim 8, it is characterised in that the step of forming adhesion layer includes, leads to
The mode for crossing epitaxial growth forms the adhesion layer.
11. forming method as claimed in claim 1, it is characterised in that in the step of forming grid, the grid
Extremely dummy grid；The forming method after forming the dielectric layer before attachment plug is formed, also
Including：
Remove the grid formation opening；
Metal gates are formed in said opening.
12. forming method as claimed in claim 11, it is characterised in that the grid and first side wall it
Between be also formed with adhesion layer；
The step of forming opening includes：
Carry out the first etching and remove the grid, expose the adhesion layer；
Carry out the second etching and remove the adhesion layer, expose first side wall.
13. forming method as claimed in claim 12, it is characterised in that first etching and second quarter
One or two step in erosion includes：Performed etching by the way of wet etching.
14. forming method as claimed in claim 13, it is characterised in that in the step of carrying out the first etching, adopt
The grid is removed with tetramethyl ammonium hydroxide solution.
15. forming method as claimed in claim 13, it is characterised in that the material of the adhesion layer includes germanium silicon；
In the step of carrying out the second etching, the adhesion layer is removed using ammoniacal liquor or hydrochloric acid solution.
16. forming method as claimed in claim 1, it is characterised in that the forming method is forming described the
After one side wall and the second side wall before filled media layer, in addition to：The substrate of grid both sides is entered
Row lightly doped drain injects.
17. a kind of semiconductor structure, it is characterised in that including：
Substrate；
Grid on the substrate；
It is sequentially located at the first side wall and the second side wall on the gate lateral wall, the dielectric of first side wall
Constant is less than the dielectric constant of second side wall；
It is filled in the dielectric layer between the grid；
Attachment plug in the dielectric layer.
18. semiconductor structure as claimed in claim 17, it is characterised in that the material of first side wall includes
Fluorinated graphene or graphene, the material of second side wall include silica.
19. semiconductor structure as claimed in claim 18, it is characterised in that first side wall includes 10 layers
To 30 layers of fluorinated graphene.
20. semiconductor structure as claimed in claim 18, it is characterised in that described the of fluorinated graphene material
Side within the walls fluorine atom and carbon atom atomic quantity ratio be less than 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610274387.9A CN107331646A (en) | 2016-04-28 | 2016-04-28 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610274387.9A CN107331646A (en) | 2016-04-28 | 2016-04-28 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107331646A true CN107331646A (en) | 2017-11-07 |
Family
ID=60193334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610274387.9A Pending CN107331646A (en) | 2016-04-28 | 2016-04-28 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107331646A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109003985A (en) * | 2018-08-07 | 2018-12-14 | 长江存储科技有限责任公司 | Memory construction and forming method thereof |
| CN109860209A (en) * | 2019-02-28 | 2019-06-07 | 深圳市华星光电半导体显示技术有限公司 | The production method and TFT substrate of TFT substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9287403B1 (en) * | 2014-12-05 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET and method for manufacturing the same |
-
2016
- 2016-04-28 CN CN201610274387.9A patent/CN107331646A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9287403B1 (en) * | 2014-12-05 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET and method for manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| KUAN-L HO ET AL.: "Fluorinated Graphene as High Performance Dielectric Materials and the Application for Graphene Nanoelectronics", 《SCIENTIFIC REPORTS 4:5893》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109003985A (en) * | 2018-08-07 | 2018-12-14 | 长江存储科技有限责任公司 | Memory construction and forming method thereof |
| CN109003985B (en) * | 2018-08-07 | 2024-03-29 | 长江存储科技有限责任公司 | Memory structure and forming method thereof |
| CN109860209A (en) * | 2019-02-28 | 2019-06-07 | 深圳市华星光电半导体显示技术有限公司 | The production method and TFT substrate of TFT substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20240186372A1 (en) | Self-aligned contact air gap formation | |
| CN106057674A (en) | Shield grid groove MSOFET manufacturing method | |
| TW201916256A (en) | Method of manufacturing semiconductor device | |
| CN103871856B (en) | The forming method of metal gates | |
| KR20140133983A (en) | Semiconductor devices and methods of manufacturing the same | |
| TW201611285A (en) | Semiconductor structure and fabricating method thereof | |
| US11508726B2 (en) | Semiconductor structure with gate contact | |
| US11075212B2 (en) | Semiconductor device and method of manufacturing | |
| CN106486350A (en) | The forming method of semiconductor structure | |
| CN107039335A (en) | The forming method of semiconductor structure | |
| CN107275214A (en) | Semiconductor devices and forming method thereof | |
| CN104752215A (en) | Transistor forming method | |
| CN107039447A (en) | Memory cell and forming method thereof | |
| CN111489972B (en) | Semiconductor structure and forming method thereof | |
| US20200111899A1 (en) | Semiconductor device | |
| US20240188289A1 (en) | Semiconductor device and method of manufacturing | |
| CN107331646A (en) | Semiconductor structure and forming method thereof | |
| CN107045981A (en) | The forming method of semiconductor structure | |
| JP5654184B1 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US20220238667A1 (en) | Semiconductor structure and forming method thereof | |
| TW201423849A (en) | Method of forming semiconductor device and semiconductor device | |
| CN111384160B (en) | Manufacturing method of field effect transistor, field effect transistor and grid structure | |
| CN105826264A (en) | Method for forming semiconductor device | |
| CN105514027B (en) | Semiconductor devices and forming method thereof | |
| CN104681538B (en) | Contact hole and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171107 |
|
| RJ01 | Rejection of invention patent application after publication |