CN105514027B - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN105514027B CN105514027B CN201410553884.3A CN201410553884A CN105514027B CN 105514027 B CN105514027 B CN 105514027B CN 201410553884 A CN201410553884 A CN 201410553884A CN 105514027 B CN105514027 B CN 105514027B
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Abstract
A kind of semiconductor devices of present invention offer and forming method thereof, including：Substrate is formed, hard mask is formed in the substrate；The first etching stop layer is formed over the substrate；The second etching stop layer is formed on first etching stop layer；Dielectric layer is formed on second etching stop layer；The dielectric layer is performed etching to form contact hole, the etching stops when contact hole exposes the hard mask surface.The present invention can avoid the appearance of short circuit phenomenon between the first plug and grid, can effectively expand the window of contact hole etching technique, improve the yields in device manufacturing processes, reduce device manufacturing cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor devices and forming method thereof
Background technology
With the continuous development of ic manufacturing technology, requirement of the people to the integrated level and performance of integrated circuit becomes
It is higher and higher.In order to improve integrated level, cost is reduced, the critical size of component constantly becomes smaller, the circuit of IC interior
Density is increasing, and this development is so that crystal column surface can not provide enough areas to make required interconnection line.
In order to meet needed for the interconnection line after critical dimension reduction, different metal layer or metal layer and substrate at present
Conducting is realized by interconnection structure.With the propulsion of technology node, the size of interconnection structure also becomes smaller and smaller.It is existing
Technology forms interconnection structure using self-registered technology.
With reference to figure 1 and Fig. 2, a kind of schematic diagram of autoregistration attachment plug forming method of the prior art is shown.Herein, with
It applies and illustrates for the attachment plug in NOR flash.
As shown in Figure 1, be initially formed substrate, the step of formation substrate, includes：Semiconductor substrate 10 is provided；Partly leading
Multiple floating booms 11 are formed in body substrate 10；Control gate material layer and hard mask 13 are formed on floating boom 11, are covered firmly with described later
Mould 13 is that control gate material layer described in mask etching forms control gate 12, and the floating boom 11 and control gate 12 constitute a combination grid
Pole；The second plug 14 is formed between adjacent combined grid later.
Etching stop layer 15 and dielectric layer 16 are formed on second plug 14 later, and with the etching stop layer 15
It is performed etching as stop-layer, to form contact hole 17 in the dielectric layer 16, the contact hole 17 is located at described second and inserts
On plug 14 and expose second plug 14.
As shown in Fig. 2, conductive material is filled into contact hole 17, to form the first plug 20.First plug 20 with
Second plug 14 matches, and realizes electrical connection.
However, being susceptible to 12 short circuit of the first plug 20 and control gate using the semiconductor devices that the prior art is formed
The problem of.
Invention content
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, reduces short between plug and grid
The problem of road.
To solve the above problems, the present invention provides a kind of method for forming semiconductor devices, include the following steps：
Substrate is formed, hard mask is formed in the substrate；The first etching stop layer is formed on the substrate；Described
The second etching stop layer is formed on first etching stop layer；Dielectric layer is formed on second etching stop layer；With described
One etching stop layer and second etching stop layer perform etching the dielectric layer as stop-layer, can expose institute to be formed
State the contact hole on hard mask surface；Conductive material is filled into the contact hole, to form the first plug.
Optionally, the step of being performed etching to the dielectric layer include：The etch rate of first etching stop layer is less than
The etch rate of second etching stop layer.
Optionally, the material identical of the hard mask and second etching stop layer.
Optionally, the material of second etching stop layer is silicon nitride, and the material of first etching stop layer is two
The silicon nitride of silica, metal or silicon doping.
Optionally, the silicon nitride of the material silicon doping of first etching stop layer, is forming first etching stopping
After layer, is formed before the second etching stop layer, further include that the silicon nitride adulterated to the silicon makes annealing treatment.
Optionally, the thickness of first etching stop layer existsIt arrivesIn range.
Optionally, the step of formation substrate includes：Semiconductor substrate is provided；It is formed on the semiconductor substrate multiple floating
Grid；Control gate is formed on the floating gate, and the hard mask is formed on the control gate, and the floating boom and control gate constitute one
Combined grid；The second plug is formed between adjacent combined grid；The dielectric layer is performed etching to form the step of contact hole
Suddenly include：The contact hole is located at the top of second plug, and exposes second plug.
Optionally, the step of the first etching stop layer of formation includes：Using chemical vapor deposition, physical vapour deposition (PVD), original
Sublayer deposits or the mode of boiler tube forms first etching stop layer.
Optionally, in the step of being performed etching to the dielectric layer, forming contact hole, second etching stop layer and institute
The etching selection ratio of the first etching stop layer is stated 3:1 to 10:In the range of 1.
Optionally, in the step of being performed etching to the dielectric layer, forming contact hole, second etching stop layer and institute
The etching selection ratio of hard mask is stated 1:1 to 10:In the range of 1.
Optionally, in the step of performing etching the dielectric layer to form contact hole, using fluoro-gas to being given an account of
Matter layer carries out dry etching, to form contact hole.
Optionally, the fluoro-gas includes one or more in CF4 or C2F2.
Optionally, it after the step of substrate is provided, is formed before the first etching stop layer, the forming method further includes：
Chemical mechanical grinding is carried out to the substrate.
The present inventor additionally provides a kind of semiconductor device structure, including：
Substrate is formed with hard mask in the substrate；The first etching stop layer in substrate；Positioned at the first etch-stop
Only the second etching stop layer on layer；Dielectric layer on the second etching stop layer；Be formed in first etching stop layer,
The first plug in second etching stop layer and dielectric layer, first plug are in contact with the hard mask.
Optionally, first etching stop layer is different from the second etching stopping layer material.
Optionally, the substrate includes：Semiconductor substrate；Multiple floating booms in semiconductor substrate；Positioned at described
Control gate on floating boom；The hard mask is formed on the control gate；The floating boom and control gate constitute a combined grid,
The second plug is formed between adjacent combined grid；First plug be located on second plug and with second plug
It is in contact.
Optionally, the material of second etching stop layer is silicon nitride, and the material of first etching stop layer is
The silicon nitride of silica, metal or silicon doping.
Optionally, the thickness of first etching stop layer existsIt arrivesIn range.
Compared with prior art, technical scheme of the present invention has the following advantages：By in the second etching stop layer and firmly
The first etching stop layer is added between mask, using first etching stop layer and the second etching stop layer as etching stop layer
Dielectric layer is performed etching, contact hole opening can be made to can be good at stopping at the top of substrate hard mask, avoid first
The appearance of short circuit phenomenon between plug and grid can effectively expand the window of contact hole etching technique, improve device manufacture
Yields in the process reduces device manufacturing cost.
Description of the drawings
Fig. 1 to Fig. 2 is a kind of schematic diagram forming autoregistration semiconductor devices in the prior art；
Fig. 3 is schematic diagram short-circuit between semiconductor devices plug and grid caused by over etching amount；
Fig. 4 to Figure 10 is the signal of each step in one embodiment of method for forming semiconductor devices provided by the present invention
Figure.
Specific implementation mode
By background technology it is found that plug is easy to generate short circuit between grid in the prior art, in conjunction with the formation of plug
Journey analyzes the reason of short circuit problem：As shown in Figure 1, formed before etching stop layer 15 in substrate, it can also be to substrate
Mechanical lapping (Chemical Mechanical Polishing, CMP) is learned, substrate surface height rises and falls after CMP, correspondingly,
The surface height of the etching stop layer 15 covered in substrate rises and falls, and the surface requirements of fluctuating use enough in contact hole etching
Over etching amount.
It is as shown in Figure 3 in the prior art, the material identical of the etching stop layer 15 and the hard mask 13, contact hole
Larger over etching amount is easy that etching is made to be difficult at the position for stopping at etching stop layer 15 in etching, but further etches simultaneously
Part hard mask 13 is eliminated, and then exposes the control gate 12 of 13 lower section of hard mask, fills conduction material to contact hole again later
When material forms plug, the plug is easy to be in contact with the control gate 12 exposed and causes short circuit, to influence device performance.This
Outside, component problem caused by this over etching amount also constrains the process window of the etching process, reduces device manufacture
Yields.
In order to solve the technical problem, the present invention provides a kind of semiconductor devices and forming method thereof, including it is as follows
Step：Substrate is formed, hard mask is formed in the substrate；The first etching stop layer is formed on the substrate；Described
The second etching stop layer is formed on one etching stop layer；Dielectric layer is formed on second etching stop layer；With described first
Etching stop layer and second etching stop layer perform etching the dielectric layer as stop-layer, with formed can expose described in
The contact hole on hard mask surface；Conductive material is filled into the contact hole, to form the first plug.
The present invention between the second etching stop layer and hard mask by adding the first etching stop layer so that etch media
When layer forms contact hole, contact hole opening can be good at stopping above hard mask, avoid eliminating too much when etching hard
The material of mask and cause problem short-circuit between the first plug and grid.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Fig. 9 is that the structure of each step in one embodiment of method for forming semiconductor devices provided by the present invention is shown
It is intended to.It should be noted that the present embodiment is illustrated by taking NOR flash as an example, the present invention should not be limited with this.
With reference to figure 4, substrate 1000 is formed, hard mask 130 is formed in the substrate 1000.
In the present embodiment, formed substrate 1000 the step of include：Semiconductor substrate 100 is provided；On a semiconductor substrate 100
Form multiple floating booms 110；Control gate 120 is formed on floating boom 110, the hard mask 130 is formed on the control gate 120,
Floating boom 110 and control gate 120 constitute a combined grid；The second plug 140 is formed between adjacent combined grid.
100 material of the semiconductor substrate is selected from monocrystalline silicon, polysilicon or non-crystalline silicon；The semiconductor substrate 100 also may be used
To be selected from silicon, germanium, GaAs or silicon Germanium compound；The semiconductor substrate 100 is also selected from epitaxial layer or epitaxial layer
Silicon-on；The semiconductor substrate 100 can also be that other semi-conducting materials, the present invention are not limited in any way this.This reality
It is silicon to apply the material of substrate 100 described in example.
In NOR flash, the floating boom 110 is used for storing information, the control gate 120 when memory device works
In data storage or erasing on control floating boom 110.In the present embodiment, the floating boom 110, control gate are formed using polysilicon
120。
It should be noted that an insulating layer (unmarked in figure) is additionally provided between the floating boom 110 and control gate 120,
For the floating boom 120 and control gate 120 to be isolated.
Formed control gate 120 the step of include：Control gate material layer is formed on the insulating layer；In the control gate material
Hard mask 130 is formed on the bed of material；It is later that control gate material layer described in mask etching forms control gate with the hard mask 130
120.In the present embodiment, the material of the hard mask 130 is silicon nitride.
The step of forming the second plug 140 include：It is formed between the combined grid that floating boom 110 and control gate 120 form
First contact hole, first contact hole expose the semiconductor substrate 100, are filled in first contact hole later conductive
Material, to form the second plug 140.
Specifically, 140 material of the second plug is one in tungsten, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper
Kind is a variety of, and the present invention is not limited in any way this.Second plug, 140 material described in the present embodiment is tungsten.
With reference to figure 5, the first etching stop layer 180 is formed in the substrate 1000.
It should be noted that in the present embodiment, after the step of forming substrate 1000, the first etching stop layer is formed
Before 180, the forming method further includes：Chemical mechanical grinding is carried out to the substrate 1000.
After chemical mechanical grinding step, first etching stop layer 180 is formed in substrate 1000.The present embodiment
In, stop-layer of first etching stop layer 180 as subsequent etching contact hole step.In the present embodiment, first quarter
It is different from etch rate during subsequent etching of the hard mask 130 to lose stop-layer 180.
The material of first etching stop layer 180 can be the silicon nitride of silica, metal or silicon doping.Specifically
Ground can pass through chemical vapor deposition (Chemical vapor deposition, CVD), physical vapour deposition (PVD) (Physical
Vapor Deposition, PVD), the mode shape of atomic layer deposition (Atomic layer deposition, ALD) or boiler tube
At first etching stop layer 180.In the present embodiment, first etching stop layer 180 is the silicon nitride of silicon doping, specifically
Ground carries out Si ion implantation to the silicon nitride and forms silicon doping after forming silicon nitride by chemical vapor deposition method
Silicon nitride, with change the first etching stop layer 180 etching characteristic.Optionally, it can also be carried out after Si ion implantation
Annealing process (such as：Spike annealing), to further change the etching characteristic of the first etching stop layer 180.
With reference to figure 6, silicon ion doped silicon nitride and etch rate relational graph are shown.Abscissa is etch period in figure,
Ordinate is silicon nitride etch amount, and what figure line 21 indicated is the etch amount of pure silicon nitride, and figure line 22 is indicated with 2KeV energy injections
The etch amount of the silicon nitride of silicon ion, what figure line 23 indicated is with the etch amount of the silicon nitride of 1KeV energy injection silicon ions, figure
What line 24 indicated is with after 1KeV energy injection silicon ions, in the etch amount of the silicon nitride by spike annealing processing.
As shown in fig. 6, under identical etch period, the etch amount for the pure silicon nitride that figure line 21 indicates is maximum, figure line 22
Secondly the etch amount of the silicon nitride with 2KeV energy injection silicon ions indicated, and is noted with what figure line 23 indicated with 1KeV energy
The etch amount for entering the silicon nitride of silicon ion is suitable, figure line 24 indicate with 1KeV energy injections silicon ion and then pass through spike
The etch amount of the silicon nitride of annealing is minimum.
That is, by adulterating silicon ion in silicon nitride, etch rate can be effectively reduced (when etch amount is with etching
Between ratio).Specifically, the etch rate of pure silicon nitride is 8 times to 9 times of the etch rate of the silicon nitride of silicon doping.Therefore
Compared with the hard mask of silicon nitride material, have by the first etching stop layer of the silicon nitride material of Si ion implantation smaller
Etch rate.In addition, by annealing the etching special efficacy of material can also be further changed, the silicon nitride of silicon doping by annealing with
Afterwards, etch rate can further decrease.
In concrete technology, the energy that silicon injection is carried out to silicon nitride, Yi Jishi can be selected according to the needs of etching process
It is no to anneal.
It should be noted that if the thickness of the first etching stop layer 180 is too small, it is difficult to form contact hole in subsequent etching
The step of in play the role of stop-layer；If the thickness of the first etching stop layer 180 is excessive, it be easy to cause the waste of material
Or increase technology difficulty.Optionally, the thickness of first etching stop layer 180 existsBetween.
With reference to figure 7, the second etching stop layer 150 is formed on first etching stop layer 180.Second etch-stop
Only layer 150 and the material of the first etching stop layer 180 are set as：In the step of subsequent etching forms contact hole, the second etching
The etch rate of stop-layer 150 is more than the etch rate of the first etching stop layer 180.
In this example, the material of the second etching stop layer 150 is silicon nitride, the material identical with hard mask 130, but this
It invents without limitation.
It should be noted that in order to enable subsequent contact hole etching preferably to stop on the first etching stop layer 180, from
And it avoids etching the excessive damage to the first etching stop layer 180, second etching stop layer 150 and first etch-stop
Only the etching selection ratio of layer 180 is 3:1 to 10:In the range of 1.
Specifically, second etching stop layer 150 can also pass through chemical vapor deposition, physical vapour deposition (PVD), atom
Layer deposition or the mode of boiler tube are formed.
It should be noted that in the present embodiment, the material phase of second etching stop layer 150 and the hard mask 130
Together, therefore, the etching selection ratio of the second etching stop layer 150 described in the etching of subsequent touch hole and the hard mask 130 is 1:
1.But the present invention is without limitation, in order to reduce consumption of the subsequent etching process to hard mask 130, optionally, contact hole
Second etching stop layer 150 described in etching is with the etching selection ratio of the hard mask 130 1:1 to 10:In the range of 1, from
And the etch amount of hard mask 130 can be reduced, and then short circuit problem can be further reduced.
With reference to figure 8, dielectric layer 160 is formed on second etching stop layer 150, for realizing device isolation.
In the present embodiment, 160 material of the dielectric layer is oxide, and the dielectric layer 160 can also be low-K dielectric material
Or ultralow K dielectric materials, such as doping silicon dioxide, organic polymer and porous material etc., the present invention do not do any limit herein
It is fixed.
The side such as atomic deposition, physical vapour deposition (PVD), chemical vapor deposition or boiler tube may be used in the dielectric layer 160
Formula is formed, and the present invention is not limited in any way this.This step is same as the prior art, and details are not described herein.
With reference to figure 9, using first etching stop layer, 180 and second etching stop layer 150 as stop-layer to being given an account of
Matter layer 160 performs etching, to form the contact hole 170 that can expose the hard mask surface.
The contact hole 170 is located at the top of second plug 140, and in the present embodiment, the contact hole 170 also exposes
Hard mask 130 on the control gate 120 adjacent with the second plug 140.
In the present embodiment, 160 technique using plasma dry etching technology of the etch media layer, using fluoro-gas
The plasma dry etching is carried out, the fluoro-gas can be CF4Or C2F2In one or several kinds.
When being performed etching using fluoro-gas, second etching stop layer 150 and first etching stop layer 180
Etching selection ratio is 3:1 to 10:1, the etching selection ratio of second etching stop layer and hard mask 130 in the substrate 1000
It is 1:1 to 10:1, stop etching so as to realize, it is not easy to which the excessive damage for causing hard mask 130 avoids short circuit.
In the present embodiment, between 10~50sccm, power exists the fluoro-gas range of flow used in etching gas
Between 100~1000W, air pressure is between 10~100mT.When being performed etching using fluoro-gas, used concrete technology ginseng
Number should be adjusted according to equipment and specific gas, and the present invention does not do any restrictions herein.
With reference to figure 10, conductive material is filled into the contact hole 170, to form the first plug 200.
One kind in tungsten, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper of first plug, 200 material or
A variety of, the present invention is not limited in any way this.
When due to contact hole etching, contact hole opening can be good at stopping at 130 top of hard mask of substrate 1000, and
Will not overetch hard mask and expose control gate 120, it is therefore, described in the interior filling conductive material into contact hole
It can be realized and be insulated with hard mask 130 between conductive material and the control gate 120, avoid the first plug 140 and grid (this reality
Apply example grid 120 in order to control) between short circuit, can effectively expand the window of contact hole etching technique, improve device yield, drop
Low device manufacturing cost.
Correspondingly, the present invention also provides a kind of semiconductor devices, with continued reference to FIG. 10, showing semiconductor device of the present invention
The schematic diagram of one embodiment of part.The semiconductor devices includes：
Substrate 1000 is formed with hard mask 130 in the substrate 1000；
First etching stop layer 180, first etching stop layer 180 are located in the substrate 1000；
Second etching stop layer 150, second etching stop layer 150 are located on the first etching stop layer 180；
Dielectric layer 160, the dielectric layer 160 are located on the second etching stop layer 150；
First plug 200, first plug 200 be formed in first etching stop layer, the second etching stop layer and
In dielectric layer, first plug 200 is in contact with the hard mask 130.
As shown in Figure 10, in the present embodiment, the substrate 1000 includes：
Semiconductor substrate 100；
Floating boom 110, the floating boom 110 are located in semiconductor substrate 100；
Control gate 120, the hard mask 130 are located on the control gate 120；
There is insulating layer (not having label in figure) between floating boom 110 and control gate 120, for the floating boom 110 and control to be isolated
Grid 120 processed, and the floating boom 110 and the control gate 120 constitute a combined grid.
Second plug 140, second plug 140 is between adjacent combined grid.
100 material of the semiconductor substrate is selected from monocrystalline silicon, polysilicon or non-crystalline silicon；The semiconductor substrate 100 also may be used
To be selected from silicon, germanium, GaAs or silicon Germanium compound；The semiconductor substrate 100 is also selected from epitaxial layer or epitaxial layer
Silicon-on；The semiconductor substrate 100 can also be that other semi-conducting materials, the present invention are not limited in any way this.This reality
It is silicon to apply the material of substrate 100 described in example.
In NOR flash, the floating boom 110 is used for storing information, the control gate 120 when memory device works
In data storage or erasing on control floating boom 110.In the present embodiment, the floating boom 110, control gate are formed using polysilicon
120。
Second plug, 140 material is one kind or more in tungsten, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper
Kind, the present invention is not limited in any way this.Second plug, 140 material described in the present embodiment is tungsten.
The material of first etching stop layer 180 can be the silicon nitride of silica, metal or silicon doping.This implementation
In example, first etching stop layer 180 is the silicon nitride of silicon doping.Specifically, after by forming silicon nitride, to described
Silicon nitride carries out the silicon nitride that Si ion implantation forms silicon doping, to change the etching characteristic of the first etching stop layer 180.It is optional
, can also be annealed to the silicon nitride of silicon doping (such as：Spike annealing), to further change the first etching stop layer
180 etching characteristic, to obtain first etching stop layer 180.
It should be noted that if the thickness of the first etching stop layer 180 is too small, it is difficult to form contact hole in subsequent etching
The step of in play the role of stop-layer；If the thickness of the first etching stop layer 180 is excessive, it be easy to cause the waste of material
Or increase technology difficulty, optionally, the thickness of first etching stop layer 180 existsBetween.
In the step of subsequent etching forms contact hole, the etch rate of the second etching stop layer 150 is more than the first etching
The etch rate of stop-layer 180.In this example, the material of the second etching stop layer 150 is silicon nitride, the material with hard mask 130
Expect identical.Compared with the hard mask 130 (or second etching stop layer 150) of silicon nitride material, by the nitridation of Si ion implantation
First etching stop layer 150 of silicon materials has a smaller etch rate (as shown in Figure 6), but hard mask of the present invention 130, the
The specific material of one etching stop layer 180 and the second etching stop layer 150 is not limited.
It should be noted that in order to enable subsequent contact hole etching preferably to stop on the first etching stop layer 180,
To avoid etching the excessive damage to the first etching stop layer 180, second etching stop layer 150 is etched with described first
The etching selection ratio of stop-layer 180 is 3:1 to 10:In the range of 1.In the present embodiment, second etching stop layer 150 and institute
The material identical of hard mask 130 is stated, therefore, the second etching stop layer 150 and the hard mask described in the etching of subsequent touch hole
130 etching selection ratio is 1:1.But the present invention is without limitation, in order to reduce subsequent etching process to hard mask 130
Consumption, optionally, the second etching stop layer 150 described in contact hole etching is with the etching selection ratio of the hard mask 130 1:1
To 10:In the range of 1, so as to reduce the etch amount of hard mask 130, and then short circuit problem can be further reduced.
160 material of the dielectric layer is oxide, and the dielectric layer 160 can also be that low-K dielectric material or ultralow K are situated between
Material, such as doping silicon dioxide, organic polymer and porous material etc., the present invention do not do any restriction herein.
First plug 200 is located on second plug 140 and is contacted with second plug 140.Described first
200 material of plug is selected from the one or more of tungsten, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, and the present invention couple first inserts
The material of plug 200 is not limited in any way.
The advantages of semiconductor devices of the present invention, is, is added between the second etching stop layer 150 and hard mask 130
One etching stop layer 180, using 180 and second etching stop layer 150 of affiliated first etching stop layer as etching stop layer to being situated between
When matter performs etching, contact hole opening can be made to can be good at stopping at 130 top of hard mask of substrate 1000, without mistake
It spends etch hardmask 130 and exposes control gate 120.Therefore, the first plug 140 and grid (grid 120 in order to control in the present embodiment)
Between can with hard mask 130 realize insulate, avoid between the first plug 140 and grid (grid 120 in order to control in the present embodiment)
Short circuit, can effectively expand the window of contact hole etching technique, improve device yield, lower device manufacturing cost.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor devices, which is characterized in that including：
Substrate is formed, hard mask is formed in the substrate；
The first etching stop layer is formed on the substrate；
The second etching stop layer is formed on first etching stop layer；
Dielectric layer is formed on second etching stop layer；
The dielectric layer is performed etching as stop-layer using first etching stop layer and second etching stop layer, with
The contact hole on the hard mask surface can be exposed by being formed, and be less than the second etching stop layer to the etch rate of the first etching stop layer
Etch rate；
Conductive material is filled into the contact hole, to form the first plug.
2. forming method as described in claim 1, which is characterized in that the material of the hard mask and second etching stop layer
Expect identical.
3. forming method as described in claim 1, which is characterized in that the material of second etching stop layer is silicon nitride,
The material of first etching stop layer is the silicon nitride of silica, metal or silicon doping.
4. forming method as claimed in claim 3, which is characterized in that the nitrogen of the material silicon doping of first etching stop layer
SiClx forms before the second etching stop layer after forming first etching stop layer, further includes the nitrogen adulterated to the silicon
SiClx is made annealing treatment.
5. forming method as described in claim 1, which is characterized in that the thickness of first etching stop layer existsIt arrivesIn range.
6. forming method as described in claim 1, which is characterized in that formed substrate the step of include：Semiconductor substrate is provided；
Multiple floating booms are formed on the semiconductor substrate；Control gate is formed on the floating gate, and the hard mask is formed in the control
On grid processed, the floating boom and control gate constitute a combined grid；
The second plug is formed between adjacent combined grid；
The step of performing etching the dielectric layer to form contact hole include：The contact hole is located at the upper of second plug
Side, and expose second plug.
7. forming method as described in claim 1, which is characterized in that formed the first etching stop layer the step of include：Using
Chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or boiler tube mode form first etching stop layer.
8. forming method as described in claim 1, which is characterized in that performed etching to the dielectric layer, form contact hole
In step, the etching selection ratio of second etching stop layer and first etching stop layer is 3:1 to 10:In the range of 1.
9. forming method as described in claim 1, which is characterized in that performed etching to the dielectric layer, form contact hole
In step, the etching selection ratio of second etching stop layer and the hard mask is 1:1 to 10:In the range of 1.
10. forming method as described in claim 1, which is characterized in that perform etching the dielectric layer to form contact hole
The step of in, using fluoro-gas to the dielectric layer carry out dry etching, to form contact hole.
11. forming method as claimed in claim 10, which is characterized in that the fluoro-gas includes CF4Or C2F2In one kind
Or it is a variety of.
12. forming method as described in claim 1, which is characterized in that after the step of providing substrate, form the first etch-stop
Only before layer, the forming method further includes：Chemical mechanical grinding is carried out to the substrate.
13. a kind of semiconductor devices, which is characterized in that including：
Substrate is formed with hard mask in the substrate；
The first etching stop layer in substrate；
The second etching stop layer on the first etching stop layer；
Dielectric layer on the second etching stop layer；
The first plug being formed in first etching stop layer, the second etching stop layer and dielectric layer, first plug
It is in contact with the hard mask, during forming the plug, is less than to the etch rate of the first etching stop layer the second quarter
Lose the etch rate of stop-layer.
14. semiconductor devices as claimed in claim 13, which is characterized in that first etching stop layer and the second etching
It is different to stop layer material.
15. semiconductor devices as claimed in claim 13, which is characterized in that the substrate includes：Semiconductor substrate；It is located at
Multiple floating booms in semiconductor substrate；Control gate on the floating boom；The hard mask is formed on the control gate；Institute
It states floating boom and control gate constitutes a combined grid, the second plug is formed between adjacent combined grid；First plug position
It is in contact on second plug and with second plug.
16. semiconductor devices as claimed in claim 13, which is characterized in that the material of second etching stop layer is nitrogen
SiClx, the material of first etching stop layer are the silicon nitride of silica, metal or silicon doping.
17. semiconductor devices as claimed in claim 13, which is characterized in that the thickness of first etching stop layer existsIt arrivesIn range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410553884.3A CN105514027B (en) | 2014-10-17 | 2014-10-17 | Semiconductor devices and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410553884.3A CN105514027B (en) | 2014-10-17 | 2014-10-17 | Semiconductor devices and forming method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN105514027A CN105514027A (en) | 2016-04-20 |
| CN105514027B true CN105514027B (en) | 2018-09-07 |
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