CN108155146B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN108155146B
CN108155146B CN201611112156.4A CN201611112156A CN108155146B CN 108155146 B CN108155146 B CN 108155146B CN 201611112156 A CN201611112156 A CN 201611112156A CN 108155146 B CN108155146 B CN 108155146B
Authority
CN
China
Prior art keywords
layer
stop layer
forming
etching stop
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611112156.4A
Other languages
Chinese (zh)
Other versions
CN108155146A (en
Inventor
张城龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201611112156.4A priority Critical patent/CN108155146B/en
Publication of CN108155146A publication Critical patent/CN108155146A/en
Application granted granted Critical
Publication of CN108155146B publication Critical patent/CN108155146B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate; forming a plurality of grid structures on the substrate, wherein the grid structures are provided with mask layers; forming a dielectric layer between the grid structures; at least one etching stop layer is covered on the dielectric layer and the mask layer in a shape-preserving manner; forming an interlayer dielectric layer on the etching stop layer; etching the interlayer dielectric layer between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening, removing the etching stop layer at the bottom of the first opening and exposing the mask layer and the dielectric layer; removing the dielectric layer at the bottom of the first opening to form a second opening exposing the substrate between the gate structures; forming a plug in the second opening. According to the technical scheme, the loss of the mask layer in the process of forming the second opening is reduced, the shoulder loss problem is improved, and the performance of the formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming higher, which makes the wafer surface unable to provide enough area to make the required interconnection lines.
In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. The interconnect structure includes an interconnect line and a plug formed within the contact hole. The plugs are connected to the semiconductor device, and the interconnection lines realize connection between the plugs, thereby constituting a circuit.
The plug in the transistor structure comprises a plug positioned on the surface of the gate structure and used for realizing the connection between the gate and an external circuit; and the plug is positioned on the surface of the source-drain doped region and used for realizing the connection between the source region or the drain region of the transistor and an external circuit.
As the size of devices is continuously reduced, the difficulty of forming plugs through direct photolithography and etching processes is increased, and therefore, a self-aligned process is introduced in the plug forming process to form contact holes. However, in the prior art, the difficulty of forming the contact hole by using a self-alignment process is high, and the performance of the semiconductor structure is easily reduced.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a substrate; forming a plurality of grid structures on the substrate, wherein the grid structures are provided with mask layers; forming a dielectric layer between the grid structures; at least one etching stop layer is covered on the dielectric layer and the mask layer in a shape-preserving manner; forming an interlayer dielectric layer on the etching stop layer; etching the interlayer dielectric layer between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening, removing the etching stop layer at the bottom of the first opening and exposing the mask layer and the dielectric layer; removing the dielectric layer at the bottom of the first opening to form a second opening exposing the substrate between the gate structures; forming a plug in the second opening.
Optionally, the step of conformally covering at least one etching stop layer on the dielectric layer and the mask layer includes: conformally covering a first etching stop layer on the dielectric layer and the mask layer; conformally covering a second etching stop layer on the first etching stop layer; in the step of forming the interlayer dielectric layer, the interlayer dielectric layer is positioned on the second etching stop layer; and in the step of forming the first opening, etching by taking the first etching stop layer and the second etching stop layer as stop layers.
Optionally, in the step of forming the first etching stop layer, a material of the first etching stop layer is different from a material of the mask layer.
Optionally, in the step of forming the gate structure, the mask layer is made of silicon nitride; in the step of forming the first etching stop layer, the first etching stop layer is made of silicon oxide or polysilicon.
Optionally, in the step of forming the first etching stop layer, the thickness of the first etching stop layer is within the range
Figure BDA0001172542040000022
To
Figure BDA0001172542040000021
Within the range.
Optionally, in the step of forming the second etching stop layer, a material of the second etching stop layer is different from a material of the first etching stop layer.
Optionally, in the step of forming the first etching stop layer, the first etching stop layer is made of silicon oxide; in the step of forming the second etching stop layer, the second etching stop layer is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, titanium nitride, boron nitride, and aluminum nitride.
Optionally, in the step of forming the second etching stop layer, the thickness of the second etching stop layer is within the range
Figure BDA0001172542040000024
To
Figure BDA0001172542040000023
Within the range.
Optionally, one or both of the step of forming the first etching stop layer and the step of forming the second etching stop layer includes: the formation is performed by means of atomic layer deposition or chemical vapor deposition.
Optionally, in the step of forming the gate structure, the thickness of the mask layer is gradually reduced along a direction in which the sidewall of the gate structure points to the center of the gate structure; or the thickness of the mask layer is gradually increased along the direction of the side wall of the gate structure to the center of the gate structure.
Optionally, in the step of forming the dielectric layer, the dielectric layer covers the mask layer; after the dielectric layer is formed and before the etching stop layer is formed, the forming method further comprises the following steps: and carrying out planarization treatment on the dielectric layer to expose the mask layer.
Accordingly, the present invention also provides a semiconductor structure comprising:
a substrate; the grid structures are positioned on the substrate, and the grid structures are provided with mask layers; at least one etching stop layer covering part of the mask layer in a shape-preserving manner; the interlayer dielectric layer is positioned on the etching stop layer; and the plug is positioned between the adjacent grid structures and penetrates through the interlayer dielectric layer and the etching stop layer.
Optionally, the etch stop layer includes: the first etching stop layer covers part of the mask layer in a shape-preserving manner; and the second etching stop layer is covered on the first etching stop layer in a shape-preserving manner.
Optionally, the material of the first etch stop layer is different from the material of the mask layer.
Optionally, the mask layer is made of silicon nitride; the first etching stop layer is made of silicon oxide or polysilicon.
Optionally, the first etch stop layer has a thickness of
Figure BDA0001172542040000032
To
Figure BDA0001172542040000031
Within the range.
Optionally, the material of the second etch stop layer is different from the material of the first etch stop layer.
Optionally, the first etching stop layer is made of silicon oxide; the second etching stop layer is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, titanium nitride, boron nitride and aluminum nitride.
Optionally, the second etch stop layer has a thickness of
Figure BDA0001172542040000034
To
Figure BDA0001172542040000033
Within the range.
Optionally, the thickness of the mask layer is gradually reduced along the direction from the side wall of the gate structure to the center of the gate structure; or the thickness of the mask layer is gradually increased along the direction of the side wall of the gate structure to the center of the gate structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the invention, at least one etching stop layer is conformally covered on the dielectric layer and the mask layer; and etching the interlayer dielectric layer positioned between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening. The at least one etching stop layer is covered on the dielectric layer and the mask layer in a shape-preserving manner, so that the thickness uniformity of the etching stop layer at the bottom of the first opening is high, the process step of removing the etching stop layer at the bottom of the first opening can be stopped on the surface of the mask layer well, the area of the mask layer exposed at the bottom of the first opening can be increased, the loss of the mask layer in the process of forming the second opening is reduced, the shoulder loss problem is improved, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-3 are schematic cross-sectional views of a semiconductor structure in accordance with various steps of a method for forming the semiconductor structure;
FIG. 4 is a schematic cross-sectional view of various steps in another method for forming a semiconductor structure;
FIG. 5 is a schematic cross-sectional view of a semiconductor structure formed in accordance with various steps of a further method of forming a semiconductor structure;
FIGS. 6-12 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIGS. 13-16 are schematic cross-sectional views illustrating steps of another embodiment of a method for forming a semiconductor structure;
fig. 17 and 18 are schematic cross-sectional views of steps of a semiconductor structure forming method according to still another embodiment of the present invention.
Detailed Description
As is apparent from the background art, the semiconductor structure in the prior art has a problem of performance degradation. The cause of the performance degradation problem is now analyzed in connection with the formation of a semiconductor structure:
fig. 1 to fig. 3 are schematic cross-sectional views illustrating steps of a semiconductor structure forming method.
Referring to fig. 1, a substrate 10 is provided; forming a plurality of gate structures 12 on the substrate 10, wherein the gate structures 12 are provided with mask layers 11; forming a dielectric layer 13 between the gate structures 12, wherein the dielectric layer 13 exposes the top of the mask layer 11; an interlayer dielectric layer 15 is formed on the dielectric layer 13 and the mask layer 11.
Referring to fig. 2, the interlayer dielectric layer 15 between the gate structures 12 is etched to form a first opening 16, and the bottom of the first opening 16 exposes the mask layer 13 and the dielectric layer 13 between adjacent gate structures 12.
Referring to fig. 3, the dielectric layer 13 of the opening 16 is removed, and a second opening 17 exposing the substrate 10 between the adjacent gate structures 12 at the bottom is formed; thereafter, a plug (not shown in the figure) is formed in said second opening 17.
As shown in fig. 2, a self-aligned etching process is adopted in the forming process of the semiconductor structure, so that in a plane parallel to the surface of the substrate 10, the size of the first opening 16 is larger than the size of the dielectric layer 13 between the adjacent gate structures 12, and therefore the bottom of the first opening 16 not only exposes the dielectric layer 13 between the adjacent gate structures 12, but also exposes a part of the mask layer 11.
Referring to fig. 4, as the device size decreases, the distance between adjacent gate structures 22 decreases, the size of the first opening 26 decreases, and the difficulty of the process for forming the first opening 26 increases. As shown in fig. 4, the bottom of the first opening 26 tends to be "concave" (as shown in region a in fig. 4), resulting in a reduced area of the bottom of the first opening 26 exposed by the mask layer 21.
The reduced area of the bottom of first opening 26 exposing masking layer 21 increases the Loss of masking layer 21 during the removal of dielectric layer 23, exacerbating the Shoulder Loss (Shoulder Loss) problem. The degradation of the shoulder loss problem may cause the plug to shift in position, which may change the distance between the plug and the gate structure 22, increase the probability of the plug shorting, and affect the performance of the formed semiconductor structure.
In order to improve the shoulder loss phenomenon in the self-aligned etching process, referring to fig. 5, in the process of forming the dielectric layer 33, the dielectric layer 33 covers the mask layer 31; forming an etching stop layer 34 on the dielectric layer 33 after forming the dielectric layer 33 and before forming the interlayer dielectric layer 35; in the process of forming the first opening 36, the etching stop layer 34 is used as a stop layer for etching, and the interlayer dielectric layer 35 and the etching stop layer between the adjacent gate structures 32 are removed to form the first opening 36.
Since the dielectric layer 33 covers the mask layer 31, the shape of the surface of the dielectric layer 33 does not correspond to the shape of the top of the mask layer 31. As shown in fig. 5, in the semiconductor structure, the thickness of the mask layer 31 gradually increases along the direction from the sidewall of the gate structure 32 to the center of the gate structure 32, that is, the surface of the formed mask layer 31 has an arc shape protruding upward.
Before the etching stop layer 34 is formed, the surface of the dielectric layer 33 is usually planarized, so that the surface of the dielectric layer 33 is planar, and thus the shape of the formed etching stop layer 34 is planar as the surface of the dielectric layer 33. Therefore, the shape of the etch stop layer 34 does not conform to the shape of the top of the mask layer 31.
Since the shape of the etching stop layer 34 is not consistent with the shape of the top of the mask layer 31, the etching stop layer 34 is used as a stop layer to perform etching, so that the formed first opening 36 can be well stopped on the etching stop layer 34. However, since the shape of the etch stop layer 34 is not consistent with the shape of the top of the mask layer 31, the thicknesses of the dielectric layer 33 and the etch stop layer 34 above the mask layer 31 are not uniform, and thus, after the etch stop layer 34 is removed to expose the dielectric layer 33, a first opening 36 having a "concave" shape is still formed, so that it is difficult to enlarge the area where the mask layer 31 is exposed, and it is difficult to improve the Shoulder Loss (Shoulder Loss) problem.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a substrate; forming a plurality of grid structures on the substrate, wherein the grid structures are provided with mask layers; forming a dielectric layer between the grid structures; at least one etching stop layer is covered on the dielectric layer and the mask layer in a shape-preserving manner; forming an interlayer dielectric layer on the etching stop layer; etching the interlayer dielectric layer between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening, removing the etching stop layer at the bottom of the first opening and exposing the mask layer and the dielectric layer; removing the dielectric layer at the bottom of the first opening to form a second opening exposing the substrate between the gate structures; forming a plug in the second opening.
In the technical scheme of the invention, at least one etching stop layer is conformally covered on the dielectric layer and the mask layer; and etching the interlayer dielectric layer positioned between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening. Because the etching stop layer of at least one layer is covered on the dielectric layer and the mask layer in a shape-preserving manner, the etching stop layer is used as the stop layer for etching, the first opening can be effectively stopped on the surface of the mask layer, the area of the mask layer exposed from the bottom of the first opening can be increased, the loss of the mask layer in the process of forming the second opening can be reduced, the problem of shoulder loss can be improved, and the performance of the formed semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 12 are schematic cross-sectional views illustrating steps of a semiconductor structure forming method according to an embodiment of the present invention.
Referring to fig. 6, a substrate 100 is provided.
The substrate 100 is used to provide a process platform.
Specifically, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the material of the substrate may also be selected from other semiconductor materials such as germanium, gallium arsenide, or silicon germanium compounds. In addition, the substrate 100 may also have an epitaxial layer or a silicon-on-epitaxial layer structure.
In this embodiment, the semiconductor structure is a planar transistor, so the substrate 100 is a planar substrate. In other embodiments of the present invention, the semiconductor structure is a fin field effect transistor, and the substrate surface may further have a discrete fin portion.
With continued reference to fig. 6, a plurality of gate structures 120 are formed on the substrate 100, the gate structures 120 having a mask layer 110 thereon.
The gate structure 120 is used to control the conduction and the shutdown of the channel in the formed semiconductor structure.
Specifically, the gate structure 120 may be a control gate structure or a floating gate structure of a memory device, or may be a gate structure of a logic device. In this embodiment, the gate structure 120 includes a gate stack (not shown) on the substrate and a gate sidewall spacer (not shown) on the sidewall of the gate stack.
The step of forming the gate structure 120 includes: forming a gate material layer on the substrate 100; forming a gate pattern layer on the gate material layer; etching the gate material layer by taking the gate pattern layer as a mask to expose the substrate 100, and forming a gate stack on the substrate 100; forming a side wall material layer on the surface of the substrate 100 and on the top and the side wall of the gate stack; and removing the side wall material layer on the substrate 100 and higher than the gate stack in a dry etching manner to form a gate side wall on the side wall of the gate stack.
In this embodiment, the semiconductor structure is a planar transistor, so the gate structures 120 are located on the surface of the planar substrate 100. In other embodiments of the present invention, the semiconductor structure may also be a fin field effect transistor, the substrate further has a fin, and the gate structure crosses over the fin and covers a portion of the top of the fin and a portion of the surface of the sidewall of the fin.
The mask layer 110 is located on the gate structure 120, and is used as an etching mask in a subsequent semiconductor process, and is also used for protecting the gate structure 120 in the subsequent semiconductor process, so as to prevent the gate structure 120 from being damaged.
In this embodiment, the mask layer 110 is made of silicon nitride. In other embodiments of the present invention, the material of the mask layer may also be silicon oxynitride and other materials with relatively high density.
Specifically, the step of forming the mask layer 110 includes: forming a groove in the dielectric layer 110, wherein the bottom of the groove exposes the top of the gate structure 120; a mask material is filled into the trench to form the mask layer 110.
It should be noted that, in the step of forming the trench, the trench is formed by removing a part of the thickness of the gate stack and the gate sidewall, so that the bottom of the trench exposes the top surfaces of the gate stack and the gate sidewall, and the mask layer 110 material filled in the trench forms a mask layer covering the gate stack and the gate sidewall.
In other embodiments of the present invention, the trench may be further formed by removing a portion of the gate stack, so that the trench is surrounded by the gate sidewall and the gate stack. Therefore, the mask layer material filled in the groove and the gate side wall higher than the gate stack form the mask layer.
In this embodiment, the thickness of the mask layer 110 is gradually reduced along the direction from the sidewall of the gate structure 120 to the center of the gate structure 120, so as to compensate for the difference in etching rate by the shape of the mask layer 110, thereby improving the shape of the formed contact hole and improving the property of the formed plug. That is, the end of the mask layer 110 away from the gate structure 120 has a convex shape at its edge, and the surface of the mask layer 110 has a concave shape facing the substrate 100.
As shown in fig. 6, a dielectric layer 130 is formed between the gate structures 120.
The dielectric layer 130 is used to realize electrical isolation between different gate structures 120 and electrical isolation between different semiconductor structures.
In this embodiment, the dielectric layer 130 is made of silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from one or more combinations of silicon nitride, silicon oxynitride, low K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or ultra-low K dielectric material (dielectric constant less than 2.5), where the low K dielectric material or the ultra-low K dielectric material includes doped silicon dioxide, organic polymer, porous material, and the like.
Specifically, the dielectric layer 130 may be formed on the substrate 100 not covered by the gate structure 120 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or furnace.
It should be noted that, after the gate structure 120 is formed and before the dielectric layer 130 is formed, the forming method further includes: source and drain doped regions (not shown) are formed in the substrate 100 on both sides of the gate structure 120. Wherein the source-drain doped region between adjacent gate structures 120 is shared by the transistors of the adjacent gate structures 120.
Referring to fig. 7, at least one etch stop layer is conformally coated over the dielectric layer 130 and the masking layer 110.
The etching stop layer is used for stopping in the subsequent process, so that the etching process can be stopped on the surface of the mask layer 110, the purpose of enlarging the area of the exposed mask layer 110 is achieved, and the shoulder loss problem is solved.
Specifically, as shown in fig. 7, in this embodiment, the step of conformally covering at least one etching stop layer on the dielectric layer 130 and the mask layer 110 includes: conformally covering a first etching stop layer 141 on the dielectric layer 130 and the mask layer 110; a second etch stop layer 142 is conformally covered on the first etch stop layer 141.
The first etch stop layer 141 and the second etch stop layer 142 are used to stop in a subsequent process. The method of adopting two etching stop layers can improve the control capability of the etching process, is beneficial to improving the control precision of the etching process, is beneficial to improving the etching effect and improving the shoulder loss problem.
The first etching stop layer 141 is conformally covered on the dielectric layer 130 and the mask layer 110; the second etch stop layer 142 conformally covers the first etch stop layer 141. The shape of the first etch stop layer 141 and the shape of the second etch stop layer 142 correspond to the shape of the mask layer 110.
Specifically, in order to enable the first etch stop layer 141 to perform a stopping function, the material of the first etch stop layer 141 is different from the material of the mask layer 110. In this embodiment, the mask layer 110 is made of silicon nitride, so the first etch stop layer 141 is made of silicon oxide. In other embodiments of the present invention, the material of the first etch stop layer may also be polysilicon.
In order to enable the second etch stop layer 142 to perform the etching stop function, the material of the second etch stop layer 142 is different from the material of the first etch stop layer 141. In this embodiment, the first etching stop layer 141 is made of silicon oxide, so the second etching stop layer 142 is made of silicon nitride. In addition, in other embodiments of the present invention, the material of the second etch stop layer may further include one or more of silicon carbide, silicon carbonitride, silicon oxynitride, titanium nitride, boron nitride, and aluminum nitride.
One or both of the step of forming the first etch stop layer 141 and the step of forming the second etch stop layer 142 includes: the formation is performed by means of atomic layer deposition or chemical vapor deposition.
In this embodiment, the first etching stop layer 141 and the second etching stop layer 142 are formed by atomic layer deposition. The first etching stop layer 141 and the second etching stop layer 142 formed by the atomic layer deposition method have good step coverage, and are beneficial to improving the consistency of the surface shapes of the formed first etching stop layer 141 and the formed second etching stop layer 142 and the mask layer 110.
It should be noted that, in other embodiments of the present invention, the first etch stop layer and the second etch stop layer may also be formed by chemical vapor deposition with good step coverage, for example, a method of plasma enhanced chemical vapor deposition.
The thickness of the first etch stop layer 141 is preferably neither too large nor too small.
If the thickness of the first etching stop layer 141 is too small, it is difficult to stop etching in the subsequent process, which is not favorable for stopping the etching process on the surface of the mask layer 110 and is not favorable for improving the problem of shoulder loss; if the thickness of the first etching stop layer 141 is too large, the material is easily wasted, and the process difficulty is increased. In this embodiment, the first etching stop layer 141 has a thickness of
Figure BDA0001172542040000102
To
Figure BDA0001172542040000101
Within the range.
The thickness of the second etch stop layer 142 is preferably neither too large nor too small.
If the thickness of the second etching stop layer 142 is too small, it is difficult to stop etching in the subsequent process, which is not favorable for stopping the etching process on the surface of the mask layer 110 and is not favorable for improving the problem of shoulder loss; if the thickness of the second etching stop layer 142 is too large, the problems of material waste and process difficulty increase are easily caused. In this embodiment, the second etch stop layer 142 has a thickness of
Figure BDA0001172542040000103
To
Figure BDA0001172542040000104
Within the range.
Referring to fig. 8, an interlayer dielectric layer 150 is formed on the etch stop layer.
The interlevel dielectric layer 150 is used to achieve electrical isolation of adjacent semiconductor structures.
The interlayer dielectric layer 150 is made of silicon oxide. In other embodiments of the present invention, the material of the interlayer dielectric layer may also be selected from one or more combinations of silicon oxynitride, a low K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low K dielectric material (dielectric constant less than 2.5), where the low K dielectric material or the ultra-low K dielectric material includes doped silicon dioxide, organic polymer, porous material, and the like.
In this embodiment, a first etching stop layer 141 and a second etching stop layer 142 are sequentially formed on the mask layer 110 and the dielectric layer 130, so in the step of forming the interlayer dielectric layer 150, the interlayer dielectric layer 150 is located on the second etching stop layer 142. Specifically, the interlayer dielectric layer 150 may be formed on the second etch stop layer 142 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or furnace tube.
Referring to fig. 9 and 10, the interlayer dielectric layer 150 between the gate structures 120 is etched using the etch stop layer as a stop layer to form a first opening 161, and the etch stop layer at the bottom of the first opening 161 is removed to expose the mask layer 110 and the dielectric layer 130.
The first opening 161 is used to expose the dielectric layer 130 between adjacent gate structures 120, and provides a process base for removing the dielectric layer 130.
In this embodiment, a first etching stop layer 141 and a second etching stop layer 142 are sequentially formed on the mask layer 110 and the dielectric layer 130, so in the step of forming the first opening 161, the first etching stop layer 141 and the second etching stop layer 142 are used as stop layers for etching.
Specifically, as shown in fig. 9, the second etching stop layer 142 is used as a stop layer to etch the interlayer dielectric layer 150 between the adjacent gate structures 120, so as to form the first opening 161; as shown in fig. 10, the second etching stop layer 142 and the first etching stop layer 141 exposed at the bottom of the first opening 161 are sequentially removed to expose the dielectric layer 130 and a portion of the mask layer 110.
As shown in fig. 9, the etching stop layer is used as a stop layer in the process of forming the first opening 161, so that the etching stop layer is exposed at the bottom of the first opening 161. In this embodiment, the second etch stop layer 142 is exposed at the bottom of the first opening 161.
And since the first etch stop layer 141 and the second etch stop layer 142 conformally cover the dielectric layer 130 and the mask layer 110, the bottom of the first opening 161 has a shape that is identical to the shape of the dielectric layer 130 and the mask layer 110.
Specifically, the step of forming the first opening 161 includes: the first opening 161 is formed by a dry etching process to expose the etch stop layer. In this embodiment, the step of forming the first opening 161 by a dry etching process includes: and etching is formed by adopting a C-F-based plasma etching or C-H-F-based plasma etching mode.
After the first opening 161 is formed, as shown in fig. 10, the etching stop layer at the bottom of the first opening 161 is removed to expose the dielectric layer 130 and a portion of the mask layer 110.
Since the etching stop layer is conformally covered on the dielectric layer 130 and the mask layer 110, the thickness uniformity of the etching stop layer exposed at the bottom of the first opening 161 is high, and thus the process of removing the etching stop layer is stopped when the surface of the mask layer 110 is exposed, thereby increasing the area of the exposed mask layer 110 and relieving the problem of shoulder loss.
In this embodiment, a first etching stop layer 141 and a second etching stop layer 142 are sequentially formed on the mask layer 110 and the dielectric layer 130. The step of removing the etch stop layer therefore comprises: and removing the second etching stop layer 142 and the first etching stop layer 141 exposed at the bottom of the first opening 161 in sequence to expose the dielectric layer 130 and the mask layer 110.
The step of removing the second etch stop layer 142 and the first etch stop layer 141 includes: the removal is performed by a dry etching process. Specifically, the step of removing the second etching stop layer 142 and the first etching stop layer 141 by a dry etching process includes: and etching by adopting a C-F based plasma etching mode or a C-H-F based plasma etching mode.
Referring to fig. 11, dielectric layer 130 at the bottom of first opening 161 (shown in fig. 10) is removed to form a second opening 163 exposing substrate 100 between gate structures 120.
The second opening 163 is used to expose the substrate 100, providing a process space for the formation of a subsequent plug.
Specifically, in this embodiment, after forming the first opening 161 (as shown in fig. 10), the dielectric layer 130 between the adjacent gate structures 120 at the bottom of the first opening 161 is removed to expose the surface of the substrate 100. The second opening 163 is enclosed by sidewalls of adjacent gate structures 120 and the substrate 100 between adjacent gate structures 120.
The step of forming the second opening 163 includes: the second opening 163 is formed by a dry etching process. Specifically, the step of forming the second opening 163 by the dry etching process includes: and etching by adopting a C-F based plasma etching or C-H-F based plasma etching mode.
Referring to fig. 12, a plug 180 is formed in the second opening 163 (shown in fig. 11).
The plug 180 is used to make a connection to an external circuit. In this embodiment, the plug 180 is connected to the substrate 100 between the adjacent gate structures 120, so as to connect the substrate 100 to an external circuit.
Specifically, the step of forming the plug 180 includes: filling a conductive material into the second opening 163, wherein the conductive material covers the interlayer dielectric layer 150; the conductive material is planarized to form the plug 180 in the second opening 163. In this embodiment, the conductive material is tungsten. In other embodiments of the present invention, the conductive material may be selected from one or more of aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, or copper.
When the first opening 161 (as shown in fig. 10) is formed, the first etching stop layer 141 and the second etching stop layer 142 which are conformally covered are provided, so that the problem of shoulder loss is effectively improved, the possibility of position offset of the plug 180 is reduced, the probability of short circuit of the plug 180 is reduced, the performance of the formed semiconductor structure is improved, and the manufacturing yield is improved.
Referring to fig. 13 to 16, schematic cross-sectional structures corresponding to steps of another embodiment of a method for forming a semiconductor structure of the present invention are shown.
The difference between this embodiment and the previous embodiment is that, as shown in fig. 13, in the step of forming the dielectric layer 230 in this embodiment, the dielectric layer 230 covers the mask layer 210.
Therefore, as shown in fig. 14, after forming the dielectric layer 230 and before forming the etch stop layer, the forming method further includes: the dielectric layer 230 is planarized to expose the mask layer 210.
In this embodiment, the dielectric layer 230 and the mask layer 210 are planarized, so that the top of the dielectric layer 230 is flush with the top of the mask layer 210.
The planarization process is used to remove the dielectric layer 230 above the mask layer 210 to expose the mask layer 210. Specifically, the step of planarization treatment may be performed by chemical mechanical polishing.
Referring to fig. 15, after planarization, a first etch stop layer 241 is conformally coated over the dielectric layer 220 and the mask layer 210; a second etch stop layer 242 is conformally covered over the first etch stop layer 241.
Because the dielectric layer 230 and the mask layer 210 are subjected to planarization processing, the surface flatness of the dielectric layer 230 and the mask layer 210 is high, and the first etching stop layer 241 and the second etching stop layer 242 which are sequentially covered in a conformal manner are flat-plate-shaped film layers. The formation of the first etching stop layer 241 and the second etching stop layer 242 in a flat plate shape can simplify the structure of the semiconductor structure, reduce the difficulty in controlling the semiconductor process, and improve the performance of the formed semiconductor structure.
Next, referring to fig. 16, an interlayer dielectric layer 250 is formed on the second etch stop layer 242; and etching the interlayer dielectric layer 250 between the adjacent gate structures 220 by using the first etching stop layer 241 and the second etching stop layer 242 as stop layers to form the plug 280.
Referring to fig. 17 and 18, schematic cross-sectional structures corresponding to respective steps of a further embodiment of a method for forming a semiconductor structure of the present invention are shown.
The present embodiment is the same as the previous embodiments, and the description of the present invention is omitted. The difference between this embodiment and the previous embodiment is that, in the step of forming the gate structure 320, the thickness of the mask layer 310 is gradually increased along the direction from the sidewall of the gate structure 320 to the center of the gate structure 320, that is, the mask layer 310 has a protrusion at the center of the gate structure 320, and the surface of the mask layer 310 has an upward "protrusion" shape.
Therefore, as shown in fig. 17, in the step of forming the etch stop layer, the shape of the etch stop layer is consistent with the surface shape of the mask layer 310, that is, the etch stop layer has a curvature in a direction away from the substrate 300.
In this embodiment, the step of forming the etching stop layer includes: conformally covering a first etching stop layer 341 on the dielectric layer 330 and the mask layer 310; a second etch stop layer 342 is conformally covered over the first etch stop layer 341. The first etch stop layer 341 and the second etch stop layer 342 each have a curvature in a direction away from the substrate 300.
As shown in fig. 18, after the etch stop layer is formed, an interlayer dielectric layer 350 is formed on the second etch stop layer 342; and etching the interlayer dielectric layer 350 between the adjacent gate structures 320 by using the first etching stop layer 341 and the second etching stop layer 342 as stop layers to form a plug 380.
Correspondingly, the invention also provides a semiconductor structure.
Referring to fig. 12, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
A substrate 100; a plurality of gate structures 120 located on the substrate 100, the gate structures 120 having a mask layer 110 thereon; at least one etching stop layer covering part of the mask layer 110 in a shape-preserving manner; an interlayer dielectric layer 150 on the etch stop layer; and a plug 180 positioned between adjacent gate structures 120 and penetrating through the interlayer dielectric layer 150 and the etch stop layer.
The substrate 100 is used to provide a process platform.
Specifically, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate may also be selected from polysilicon or amorphous silicon; the material of the substrate may also be selected from other semiconductor materials such as germanium, gallium arsenide, or silicon germanium compounds. In addition, the substrate 100 may also have an epitaxial layer or a silicon-on-epitaxial layer structure.
In this embodiment, the semiconductor structure is a planar transistor, so the substrate 100 is a planar substrate. In other embodiments of the present invention, the semiconductor structure is a fin field effect transistor, and the substrate surface may further have a discrete fin portion.
The gate structure 120 is used to control the conduction and the shutdown of the channel in the formed semiconductor structure.
Specifically, the gate structure 120 may be a control gate structure or a floating gate structure of a memory device, or may be a gate structure of a logic device. In this embodiment, the gate structure 120 includes a gate stack (not shown) on the substrate and a gate sidewall spacer (not shown) on the sidewall of the gate stack.
In this embodiment, the semiconductor structure is a planar transistor, so the gate structures 120 are located on the surface of the planar substrate 100. In other embodiments of the present invention, the semiconductor structure may also be a fin field effect transistor, the substrate further has a fin, and the gate structure crosses over the fin and covers a portion of the top of the fin and a portion of the surface of the sidewall of the fin.
The mask layer 110 is located on the gate structure 120, and is used as an etching mask in a semiconductor process and also used for protecting the gate structure 120 in a subsequent semiconductor process to prevent the gate structure 120 from being damaged.
Specifically, the material of the mask layer 110 is silicon nitride. In other embodiments of the present invention, the material of the mask layer may also be silicon oxynitride and other materials with relatively high density.
In this embodiment, the thickness of the mask layer 110 is gradually reduced along the direction from the sidewall of the gate structure 120 to the center of the gate structure 120, so as to compensate for the difference in etching rate by the shape of the mask layer 110, thereby improving the shape of the formed contact hole and improving the properties of the plug 180. That is, the end of the mask layer 110 away from the gate structure 120 has a convex shape at its edge, and the surface of the mask layer 110 has a concave shape facing the substrate 100.
In this embodiment, the semiconductor structure further includes: source and drain doped regions (not shown) in the substrate 100 on both sides of the gate structure 120. The source-drain doped region between adjacent gate structures 120 is shared by the transistors of the adjacent gate structures 120.
In addition, the semiconductor structure further includes: and the dielectric layer 130 is positioned on one side of the gate structure 120 far away from the plug 180.
The dielectric layer 130 is used to realize electrical isolation between different gate structures 120 and electrical isolation between different semiconductor structures.
In this embodiment, the dielectric layer 130 is made of silicon oxide. In other embodiments of the present invention, the material of the dielectric layer may also be selected from one or more combinations of silicon nitride, silicon oxynitride, low K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or ultra-low K dielectric material (dielectric constant less than 2.5), where the low K dielectric material or the ultra-low K dielectric material includes doped silicon dioxide, organic polymer, porous material, and the like.
The etching stop layer is used for stopping in the process of forming the plug 180, so that the etching process can be stopped on the surface of the mask layer 110, the purpose of enlarging the area of the exposed mask layer 110 is achieved, and the problem of shoulder loss is solved.
Specifically, as shown in fig. 12, the etch stop layer includes: a first etching stop layer 141 conformally covering a part of the mask layer 110; and a second etch stop layer 142 conformally covering the first etch stop layer 141.
It should be noted that the side of the gate structure 120 away from the plug 180 is further provided with a dielectric layer 130. The first etch stop layer 141 also conformally covers the dielectric layer 130.
The first etch stop layer 141 and the second etch stop layer 142 are used to stop in the process. The method of adopting two etching stop layers can improve the control capability of the etching process, is beneficial to improving the control precision of the etching process, is beneficial to improving the etching effect and improving the shoulder loss problem.
The first etching stop layer 141 is conformally covered on the dielectric layer 130 and the mask layer 110; the second etch stop layer 142 conformally covers the first etch stop layer 141. The shape of the first etch stop layer 141 and the shape of the second etch stop layer 142 correspond to the shape of the mask layer 110.
Specifically, in order to enable the first etch stop layer 141 to perform a stopping function, the material of the first etch stop layer 141 is different from the material of the mask layer 110. In this embodiment, the mask layer 110 is made of silicon nitride, so the first etch stop layer 141 is made of silicon oxide. In other embodiments of the present invention, the material of the first etch stop layer may also be polysilicon.
In order to enable the second etch stop layer 142 to perform the etching stop function, the material of the second etch stop layer 142 is different from the material of the first etch stop layer 141. In this embodiment, the first etching stop layer 141 is made of silicon oxide, so the second etching stop layer 142 is made of silicon nitride. In addition, in other embodiments of the present invention, the material of the second etch stop layer 142 may further include one or more of silicon carbide, silicon carbonitride, silicon oxynitride, titanium nitride, boron nitride, and aluminum nitride.
The thickness of the first etch stop layer 141 is preferably neither too large nor too small.
If the thickness of the first etching stop layer 141 is too small, it is difficult to stop etching in the subsequent process, which is not favorable for stopping the etching process on the surface of the mask layer 110 and is not favorable for improving the problem of shoulder loss; if the thickness of the first etching stop layer 141 is too large, the material is easily wasted, and the process difficulty is increased. In this embodiment, the first etching stop layer 141 has a thickness of
Figure BDA0001172542040000172
To
Figure BDA0001172542040000171
Within the range.
The thickness of the second etch stop layer 142 is preferably neither too large nor too small.
If the thickness of the second etching stop layer 142 is too small, the second etching stop layer is difficult to stop etching in the process, so that the etching process is not stopped on the surface of the mask layer, and the problem of shoulder loss is not improved; if the thickness of the second etching stop layer 142 is too large, the problems of material waste and process difficulty increase are easily caused. In this embodiment, the second etch stop layer 142 has a thickness of
Figure BDA0001172542040000173
To
Figure BDA0001172542040000181
Within the range.
The interlevel dielectric layer 150 is used to achieve electrical isolation of adjacent semiconductor structures.
The interlayer dielectric layer 150 is made of silicon oxide. In other embodiments of the present invention, the material of the interlayer dielectric layer may also be selected from one or more combinations of silicon oxynitride, a low K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low K dielectric material (dielectric constant less than 2.5), where the low K dielectric material or the ultra-low K dielectric material includes doped silicon dioxide, organic polymer, porous material, and the like.
In this embodiment, a first etching stop layer 141 and a second etching stop layer 142 are sequentially formed on the mask layer 110 and the dielectric layer 130, so that the interlayer dielectric layer 150 is located on the second etching stop layer 142.
The plug 180 is used to make a connection to an external circuit. In this embodiment, the plug 180 is connected to the substrate 100 between the adjacent gate structures 120, so as to connect the substrate 100 to an external circuit.
In this embodiment, the plug 180 is made of tungsten. In other embodiments of the present invention, the material of the plug 180 may also be selected from one or more of aluminum, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, or copper.
Referring to fig. 16, a schematic structural diagram of another embodiment of a semiconductor structure of the present invention is shown.
The difference between this embodiment and the previous embodiment is that, as shown in fig. 15, in this embodiment, the top surface of the mask layer 210 is a plane, that is, the thickness of the mask layer 210 is equal along the direction from the sidewall of the gate structure 220 to the center of the gate structure 220. And the top of the dielectric layer 230 is flush with the mask layer 210.
The conformally coated etch stop layer is a flat shaped film layer. Specifically, the first etching stop layer 241 and the second etching stop layer 242, which are sequentially conformally covered, are flat film layers. The formation of the first etching stop layer 241 and the second etching stop layer 242 in a flat plate shape can simplify the structure of the semiconductor structure, reduce the difficulty in controlling the semiconductor process, and improve the performance of the formed semiconductor structure.
Referring to fig. 18, a schematic diagram of a semiconductor structure in accordance with yet another embodiment of the present invention is shown.
The present embodiment is the same as the previous embodiments, and the description of the present invention is omitted. The difference between this embodiment and the previous embodiment is that in this embodiment, the thickness of the mask layer 310 gradually increases along the direction from the sidewall of the gate structure 320 to the center of the gate structure 320, that is, the mask layer 310 has a protrusion at the center of the gate structure 320, and the surface of the mask layer 310 has an upward "protrusion" shape.
The shape of the etch stop layer conforms to the shape of the surface of the mask layer 310, i.e., the etch stop layer has a curvature in a direction away from the substrate 300. Specifically, the first etching stop layer 341 conformally covers the dielectric layer 330 and the mask layer 310; the second etch stop layer 342 conformally covers the first etch stop 341. The first etch stop layer 341 and the second etch stop layer 342 each have a curvature in a direction away from the substrate 300.
In summary, in the technical solution of the present invention, at least one etching stop layer is conformally covered on the dielectric layer and the mask layer; and etching the interlayer dielectric layer positioned between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening. The at least one etching stop layer is covered on the dielectric layer and the mask layer in a shape-preserving manner, so that the thickness uniformity of the etching stop layer at the bottom of the first opening is high, the process step of removing the etching stop layer at the bottom of the first opening can be stopped on the surface of the mask layer well, the area of the mask layer exposed at the bottom of the first opening can be increased, the loss of the mask layer in the process of forming the second opening is reduced, the shoulder loss problem is improved, and the performance of the formed semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of grid structures on the substrate, wherein the grid structures are provided with mask layers, and the thickness of the mask layers is gradually reduced along the direction of the side walls of the grid structures to the center of the grid structures; or the thickness of the mask layer is gradually increased along the direction of the side wall of the grid structure to the center of the grid structure;
forming a dielectric layer between the grid structures;
at least one etching stop layer is covered on the dielectric layer and the mask layer in a shape-preserving manner;
forming an interlayer dielectric layer on the etching stop layer;
etching the interlayer dielectric layer between the grid electrode structures by taking the etching stop layer as a stop layer to form a first opening, removing the etching stop layer at the bottom of the first opening and exposing the mask layer and the dielectric layer;
removing the dielectric layer at the bottom of the first opening to form a second opening exposing the substrate between the gate structures;
forming a plug in the second opening.
2. The method of forming of claim 1, wherein conformally covering the dielectric layer and the masking layer with at least one etch stop layer comprises:
conformally covering a first etching stop layer on the dielectric layer and the mask layer;
conformally covering a second etching stop layer on the first etching stop layer;
in the step of forming the interlayer dielectric layer, the interlayer dielectric layer is positioned on the second etching stop layer;
and in the step of forming the first opening, etching by taking the first etching stop layer and the second etching stop layer as stop layers.
3. The forming method of claim 2, wherein in the step of forming the first etch stop layer, a material of the first etch stop layer is different from a material of the mask layer.
4. The method according to claim 2 or 3, wherein in the step of forming the gate structure, the mask layer is made of silicon nitride;
in the step of forming the first etching stop layer, the first etching stop layer is made of silicon oxide or polysilicon.
5. The forming method of claim 2, wherein in the step of forming the first etch stop layer, the first etch stop layer has a thickness in a range of
Figure FDA0002436716620000021
To
Figure FDA0002436716620000022
Within the range.
6. The forming method of claim 2, wherein in the step of forming the second etch stop layer, a material of the second etch stop layer is different from a material of the first etch stop layer.
7. The forming method according to claim 2 or 6, wherein in the step of forming the first etching stopper layer, a material of the first etching stopper layer is silicon oxide;
in the step of forming the second etching stop layer, the second etching stop layer is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, titanium nitride, boron nitride, and aluminum nitride.
8. The shape of claim 2The method is characterized in that in the step of forming the second etching stop layer, the thickness of the second etching stop layer is within the range of
Figure FDA0002436716620000023
To
Figure FDA0002436716620000024
Within the range.
9. The method of forming as claimed in claim 2, wherein one or both of the step of forming the first etch stop layer and the step of forming the second etch stop layer comprises: the formation is performed by means of atomic layer deposition or chemical vapor deposition.
10. The forming method of claim 1, wherein in the step of forming a dielectric layer, the dielectric layer covers the mask layer;
after the dielectric layer is formed and before the etching stop layer is formed, the forming method further comprises the following steps: and carrying out planarization treatment on the dielectric layer to expose the mask layer.
11. A semiconductor structure, comprising:
a substrate;
the gate structures are positioned on the substrate, the gate structures are provided with mask layers, and the thickness of the mask layers is gradually reduced along the direction of the side walls of the gate structures to the center of the gate structures; or the thickness of the mask layer is gradually increased along the direction of the side wall of the grid structure to the center of the grid structure;
at least one etching stop layer covering part of the mask layer in a shape-preserving manner;
the interlayer dielectric layer is positioned on the etching stop layer;
and the plug is positioned between the adjacent grid structures and penetrates through the interlayer dielectric layer and the etching stop layer.
12. The semiconductor structure of claim 11, wherein the etch stop layer comprises:
the first etching stop layer covers part of the mask layer in a shape-preserving manner;
and the second etching stop layer is covered on the first etching stop layer in a shape-preserving manner.
13. The semiconductor structure of claim 12, wherein a material of the first etch stop layer is different from a material of the mask layer.
14. The semiconductor structure of claim 12 or 13, wherein the material of the mask layer is silicon nitride; the first etching stop layer is made of silicon oxide or polysilicon.
15. The semiconductor structure of claim 12, wherein the first etch stop layer has a thickness in the range of
Figure FDA0002436716620000031
To
Figure FDA0002436716620000032
Within the range.
16. The semiconductor structure of claim 12, wherein a material of the second etch stop layer is different from a material of the first etch stop layer.
17. The semiconductor structure of claim 12 or 16, wherein the material of the first etch stop layer is silicon oxide; the second etching stop layer is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, titanium nitride, boron nitride and aluminum nitride.
18. The semiconductor structure of claim 12, in which the secondThe thickness of the etching stop layer is within
Figure FDA0002436716620000033
To
Figure FDA0002436716620000034
Within the range.
CN201611112156.4A 2016-12-02 2016-12-02 Semiconductor structure and forming method thereof Active CN108155146B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611112156.4A CN108155146B (en) 2016-12-02 2016-12-02 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611112156.4A CN108155146B (en) 2016-12-02 2016-12-02 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN108155146A CN108155146A (en) 2018-06-12
CN108155146B true CN108155146B (en) 2020-06-09

Family

ID=62467897

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611112156.4A Active CN108155146B (en) 2016-12-02 2016-12-02 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN108155146B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429059B (en) * 2019-07-12 2021-09-03 德淮半导体有限公司 Semiconductor structure and method for forming semiconductor structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551923B1 (en) * 1999-11-01 2003-04-22 Advanced Micro Devices, Inc. Dual width contact for charge gain reduction
CN1767171A (en) * 2004-10-14 2006-05-03 三星电子株式会社 Etch stop structure and manufacture method, and semiconductor device and manufacture method
CN101123208A (en) * 2006-08-10 2008-02-13 中芯国际集成电路制造(上海)有限公司 Forming method for contact hole
CN103779265A (en) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method
CN105514027A (en) * 2014-10-17 2016-04-20 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551923B1 (en) * 1999-11-01 2003-04-22 Advanced Micro Devices, Inc. Dual width contact for charge gain reduction
CN1767171A (en) * 2004-10-14 2006-05-03 三星电子株式会社 Etch stop structure and manufacture method, and semiconductor device and manufacture method
CN101123208A (en) * 2006-08-10 2008-02-13 中芯国际集成电路制造(上海)有限公司 Forming method for contact hole
CN103779265A (en) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method
CN105514027A (en) * 2014-10-17 2016-04-20 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming same

Also Published As

Publication number Publication date
CN108155146A (en) 2018-06-12

Similar Documents

Publication Publication Date Title
US8421077B2 (en) Replacement gate MOSFET with self-aligned diffusion contact
TWI524466B (en) Semiconductor structure and method for manufacturing the same
US10714343B1 (en) Semiconductor structure and method for forming same
US10050129B2 (en) Method of forming fine patterns
CN110957320B (en) Semiconductor structure, memory structure and preparation method thereof
US10410920B2 (en) Semiconductor structure and fabrication method thereof
US20220285216A1 (en) Semiconductor device with self-aligned vias
TW202236599A (en) Semiconductor device structure
KR20140034503A (en) Semiconductor device with buried gate and method for fabricating the same
US11769672B2 (en) Semiconductor structure and forming method thereof
CN109545734B (en) Semiconductor structure and forming method thereof
CN108155146B (en) Semiconductor structure and forming method thereof
CN108122824B (en) Semiconductor structure and forming method thereof
US20220115234A1 (en) Semiconductor structure and forming method thereof
CN211929495U (en) Grid structure
CN212085009U (en) Grid structure
CN112951765B (en) Semiconductor structure and forming method thereof
KR100586553B1 (en) Gate of semiconductor device and method thereof
CN113903805B (en) Semiconductor structure and forming method thereof
US7442980B2 (en) Anti-punch-through semiconductor device
CN113629144B (en) Semiconductor device and method for manufacturing the same
US11195841B2 (en) Integrated circuit and method for manufacturing the same
US20210335704A1 (en) Semiconductor structure and fabrication method thereof
TW202245137A (en) Semiconductor device
CN115440813A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant