CN110957320B

CN110957320B - Semiconductor structure, memory structure and preparation method thereof

Info

Publication number: CN110957320B
Application number: CN201811133685.1A
Authority: CN
Inventors: 巩金峰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-27
Filing date: 2018-09-27
Publication date: 2024-05-21
Anticipated expiration: 2038-09-27
Also published as: CN110957320A

Abstract

The invention provides a semiconductor structure, a memory structure and a preparation method thereof, comprising the following steps: 1) Providing a semiconductor substrate, and forming a cushion layer structure on the surface of the semiconductor substrate; forming a shallow trench isolation structure in the semiconductor substrate and the pad layer structure, and isolating a plurality of active areas which are arranged at intervals in the semiconductor substrate; 2) Forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the cushion layer structure, wherein a first opening pattern is formed in the photoresist layer; 3) Etching the bottom anti-reflection layer according to the photoresist layer to form a second opening pattern in the bottom anti-reflection layer; 4) Forming a side wall structure on the side wall of the second opening pattern; 5) And forming a filling layer in the second opening pattern outside the side wall structure. When the embedded grid word line and the bit line contact are prepared based on the semiconductor structure, the bit line contact hole is defined without a photoetching process, so that photoetching exposure offset can be avoided, and accurate alignment of the bit line contact is ensured.

Description

Semiconductor structure, memory structure and preparation method thereof

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor structure, a memory structure and a preparation method of the semiconductor structure and the memory structure.

Background

With the development of the process, the integration level of the semiconductor device is higher, the size of the semiconductor device is smaller, the process is more complex, and the cost is higher. Meanwhile, in the manufacturing process of the semiconductor device, if the characteristic shape is in error with the target value (i.e., the characteristic shape cannot be precisely aligned), the performance of the semiconductor device may be significantly adversely affected. For example, in the existing manufacturing process of the memory structure, the whole process flow has more steps and higher cost, and when the bit line contact hole is formed, the existing lithography exposure process is difficult to realize accurate alignment, so that the reliability and stability of the manufactured memory structure are lower.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure, a memory structure and a method for manufacturing the same, which are used for solving the problems of more steps, higher cost, difficulty in realizing precise alignment of bit line contact holes, and poor reliability and stability of the obtained memory structure in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor structure, including the steps of:

1) Providing a semiconductor substrate, and forming a cushion layer structure on the surface of the semiconductor substrate; forming shallow trench isolation structures in the semiconductor substrate and the pad layer structure, wherein the shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the semiconductor substrate;

2) Sequentially forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the cushion layer structure, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially overlapped from bottom to top, a first opening pattern is formed in the photoresist layer, and the first opening pattern exposes a bit line contact area needing to form bit line contact and a buried gate word line area needing to form a buried gate word line;

3) Etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer to form a second opening pattern in the bottom anti-reflection layer;

4) Forming a side wall structure on the side wall of the second opening pattern, wherein the side wall structure defines the position and the shape of the embedded grid word line region, and the second opening pattern outside the side wall structure defines the position and the shape of the bit line contact region; and

5) And forming a filling layer in the second opening pattern outside the side wall structure, wherein the removing rate of the filling layer is smaller than the removing rate of the bottom anti-reflection layer and the removing rate of the side wall structure under the same etching condition.

As a preferred embodiment of the present invention, the steps 1) and 2) further include the following steps:

Removing the cushion layer structure;

performing ion implantation in the active region to form a deep well region in the active region; and

Forming a cushion layer structure again on the surface of the semiconductor substrate after ion implantation; in step 2), the hard mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially formed on the surface of the re-formed cushion layer structure.

As a preferred embodiment of the present invention, the cushion structure includes:

a pad oxide layer located on the surface of the semiconductor substrate; and

And the pad nitride layer is positioned on the surface of the pad oxide layer.

In a preferred embodiment of the present invention, in step 2), forming the hard mask layer on the surface of the pad layer structure includes the following steps:

Forming a first hard mask layer on the surface of the cushion layer structure; and

And forming a second hard mask layer on the surface of the first hard mask layer.

The present invention also provides a semiconductor structure comprising:

A semiconductor substrate;

A pad layer structure located on the surface of the semiconductor substrate;

The shallow trench isolation structure is positioned in the semiconductor substrate and the cushion layer structure so as to isolate a plurality of active areas which are arranged at intervals in the semiconductor substrate;

The hard mask layer is positioned on the surface of the cushion layer structure;

The bottom anti-reflection coating is positioned on the surface of the hard mask layer;

A filling layer positioned in the bottom anti-reflection coating layer, wherein the filling layer defines the position and the shape of bit line contact to be formed; and

The side wall structure is positioned in the bottom anti-reflection coating and outside the filling layer, and defines the position and the shape of the embedded grid word line to be formed; wherein,

And under the same etching condition, the removal rate of the filling layer is smaller than the removal rate of the bottom anti-reflection layer and the removal rate of the side wall structure.

As a preferred embodiment of the present invention, a deep well region is further formed in the active region.

A pad oxide layer located on the surface of the semiconductor substrate;

and the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferred embodiment of the present invention, the hard mask layer includes:

the first hard mask layer is positioned on the surface of the cushion layer structure; and

And the second hard mask layer is positioned on the surface of the first hard mask layer.

The invention also provides a preparation method of the memory structure, which comprises the following steps:

4) Forming a side wall structure on the side wall of the second opening pattern, wherein the side wall structure defines the position and the shape of the embedded grid word line region, and the second opening pattern outside the side wall structure defines the position and the shape of the bit line contact region;

5) Forming a filling layer in the second opening pattern outside the side wall structure, wherein the removal rate of the filling layer is smaller than the removal rate of the bottom anti-reflection layer and the removal rate of the side wall structure under the same etching condition;

6) Etching to remove the side wall structure and the hard mask layer in the embedded grid electrode word line area so as to form a pattern channel in the bottom anti-reflection layer and the hard mask layer, wherein the pattern channel defines the position and the shape of the embedded grid electrode word line;

7) Removing the filling layer and the bottom anti-reflection layer;

8) Removing the pad layer structure at the bottom of the pattern channel, and removing the hard mask layer outside the bit line contact area;

9) Etching the semiconductor substrate according to the pattern channel to form a buried gate word line groove in the semiconductor substrate;

10 Forming a buried gate word line in the buried gate word line trench, an upper surface of the buried gate word line being lower than an upper surface of the semiconductor substrate;

11 Forming a dielectric layer in the embedded grid word line groove and on the surface of the cushion layer structure; the medium layer fills the embedded grid word line groove and covers the surface of the cushion layer structure;

12 Removing the hard mask layer of the bit line contact region and etching the semiconductor substrate to form bit line contact holes in the dielectric layer and the semiconductor substrate, wherein the bottoms of the bit line contact holes are sunk in the semiconductor substrate; and

13 Filling contact material in the bit line contact hole to form bit line contact.

Removing the cushion layer structure;

a pad oxide layer located on the surface of the semiconductor substrate; and

And the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferred embodiment of the present invention, step 7) includes the steps of:

7-1) etching to remove the bottom anti-reflection layer;

7-2) etching to remove the second hard mask layer outside the bit line contact area; and

7-3) Removing the filling layer.

As a preferred embodiment of the present invention, step 8) includes the steps of:

8-1) removing the pad layer structure at the bottom of the pattern channel;

8-2) removing the first hard mask layer outside the bit line contact region; and

8-3) Removing the second hard mask layer of the bit line contact region.

As a preferred embodiment of the present invention, the step 10) includes the steps of:

10-1) forming a gate oxide layer on the side wall and the bottom of the embedded gate word line groove;

10-2) forming a gate conductive layer in the buried gate word line trench and on the surface of the pad structure, wherein the gate conductive layer fills up a gap between the buried gate word line trench and the bit line contact region and covers the reserved hard mask layer;

10-3) removing part of the gate conductive layer by adopting a chemical grinding process, so that the upper surface of the reserved gate conductive layer is level with the upper surface of the reserved hard mask layer; and

10-4) Back-etching the gate conductive layer to remove the gate conductive layer on the surface of the pad structure and remove a portion of the gate conductive layer in the buried gate word line trench to form the buried gate word line.

The present invention also provides a memory structure comprising:

a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, and a plurality of active areas which are arranged at intervals are isolated in the semiconductor substrate by the shallow trench isolation structure;

A plurality of buried gate word lines arranged at intervals and positioned in the active region, wherein the upper surface of the buried gate word lines is lower than the upper surface of the semiconductor substrate;

bit line contacts on the semiconductor substrate; and

And the dielectric layer is positioned on the surface of the embedded grid electrode word line and fills the gap between the bit line contacts.

As a preferred aspect of the present invention, the memory structure further comprises a pad structure located on a surface of the semiconductor substrate between the buried gate word line and the bit line contact.

a pad oxide layer located on the surface of the semiconductor substrate; and

And the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferred embodiment of the present invention, the bottom of the bit line contact is recessed into the semiconductor substrate.

As a preferred embodiment of the present invention, the buried gate word line includes:

the grid electrode conductive layer is positioned in the active area, and the upper surface of the grid electrode conductive layer is lower than the upper surface of the semiconductor substrate; and

And the gate oxide layer is positioned in the active region and is positioned between the gate conductive layer and the semiconductor substrate.

As described above, the semiconductor structure, the memory structure and the method for manufacturing the same of the present invention have the following beneficial effects:

The semiconductor structure and the preparation method thereof define the positions and the shapes of the buried grid word line and the bit line contact when the side wall structure and the filling layer are formed, and define the bit line contact hole without an extra photoetching process when the buried grid word line and the bit line contact are prepared based on the semiconductor structure, thereby avoiding photoetching exposure offset and ensuring the accurate alignment of the bit line contact; meanwhile, the preparation method of the semiconductor structure is simple, the process steps are simple, and the material cost and the process cost are saved;

according to the memory structure and the preparation method thereof, the positions and the shapes of the buried grid word line and the bit line contact are respectively defined by forming the side wall structure and the filling layer, and an additional photoetching process is not needed to define the bit line contact hole when the bit line contact hole is formed, so that photoetching exposure offset can be avoided, and accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the memory structure is simple, the process steps are simple, and the material cost and the process cost are saved.

Drawings

Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to a first embodiment of the present invention.

Fig. 2 to 8 are schematic structural views showing the structure obtained in step 1) in the method for manufacturing a semiconductor structure according to the first embodiment of the present invention; fig. 4 is a schematic top view of a structure obtained after forming a shallow trench isolation structure in a semiconductor substrate, and fig. 6 is a schematic cross-sectional view along the AA direction in fig. 4.

Fig. 9 is a schematic top view of a structure obtained in step 2) in the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 10 is a schematic view showing a sectional structure along the AA direction in fig. 9.

Fig. 11 is a schematic cross-sectional view showing a structure obtained in step 3) in the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 12 is a schematic top view of a structure obtained in step 4) in the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 13 is a schematic view showing a sectional structure along the AA direction in fig. 12.

Fig. 14 is a schematic view showing a structure obtained in step 5) in the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 15 is a schematic cross-sectional view along the AA direction in fig. 14.

Fig. 16 is a flowchart of a method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 17 to 23 are schematic structural views showing the structure obtained in step 1) in the method for manufacturing a memory structure according to the third embodiment of the present invention; fig. 19 is a schematic top view of a structure obtained after forming a shallow trench isolation structure in a semiconductor substrate, and fig. 20 is a schematic cross-sectional view along the AA direction in fig. 19.

Fig. 24 is a schematic top view of a structure obtained in step 2) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 25 is a schematic view showing a sectional structure along the AA direction in fig. 24.

Fig. 26 is a schematic cross-sectional structure of a structure obtained in step 3) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 27 is a schematic top view of a structure obtained in step 4) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 28 is a schematic view showing a sectional structure along the AA direction in fig. 27.

Fig. 29 is a schematic top view showing a structure obtained in step 5) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 30 is a schematic cross-sectional view along the AA direction in fig. 29.

Fig. 31 is a schematic cross-sectional view showing the structure obtained in step 6) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 32 to 33 are schematic cross-sectional structures of the structures obtained in step 7) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 34 to 36 are schematic cross-sectional views showing the structure obtained in step 8) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 37 is a schematic top view showing a structure obtained in step 9) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 38 is a schematic cross-sectional structure along the AA direction in fig. 37.

Fig. 39 to 41 are schematic cross-sectional views showing the structure obtained in step 10) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 42 is a schematic cross-sectional view showing the structure obtained in step 11) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 43 is a schematic top view showing a structure obtained in step 12) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 44 is a schematic sectional view of the structure along the AA direction in fig. 43.

Fig. 45 is a schematic top view of a structure obtained in step 13) in the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 46 is a schematic sectional view of the structure along the AA direction in fig. 44.

Description of element reference numerals

10. Semiconductor substrate

11. Cushion layer structure

111. Pad oxide layer

112. Pad nitride layer

12. Shallow trench isolation structure

13. Active region

131. Deep well region

14. Hard mask layer

141. First hard mask layer

142. Second hard mask layer

15. Bottom anti-reflection layer

151. Second opening pattern

16. Photoresist layer

161. First opening pattern

162. Bit line contact region

163. Buried gate word line region

17. Side wall structure

18. Filling layer

19. Graphic channel

20. Buried gate wordline trench

21. Buried gate word line

211. Gate oxide layer

212. Gate conductive layer

22. Dielectric layer

23. Bit line contact hole

24. Bit line contact

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1-46. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 1, the present invention provides a method for preparing a semiconductor structure, which includes the following steps:

In step 1), referring to step S11 of fig. 1 and fig. 2 to 5, a semiconductor substrate 10 is provided, and a pad structure 11 is formed on a surface of the semiconductor substrate 10; shallow trench isolation structures 12 are formed in the semiconductor substrate 10 and the pad layer structure 11, and the shallow trench isolation structures 12 isolate a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10.

As an example, the semiconductor substrate 10 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and in addition, when the semiconductor substrate 10 is a single crystal substrate or a polycrystalline substrate, it may be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

As an example, the pad layer 11 may be formed by a physical vapor deposition process or a chemical vapor deposition process, and specifically, the pad layer 11 may include a pad oxide layer 111 and a pad nitride layer 112, where the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 3.

As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench using chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc. The cross-sectional shape of the shallow trench isolation structure 12 may be set according to actual needs, where in fig. 5, the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example, but in an actual example, the cross-sectional shape is not limited to this. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required to remove the insulating layer on the surface of the pad layer structure 11.

As an example, the plurality of active regions 13 that may be isolated by the shallow trench isolation structure 12 on the semiconductor substrate 10 may be, but is not limited to, arranged in an array as shown in fig. 4.

As an example, a MOS device (not shown) is formed in the active region 13, and the MOS device includes a gate, a source, and a drain, wherein the source and the drain are located on opposite sides of the gate, respectively.

As an example, step 1) further comprises the following steps:

Removing the pad structure 11 as shown in fig. 6; specifically, the pad layer structure 11 may be removed by a dry etching process or a wet etching process;

ion implantation is performed in the active region 13 to form a deep well region 131 in the active region 13, as shown in fig. 7; specifically, the type of the deep well region 131 formed may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs; and

A pad layer structure 11 is formed again on the surface of the semiconductor substrate 10 after ion implantation, as shown in fig. 8.

The pad layer structure 11 positioned on the surface of the semiconductor substrate 10 is removed before ion implantation, so that the requirement of ion implantation on energy and dosage can be effectively reduced, and the difficulty of ion implantation is reduced; meanwhile, the accumulation of edge effects of the subsequent working procedure can be reduced.

The pad layer structure 11 is used as an etching stop layer for removing the hard mask layer formed later, so that plasma damage to the semiconductor substrate 10 caused by plasma when the hard mask layer is removed can be effectively prevented; meanwhile, the pad layer 11 may also be used as a termination layer for the planarization process of the gate conductive layer formed later.

In step 2), referring to step S12 in fig. 1 and fig. 9 to 10, a hard mask layer 14, a bottom anti-reflective layer 15 and a photoresist layer 16 are sequentially formed on the surface of the pad layer 11, wherein the hard mask layer 14, the bottom anti-reflective layer (BARC) 15 and the photoresist layer 16 are sequentially stacked from bottom to top, and a first opening pattern 161 is formed in the photoresist layer 16, and the first opening pattern 161 exposes a bit line contact region 162 where a bit line contact is to be formed and a buried gate word line region 163 where a buried gate word line is to be formed.

As an example, forming the hard mask layer 14 on the surface of the pad structure 11 may include the steps of:

forming a first hard mask layer 141 on the surface of the pad layer 11; and

A second hard mask layer 142 is formed on the surface of the first hard mask layer 141.

As an example, the first hard mask layer 141 may include an amorphous carbon (α -C) layer, an amorphous silicon (α -Si) layer, or a silicon oxynitride layer (SiON); the second hard mask layer 142 may also include an amorphous carbon layer, an amorphous silicon layer, or a silicon oxynitride layer; the material of the first hard mask layer 141 may be the same as the material of the second hard mask layer 142, or may be different from the material of the second hard mask layer 142; preferably, in this embodiment, the material of the first hard mask layer 141 is different from the material of the second hard mask layer 142.

In step 3), referring to step S13 in fig. 1 and fig. 11, the bottom anti-reflective layer 15 is etched according to the photoresist layer 16, and the first opening pattern 161 is transferred into the bottom anti-reflective layer 15 to form a second opening pattern 151 in the bottom anti-reflective layer 15.

As an example, the bottom anti-reflection layer 15 may be etched by, but not limited to, a dry etching process according to the photoresist layer 16 to form the second opening pattern 151 in conformity with the first opening pattern 161 in the bottom anti-reflection layer 15.

As an example, after the second opening pattern 151 is formed in the bottom anti-reflection layer 15, a step of removing the photoresist layer 16 is further included.

In step 4), referring to step S14 in fig. 1 and fig. 12 to 13, a sidewall structure 17 is formed on the sidewall of the second opening pattern 151, the sidewall structure 17 defines the position and shape of the buried gate word line region 163, and the second opening pattern 151 outside the sidewall structure 17 defines the position and shape of the bit line contact region 162.

As an example, forming the sidewall structure 17 on the sidewall of the second opening pattern 151 may include the following steps:

4-1) forming a sidewall material layer on the surface of the bottom anti-reflection layer 15, the sidewall of the second opening pattern 151 and the bottom by using an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process; and

4-2) Removing the sidewall material layer on the surface of the bottom anti-reflection layer 15 and at the bottom of the second opening pattern 151 by using a dry etching process, and forming the sidewall structure 17 by the sidewall material layer remaining on the sidewall of the second opening pattern 151.

As an example, the sidewall structures 17 may comprise oxide sidewall structures, i.e. the material of the sidewall structures 17 may comprise an oxide, such as silicon oxide or the like.

Note that, the "second opening pattern 151 outside the sidewall structure 17" refers to a region remained after the sidewall structure 17 is formed in the second opening pattern 151.

In step 5), referring to step S15 in fig. 1 and fig. 14 to 15, a filling layer 18 is formed in the second opening pattern 151 outside the sidewall structure 17, wherein a removal rate of the filling layer 18 is smaller than a removal rate of the bottom anti-reflection layer 15 and a removal rate of the sidewall structure 17 under the same etching condition.

As an example, forming the filling layer 18 in the second opening pattern 151 outside the sidewall structure 17 includes the following steps:

5-1) forming a filling layer 18 in the opening pattern 151 outside the side wall structure 17 and on the surface of the bottom anti-reflection layer 15; and

5-2) Etching back the filling layer 18 on the surface of the bottom anti-reflection layer 15 by dry etching.

As an example, the material of the filling layer 18 should be different from the material of the bottom anti-reflection layer 15 and the material of the sidewall structure 17, so that the filling layer 18 has a different etching selectivity than the bottom anti-reflection layer 15 and the sidewall structure 17; preferably, the removal rate of the filling layer 18 is smaller than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17 under the same etching condition, i.e. the filling layer 18 has a higher selectivity with the bottom anti-reflection layer 15 and the sidewall structure 17 under the same etching condition. More preferably, in this embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, i.e., the material of the filling layer 18 may include, but is not limited to, a nitride, such as silicon nitride. The selectivity ratio of the material of the filling layer 18 is higher than that of the bottom anti-reflection layer 15 and the sidewall structure 17, so that the filling layer 18 is kept when the bottom anti-reflection layer 15 and the sidewall structure 17 are etched and removed, and self-alignment can be realized when the bit line contact hole needs to be formed.

The semiconductor structure prepared by the preparation method of the semiconductor structure can simultaneously define the position and the shape of the buried gate word line region 163 needing to form the buried gate word line and the bit line contact region 162 needing to form bit line contact in a self-alignment manner when the side wall structure 17 and the filling layer 18 are formed, and no extra photoetching process is needed to define the bit line contact hole when the buried gate word line and the bit line contact are prepared based on the semiconductor structure, so that exposure offset existing when the bit line contact hole is formed by photoetching is avoided, and further the accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the semiconductor structure has simple process steps, and can effectively save material cost and process cost.

Example two

With continued reference to fig. 2 to 15, the present invention further provides a semiconductor structure, which includes: a semiconductor substrate 10; a pad structure 11, the pad structure 11 being located on a surface of the semiconductor substrate 10; a shallow trench isolation structure 12, wherein the shallow trench isolation structure 12 is located in the semiconductor substrate 10 and the pad layer structure 11 to isolate a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10; a hard mask layer 14, wherein the hard mask layer 14 is positioned on the surface of the cushion layer structure 11; a bottom anti-reflection coating 15, the bottom anti-reflection coating 15 being located on a surface of the hard mask layer 14; a filling layer 18, wherein the filling layer 18 is located in the bottom anti-reflection coating 15, and the filling layer 18 defines the position and shape of the bit line contact to be formed; the side wall structure 17 is positioned in the bottom anti-reflection coating 15 and outside the filling layer 18, and the side wall structure 17 defines the position and the shape of the embedded grid word line to be formed; the removal rate of the filling layer 18 is smaller than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17 under the same etching conditions.

As an example, the pad structure 11 includes a pad oxide layer 111 and a pad nitride layer 112, wherein the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 3.

As an example, a deep well region 131 is further formed in the active region 13, as shown in fig. 7; specifically, the type of the deep well region 131 may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs.

By way of example, the hard mask layer 14 includes: a first hard mask layer 141, where the first hard mask layer 141 is located on the surface of the pad layer structure 11; and a second hard mask layer 142, wherein the second hard mask layer 142 is located on the surface of the first hard mask layer 141.

As an example, the sidewall structures 17 define the location and shape of the buried gate wordline region 163 where the buried gate wordline is to be formed, the sidewall structures 17 may comprise oxide sidewall structures, i.e. the material of the sidewall structures 17 may comprise an oxide, such as silicon oxide or the like.

As an example, the filling layer 18 defines the position and shape of the bit line contact region 162 where the bit line contact needs to be formed, and the material of the filling layer 18 should be different from the material of the bottom anti-reflection layer 15 and the material of the sidewall structure 17, so that the filling layer 18 has a different etching selectivity than the bottom anti-reflection layer 15 and the sidewall structure 17; preferably, the removal rate of the filling layer 18 is smaller than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17 under the same etching condition, i.e. the filling layer 18 has a higher selectivity with the bottom anti-reflection layer 15 and the sidewall structure 17 under the same etching condition. More preferably, in this embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, i.e., the material of the filling layer 18 may include, but is not limited to, a nitride, such as silicon nitride. The selectivity ratio of the material of the filling layer 18 is higher than that of the bottom anti-reflection layer 15 and the sidewall structure 17, so that the filling layer 18 is kept when the bottom anti-reflection layer 15 and the sidewall structure 17 are etched and removed, and self-alignment can be realized when the bit line contact hole needs to be formed.

Example III

Referring to fig. 16, the present invention further provides a method for manufacturing a memory structure, where the method for manufacturing a memory structure includes the following steps:

7) Removing the filling layer and the bottom anti-reflection layer;

12 Removing the hard mask layer of the bit line contact region and etching the semiconductor substrate to form a bit line contact hole in the dielectric layer and the semiconductor substrate, wherein the bottom of the bit line contact hole is sunk in the semiconductor substrate; and

In step 1), referring to step S21 in fig. 16 and fig. 17 to 20, a semiconductor substrate 10 is provided, and a pad structure 11 is formed on a surface of the semiconductor substrate 10; shallow trench isolation structures 12 are formed in the semiconductor substrate 10 and the pad layer structure 11, and the shallow trench isolation structures 12 isolate a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10.

As an example, the pad layer 11 may be formed by a physical vapor deposition process or a chemical vapor deposition process, and specifically, the pad layer 11 may include a pad oxide layer 111 and a pad nitride layer 112, where the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 20.

As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench using chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc. The cross-sectional shape of the shallow trench isolation structure 12 may be set according to actual needs, where in fig. 20, the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example, but in an actual example, the cross-sectional shape is not limited to this. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required to remove the insulating layer on the surface of the pad layer structure 11.

As an example, the plurality of active regions 13 that may be isolated by the shallow trench isolation structure 12 on the semiconductor substrate 10 may be, but is not limited to, arranged in an array as shown in fig. 19.

As an example, step 1) further comprises the following steps:

removing the pad structure 11 as shown in fig. 21; specifically, the pad layer structure 11 may be removed by a dry etching process or a wet etching process;

Ion implantation is performed in the active region 13 to form a deep well region 131 in the active region 13, as shown in fig. 22; specifically, the type of the deep well region 131 formed may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs; and

A pad layer structure 11 is formed again on the surface of the semiconductor substrate 10 after ion implantation, as shown in fig. 23.

In step 2), referring to step S22 in fig. 16 and fig. 24 to 25, a hard mask layer 14, a bottom anti-reflective layer 15 and a photoresist layer 16 are sequentially formed on the surface of the pad structure 11, wherein the hard mask layer 14, the bottom anti-reflective layer (BARC) 15 and the photoresist layer 16 are sequentially stacked from bottom to top, and a first opening pattern 161 is formed in the photoresist layer 16, and the first opening pattern 161 exposes a bit line contact region 162 where a bit line contact is to be formed and a buried gate word line region 163 where a buried gate word line is to be formed.

forming a first hard mask layer 141 on the surface of the pad layer 11; and

In step 3), referring to step S23 in fig. 16 and fig. 26, the bottom anti-reflective layer 15 is etched according to the photoresist layer 16, and the first opening pattern 161 is transferred into the bottom anti-reflective layer 15 to form a second opening pattern 151 in the bottom anti-reflective layer 15.

In step 4), referring to step S24 in fig. 16 and fig. 27 to 28, a sidewall structure 17 is formed on the sidewall of the second opening pattern 151, the sidewall structure 17 defines the position and shape of the buried gate word line region 163, and the second opening pattern 151 outside the sidewall structure 17 defines the position and shape of the bit line contact region 162.

In step 5), referring to step S25 in fig. 16 and fig. 29 to 30, a filling layer 18 is formed in the second opening pattern 151 outside the sidewall structure 17, wherein a removal rate of the filling layer 18 is smaller than a removal rate of the bottom anti-reflection layer 15 and a removal rate of the sidewall structure 17 under the same etching condition.

In step 6), referring to step S26 in fig. 16 and fig. 31, the sidewall structure 17 and the hard mask layer 14 in the buried gate word line region 163 are etched to form a pattern channel 19 in the bottom anti-reflective layer 15 and the hard mask layer 14, wherein the pattern channel 19 defines the position and shape of the buried gate word line.

As an example, but not limited to, a dry etching process may be used to etch away the sidewall structure 17, the hard mask layer 14 directly under the sidewall structure 17 (i.e. in the buried gate wordline region 163), and the etching process is stopped at the pad structure 11, i.e. the pad structure 11 acts as an etch stop.

In step 7), referring to step S27 in fig. 16 and fig. 32 to 33, the filling layer 18 and the bottom anti-reflection layer 15 are removed.

As an example, removing the filling layer 18 and the bottom anti-reflection layer 15 comprises the following steps:

7-1) etching to remove the bottom anti-reflection layer 15, as shown in fig. 32; specifically, a dry etching process may be used to etch and remove the bottom anti-reflection layer 15;

7-2) etching away the second hard mask layer 142 except for the bit line contact region 162, i.e., removing the second hard mask layer 142 except for directly under the filler layer 18; specifically, the second hard mask layer 142 outside the bit line contact region 162 may be etched and removed by, but not limited to, a dry etching process according to the filling layer 18 as a mask layer; and

7-3) Removing the filler layer 18, as shown in fig. 33; in particular, the fill layer 18 may be removed using, but is not limited to, a dry etch process.

In step 8), referring to step S28 in fig. 16 and fig. 34 to 36, the pad layer 11 at the bottom of the pattern channel 19 is removed, and the hard mask layer 14 outside the bit line contact region 162 is removed.

Illustratively, removing the pad layer 11 at the bottom of the pattern channel 19 and removing the hard mask layer 14 outside the bit line contact region 162 includes the steps of:

8-1) removing the pad structure 11 at the bottom of the pattern channel 19, as shown in fig. 34; specifically, the pad structure 11 is etched according to the hard mask layer 14 to remove the exposed pad structure 11 at the bottom of the pattern channel 19; more specifically, the pad structure 11 at the bottom of the pattern channel 19 may be etched using, but not limited to, a dry etching process;

8-2) removing the first hard mask layer 141 outside the bit line contact region 162, as shown in fig. 35; specifically, the first hard mask layer 141 outside the bit line contact region 162 may be etched and removed by, but not limited to, a dry etching process according to the remaining second hard mask layer 142 as a mask; it should be noted that, in the process of removing the first hard mask layer 141, etching is stopped at the pad layer structure 11, that is, the pad layer structure 11 is used as an etching barrier layer; and

8-3) Removing the second hard mask layer 142 of the bit line contact region 162, as shown in fig. 36; specifically, the second hard mask layer 142 located at the bit line contact region 162 may be removed using, but not limited to, a dry etching process; specifically, when the second hard mask layer 142 is removed, etching is not performed on the pad structure 11, the first hard mask layer 141 located in the bit line contact region 162, and the semiconductor substrate 10, and etching gas for immediately etching and removing the second hard mask layer 142 has a very small etching and removing rate on the pad structure 11, the first hard mask layer 141, and the semiconductor substrate 10, which is almost negligible; this ensures that the first hard mask layer 141 in the bit line relieved region 162 is preserved when the second hard mask layer 142 is removed.

In step 9), referring to step S29 in fig. 16 and fig. 37 to 38, the semiconductor substrate 10 is etched according to the pattern channel 19 to form a buried gate word line trench 20 in the semiconductor substrate 10.

As an example, the semiconductor substrate 10 may be etched using, but not limited to, a dry etching process to form the buried gate wordline trench 20 within the semiconductor substrate 10. It should be noted that, during the etching process, the semiconductor substrate 10 may be etched according to the remaining first hard mask layer 141 and the pad layer structure 11 as a mask.

In step 10), referring to S210 in fig. 16 and fig. 39 to 41, a buried gate word line 21 is formed in the buried gate word line trench 20, and the upper surface of the buried gate word line 21 is lower than the upper surface of the semiconductor substrate 10.

By way of example, forming the buried gate word line 21 within the buried gate word line trench 20 includes the steps of:

10-1) forming a gate oxide layer 211 on the sidewalls and bottom of the buried gate wordline trench 20, as shown in fig. 39; specifically, the gate oxide layer 211 may be formed on the sidewalls and bottom of the buried gate wordline trench 20 by, but not limited to, a thermal oxidation process;

10-2) forming a gate conductive layer 212 in the buried gate word line trench 20 and on the surface of the pad structure 11, wherein the gate conductive layer 212 fills the gap between the buried gate word line trench 20 and the bit line contact region 162 (i.e., the gap between the remaining first hard mask layers 141) and covers the remaining hard mask layers 14 (in this case, the remaining hard mask layers 14 are the first hard mask layers 141);

10-3) removing a portion of the gate conductive layer 212 using a chemical polishing (CMP) process such that the upper surface of the remaining gate conductive layer 212 is level with the upper surface of the remaining hard mask layer 14 (i.e., the first hard mask layer 141 as shown in fig. 40), as shown in fig. 40; and

10-4) Etching back the gate conductive layer 212 to remove the gate conductive layer 212 on the surface of the pad structure 11 and to remove a portion of the gate conductive layer 212 in the buried gate wordline trench 20 to form the buried gate wordline 21, as shown in fig. 41. Note that, the "the upper surface of the buried gate word line 21 is lower than the upper surface of the semiconductor substrate 10" in this example means that the upper surface of the thresh gate conductive layer 212 in the buried gate word line 21 is lower than the upper surface of the semiconductor substrate 10.

As an example, the material of the gate conductive layer 212 in the buried gate word line 21 includes at least one of titanium nitride, tantalum nitride and tungsten, that is, the material of the gate conductive layer 212 may include low-resistivity metal such as titanium nitride, tantalum nitride or tungsten, or may include at least two of titanium nitride, tantalum nitride and tungsten, that is, in this case, the gate conductive layer 212 may be a conductive layer of a composite material composed of at least two materials of titanium nitride, tantalum nitride and tungsten, or may be a conductive layer including at least two layers of a titanium nitride layer, a tantalum nitride layer and a tungsten layer.

In step 11), referring to step S211 and fig. 42 in fig. 16, a dielectric layer 22 is formed in the buried gate word line trench 20 and on the surface of the pad layer structure 11; the dielectric layer 22 fills the buried gate wordline trench 20 and covers the surface of the pad structure 11.

As an example, the dielectric layer 22 may be formed using, but not limited to, a physical vapor deposition process or a chemical vapor deposition process, and the dielectric layer 22 may include, but not limited to, an oxide layer or a nitride layer, i.e., the material of the dielectric layer 22 may include, but not limited to, an oxide or a nitride. In particular, the oxide may include silicon oxide and the nitride may include silicon nitride. In this step, the first hard mask layer 141 is remained, and the first hard mask layer 141 defines the position of the bit line contact hole 23 to be formed later, so that self-alignment can be achieved in the later formation of the bit line contact hole 23.

In step 12), referring to step S212 in fig. 16 and fig. 43 to fig. 44, the hard mask layer 14 of the bit line contact region 162 is removed and the semiconductor substrate 10 is etched to form a bit line contact hole 23 in the dielectric layer 22 and the semiconductor substrate 10, wherein the bottom of the bit line contact hole 23 is recessed in the semiconductor substrate 10.

As an example, a dry etching process may be used to etch the hard mask layer 14 and the semiconductor substrate 10 to form the bit line contact hole 23, and since the position and shape of the bit line contact hole 23 are already predefined by the remaining first hard mask layer 141, the bit line contact hole 23 may be etched and formed according to the remaining first hard mask layer 141 without a photolithography process, thereby realizing precise self-alignment of the bit line contact hole 23.

It should be noted that, since the pad structure 11 is disposed under the first hard mask layer 141, when the first hard mask layer 141 is etched away, the pad structure 11 disposed directly under the first hard mask layer 141 is also removed.

The bit line contact hole 23 extends into the semiconductor substrate 10 in addition to being located in the dielectric layer 22, so that the contact area between the subsequently formed bit line contact and the active region 13 can be increased, that is, the contact area between the subsequently formed bit line contact and the active region 13 can be increased, and the contact resistance can be reduced.

It should be noted that, the dimension of the bit line contact hole 23 extending to the active region 13 may be the same as the dimension of the portion of the bit line contact hole 23 located in the dielectric layer 22, and the dimension of the bit line contact hole 23 extending to the active region 13 may be larger than the dimension of the portion of the bit line contact hole 23 located in the dielectric layer 22.

In step 13), referring to step S213 in fig. 16 and fig. 45 to 46, a contact material is filled in the bit line contact hole 23 to form a bit line contact 24.

As an example, filling the bit line contact hole 23 with a contact material to form the bit line contact 24 may include the following steps:

13-1) forming contact materials in the bit line contact holes 23 and on the surface of the dielectric layer 22 by adopting a physical vapor deposition process or a chemical vapor deposition process;

13-2) removing the contact material on the surface of the dielectric layer 22 by using a chemical mechanical polishing process, wherein the contact material remaining in the bit line contact hole 23 forms the bit line contact 24.

By way of example, the material of the bit line contacts 24 includes, but is not limited to, polysilicon. Specifically, the material of the bit line contacts 24 may include doped polysilicon to make the bit line contacts 24 conductive. The bit line contacts 24 are structures that connect the active region 13 with subsequently formed bit lines.

Example IV

Referring to fig. 17 to 46, the present invention further provides a memory structure, a semiconductor substrate 10, in which a shallow trench isolation structure 12 is formed in the semiconductor substrate 10, and the shallow trench isolation structure 12 isolates a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10; a plurality of buried gate word lines 21 arranged at intervals and located in the active region 13, wherein the upper surface of the buried gate word lines 21 is lower than the upper surface of the semiconductor substrate 10; a bit line contact 24, the bit line contact 24 being located on the semiconductor substrate 10; and a dielectric layer 22, wherein the dielectric layer 22 is located on the surface of the buried gate word line 21 and fills the gap between the bit line contacts 24.

As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench using chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc. The cross-sectional shape of the shallow trench isolation structure 12 may be set according to actual needs, where in fig. 46, the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example, but in an actual example, the cross-sectional shape is not limited thereto. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required to remove the insulating layer on the surface of the pad layer structure 11.

As an example, the plurality of active regions 13 that may be isolated by the shallow trench isolation structure 12 on the semiconductor substrate 10 may be, but is not limited to, arranged in an array as shown in fig. 45.

As an example, a deep well region 131 is further formed in the active region 13, as shown in fig. 46; specifically, the type of the deep well region 131 may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs.

As an example, the memory structure further comprises a pad structure 11, the pad structure 11 being located at the surface of the semiconductor substrate 10 between the buried gate word line 21 and the bit line contact 24.

As an example, the pad structure 11 includes a pad oxide layer 111 and a pad nitride layer 112, wherein the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 46. The pad layer structure 11 is used as an etching stop layer for removing the hard mask layer formed later, so that plasma damage to the semiconductor substrate 10 caused by plasma when the hard mask layer is removed can be effectively prevented; meanwhile, the pad layer 11 may also be used as a termination layer for the planarization process of the gate conductive layer formed later.

As an example, the buried gate word line 21 includes a gate oxide layer 211 and a gate conductive layer 212, the gate conductive layer 212 is located in the active region 13, and an upper surface of the gate conductive layer 212 is lower than an upper surface of the semiconductor substrate 10; the gate oxide layer 211 is located within the active region 13 and between the gate conductive layer 212 and the semiconductor substrate 10.

As an example, the bottom of the bit line contact 24 is recessed within the semiconductor substrate 10. The bottom of the bit line contact 24 is sunk into the semiconductor substrate 10, so that the contact area between the bit line contact 24 and the active region 13 can be increased, the contact area between the bit line 25 and the active region 13 can be increased, and the contact resistance can be reduced.

In summary, the present invention provides a semiconductor structure, a memory structure and a method for manufacturing the same, wherein the method for manufacturing the semiconductor structure includes the following steps: 1) Providing a semiconductor substrate, and forming a cushion layer structure on the surface of the semiconductor substrate; forming shallow trench isolation structures in the semiconductor substrate and the pad layer structure, wherein the shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the semiconductor substrate; 2) Sequentially forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the cushion layer structure, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially overlapped from bottom to top, a first opening pattern is formed in the photoresist layer, and the first opening pattern exposes a bit line contact area needing to form bit line contact and a buried gate word line area needing to form a buried gate word line; 3) Etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer to form a second opening pattern in the bottom anti-reflection layer; 4) Forming a side wall structure on the side wall of the second opening pattern, wherein the side wall structure defines the position and the shape of the embedded grid word line region, and the second opening pattern outside the side wall structure defines the position and the shape of the bit line contact region; and 5) forming a filling layer in the second opening pattern outside the side wall structure, wherein the removal rate of the filling layer is smaller than the removal rate of the bottom anti-reflection layer and the removal rate of the side wall structure under the same etching condition. The semiconductor structure and the preparation method thereof define the positions and the shapes of the buried grid word line and the bit line contact when the side wall structure and the filling layer are formed, and define the bit line contact hole without an extra photoetching process when the buried grid word line and the bit line contact are prepared based on the semiconductor structure, thereby avoiding photoetching exposure offset and ensuring the accurate alignment of the bit line contact; meanwhile, the preparation method of the semiconductor structure is simple, the process steps are simple, and the material cost and the process cost are saved; according to the memory structure and the preparation method thereof, the positions and the shapes of the buried grid word line and the bit line contact are respectively defined by forming the side wall structure and the filling layer, and an additional photoetching process is not needed to define the bit line contact hole when the bit line contact hole is formed, so that photoetching exposure offset can be avoided, and accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the memory structure is simple, the process steps are simple, and the material cost and the process cost are saved.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, comprising the steps of:

2. The method of fabricating a semiconductor structure according to claim 1, further comprising the steps of:

Removing the cushion layer structure;

3. The method of manufacturing a semiconductor structure according to claim 1 or 2, wherein the pad layer structure comprises:

a pad oxide layer located on the surface of the semiconductor substrate; and

And the pad nitride layer is positioned on the surface of the pad oxide layer.

4. The method of claim 1, wherein in step 2), forming the hard mask layer on the surface of the pad layer structure comprises the steps of:

5. A semiconductor structure, comprising:

A semiconductor substrate;

A pad layer structure located on the surface of the semiconductor substrate;

Under the same etching condition, the removal rate of the filling layer is smaller than the removal rate of the bottom anti-reflection layer and the removal rate of the side wall structure;

the filling layer is a nitride layer, and the side wall structure is an oxide side wall structure.

6. The semiconductor structure of claim 5, wherein a deep well region is further formed within the active region.

7. The semiconductor structure of claim 5, wherein the pad layer structure comprises:

A pad oxide layer located on the surface of the semiconductor substrate;

and the pad nitride layer is positioned on the surface of the pad oxide layer.

8. The semiconductor structure of claim 5, wherein the hard mask layer comprises:

9. A method of fabricating a memory structure, comprising the steps of:

7) Removing the filling layer and the bottom anti-reflection layer;

10. The method of manufacturing a memory structure as claimed in claim 9, wherein,

The method further comprises the following steps between the step 1) and the step 2):

Removing the cushion layer structure;

11. A method of fabricating a memory structure according to claim 9 or 10, wherein the pad layer structure comprises:

a pad oxide layer located on the surface of the semiconductor substrate; and

And the pad nitride layer is positioned on the surface of the pad oxide layer.

12. The method of claim 9, wherein in step 2), forming the hard mask layer on the surface of the pad layer structure comprises:

13. The method of manufacturing a memory structure according to claim 12, wherein step 7) comprises the steps of:

7-1) etching to remove the bottom anti-reflection layer;

7-3) Removing the filling layer.

14. The method of manufacturing a memory structure according to claim 13, wherein step 8) comprises the steps of:

8-1) removing the pad layer structure at the bottom of the pattern channel;

8-3) Removing the second hard mask layer of the bit line contact region.

15. The method of manufacturing a memory structure according to claim 9, wherein step 10) comprises the steps of:

16. A memory structure, comprising:

bit line contacts on the semiconductor substrate; and

The dielectric layer is positioned on the surface of the embedded grid word line and fills up the gap between the bit line contacts;

The position and the shape of the buried gate word line to be formed are defined by forming a side wall structure, the position and the shape of the bit line contact to be formed are defined by forming a filling layer, the side wall structure is an oxide side wall structure, and the filling layer is a nitride layer.

17. The memory structure of claim 16, wherein a deep well region is further formed within the active region.

18. The memory structure of claim 16, further comprising a pad structure located on a surface of the semiconductor substrate between the buried gate word line and the bit line contact.

19. The memory structure of claim 18, wherein the pad layer structure comprises:

a pad oxide layer located on the surface of the semiconductor substrate; and

And the pad nitride layer is positioned on the surface of the pad oxide layer.

20. The memory structure of claim 16, wherein a bottom of the bit line contact is recessed within the semiconductor substrate.

21. The memory structure of claim 16, wherein the buried gate word line comprises: