CN110957320A

CN110957320A - Semiconductor structure, memory structure and preparation method thereof

Info

Publication number: CN110957320A
Application number: CN201811133685.1A
Authority: CN
Inventors: 巩金峰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-27
Filing date: 2018-09-27
Publication date: 2020-04-03

Abstract

The invention provides a semiconductor structure, a memory structure and a preparation method thereof, comprising the following steps: 1) providing a semiconductor substrate, and forming a cushion layer structure on the surface of the semiconductor substrate; forming shallow trench isolation structures in the semiconductor substrate and the cushion layer structure, and isolating a plurality of active regions which are distributed at intervals in the semiconductor substrate; 2) forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the cushion layer structure, wherein a first opening pattern is formed in the photoresist layer; 3) etching the bottom anti-reflection layer according to the photoresist layer to form a second opening pattern in the bottom anti-reflection layer; 4) forming a side wall structure on the side wall of the second opening pattern; 5) and forming a filling layer in the second opening pattern outside the side wall structure. According to the invention, when the embedded grid word line and the bit line contact are prepared on the basis of the semiconductor structure, the bit line contact hole is not required to be defined by a photoetching process, so that photoetching exposure deviation can be avoided, and accurate alignment of the bit line contact is ensured.

Description

Semiconductor structure, memory structure and preparation method thereof

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor structure, a memory structure and a preparation method thereof.

Background

With the development of the process, the integration level of the semiconductor device is higher and higher, the size of the semiconductor device is smaller and smaller, the process is more and more complex, and the cost is higher and higher. Meanwhile, in the fabrication process of the semiconductor device, if the feature shape has an error from the target value (i.e., the feature shape cannot be precisely aligned), the performance of the semiconductor device will be significantly adversely affected. For example, in the conventional process for manufacturing a memory structure, the number of steps of the whole process flow is large, the cost is high, and when a bit line contact hole is formed, the conventional photolithography exposure process is difficult to achieve precise alignment, so that the reliability and stability of the manufactured memory structure are low.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure, a memory structure and a method for manufacturing the same, which are used to solve the problems in the prior art, such as more steps, higher cost, difficulty in achieving precise alignment of bit line contact holes, and poor reliability and stability of the obtained memory structure.

To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:

1) providing a semiconductor substrate, and forming a cushion layer structure on the surface of the semiconductor substrate; forming shallow trench isolation structures in the semiconductor substrate and the cushion layer structure, wherein the shallow trench isolation structures isolate a plurality of active regions which are distributed at intervals in the semiconductor substrate;

2) sequentially forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the cushion layer structure, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially overlapped from bottom to top, a first opening pattern is formed in the photoresist layer, and the first opening pattern exposes a bit line contact area needing to form bit line contact and an embedded grid word line area needing to form an embedded grid word line;

3) etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer so as to form a second opening pattern in the bottom anti-reflection layer;

4) forming a side wall structure on the side wall of the second opening pattern, wherein the side wall structure defines the position and the shape of the word line region of the embedded grid, and the second opening pattern outside the side wall structure defines the position and the shape of the bit line contact region; and

5) and forming a filling layer in the second opening pattern outside the side wall structure, wherein under the same etching condition, the removal rate of the filling layer is less than the removal rate of the bottom anti-reflection layer and the removal rate of the side wall structure.

As a preferable scheme of the invention, the method also comprises the following steps between the step 1) and the step 2):

removing the cushion layer structure;

performing ion implantation in the active region to form a deep well region in the active region; and

forming a cushion layer structure on the surface of the semiconductor substrate after ion implantation again; and 2), sequentially forming the hard mask layer, the bottom anti-reflection layer and the photoresist layer on the surface of the formed cushion layer structure in step 2).

As a preferable aspect of the present invention, the cushion layer structure includes:

a pad oxide layer on the surface of the semiconductor substrate; and

and the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferable aspect of the present invention, the step 2) of forming the hard mask layer on the surface of the pad layer structure includes the following steps:

forming a first hard mask layer on the surface of the cushion layer structure; and

and forming a second hard mask layer on the surface of the first hard mask layer.

The present invention also provides a semiconductor structure comprising:

a semiconductor substrate;

the cushion layer structure is positioned on the surface of the semiconductor substrate;

the shallow trench isolation structure is positioned in the semiconductor substrate and the cushion layer structure so as to isolate a plurality of active regions which are distributed at intervals in the semiconductor substrate;

the hard mask layer is positioned on the surface of the cushion layer structure;

the bottom anti-reflection coating is positioned on the surface of the hard mask layer;

the filling layer is positioned in the bottom anti-reflection coating and defines the position and the shape of a bit line contact to be formed; and

the side wall structure is positioned in the bottom anti-reflection coating and positioned outside the filling layer, and defines the position and the shape of the embedded gate word line to be formed; wherein the content of the first and second substances,

under the same etching condition, the removal rate of the filling layer is less than that of the bottom anti-reflection layer and that of the side wall structure.

In a preferred embodiment of the present invention, a deep well region is further formed in the active region.

a pad oxide layer on the surface of the semiconductor substrate;

and the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferred aspect of the present invention, the hard mask layer includes:

the first hard mask layer is positioned on the surface of the cushion layer structure; and

and the second hard mask layer is positioned on the surface of the first hard mask layer.

The invention also provides a preparation method of the memory structure, which comprises the following steps:

4) forming a side wall structure on the side wall of the second opening pattern, wherein the side wall structure defines the position and the shape of the word line region of the embedded grid, and the second opening pattern outside the side wall structure defines the position and the shape of the bit line contact region;

5) forming a filling layer in the second opening pattern outside the side wall structure, wherein under the same etching condition, the removal rate of the filling layer is less than the removal rate of the bottom anti-reflection layer and the removal rate of the side wall structure;

6) etching and removing the side wall structure and the hard mask layer positioned in the embedded grid word line region so as to form a pattern channel in the bottom anti-reflection layer and the hard mask layer, wherein the pattern channel defines the position and the shape of the embedded grid word line;

7) removing the filling layer and the bottom anti-reflection layer;

8) removing the cushion layer structure at the bottom of the pattern channel and removing the hard mask layer outside the bit line contact area;

9) etching the semiconductor substrate according to the pattern channel to form a buried gate word line groove in the semiconductor substrate;

10) forming a buried gate word line in the buried gate word line trench, wherein the upper surface of the buried gate word line is lower than the upper surface of the semiconductor substrate;

11) forming a dielectric layer in the embedded grid word line groove and on the surface of the cushion layer structure; the dielectric layer fills the embedded grid word line groove and covers the surface of the cushion layer structure;

12) removing the hard mask layer in the bit line contact area and etching the semiconductor substrate to form a bit line contact hole in the dielectric layer and the semiconductor substrate, wherein the bottom of the bit line contact hole is sunk into the semiconductor substrate; and

13) and filling a contact material in the bit line contact hole to form a bit line contact.

removing the cushion layer structure;

a pad oxide layer on the surface of the semiconductor substrate; and

and the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferable aspect of the present invention, the step 7) includes the steps of:

7-1) etching to remove the bottom anti-reflection layer;

7-2) etching to remove the second hard mask layer outside the bit line contact area; and

7-3) removing the filling layer.

As a preferable aspect of the present invention, the step 8) includes the steps of:

8-1) removing the cushion layer structure at the bottom of the pattern channel;

8-2) removing the first hard mask layer outside the bit line contact area; and

8-3) removing the second hard mask layer in the bit line contact area.

As a preferable aspect of the present invention, the step 10) includes the steps of:

10-1) forming a gate oxide layer on the side wall and the bottom of the embedded gate word line groove;

10-2) forming a gate conductive layer in the embedded gate word line trench and on the surface of the cushion layer structure, wherein the gate conductive layer fills a gap between the embedded gate word line trench and the bit line contact region and covers the reserved hard mask layer;

10-3) removing part of the grid conducting layer by adopting a chemical grinding process, so that the upper surface of the reserved grid conducting layer is flush with the upper surface of the reserved hard mask layer; and

10-4) etching back the gate conductive layer to remove the gate conductive layer on the surface of the pad layer structure and remove a portion of the gate conductive layer in the trench of the buried gate word line to form the buried gate word line.

The present invention also provides a memory structure, comprising:

the semiconductor device comprises a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, and a plurality of active regions which are distributed at intervals are isolated in the semiconductor substrate by the shallow trench isolation structure;

the embedded grid word lines are arranged at intervals and are positioned in the active region, and the upper surfaces of the embedded grid word lines are lower than the upper surface of the semiconductor substrate;

bit line contacts on the semiconductor substrate; and

and the dielectric layer is positioned on the surface of the embedded grid word line and fills the gap between the bit line contacts.

As a preferred aspect of the present invention, the memory structure further includes a pad structure, and the pad structure is located on a surface of the semiconductor substrate between the buried gate word line and the bit line contact.

a pad oxide layer on the surface of the semiconductor substrate; and

and the pad nitride layer is positioned on the surface of the pad oxide layer.

As a preferred embodiment of the present invention, the bottom of the bit line contact is recessed in the semiconductor substrate.

As a preferred aspect of the present invention, the buried gate word line includes:

the grid conducting layer is positioned in the active region, and the upper surface of the grid conducting layer is lower than the upper surface of the semiconductor substrate; and

and the grid oxide layer is positioned in the active region and is positioned between the grid conducting layer and the semiconductor substrate.

As described above, the semiconductor structure, the memory structure and the manufacturing method thereof of the present invention have the following advantages:

according to the semiconductor structure and the preparation method thereof, the position and the shape of the contact of the embedded grid word line and the bit line are defined when the side wall structure and the filling layer are formed, and the bit line contact hole is defined without an additional photoetching process when the embedded grid word line and the bit line contact are prepared on the basis of the semiconductor structure, so that photoetching exposure deviation can be avoided, and accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the semiconductor structure is simple, the process steps are simple, and the material cost and the process cost are saved;

according to the memory structure and the preparation method thereof, the positions and the shapes of the embedded grid word line and the embedded grid bit line contact are respectively defined by forming the side wall structure and the filling layer, and the bit line contact hole is defined without an additional photoetching process when the bit line contact hole is formed, so that photoetching exposure deviation can be avoided, and accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the memory structure is simple, the process steps are simple, and the material cost and the process cost are saved.

Drawings

Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to a first embodiment of the present invention.

Fig. 2 to 8 are schematic structural diagrams illustrating the structure obtained in step 1) of the method for manufacturing a semiconductor structure according to the first embodiment of the present invention; fig. 4 is a schematic top view of a structure obtained after forming a shallow trench isolation structure in a semiconductor substrate, and fig. 6 is a schematic cross-sectional view along the AA direction in fig. 4.

Fig. 9 is a schematic top view of the structure obtained in step 2) of the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 10 is a schematic cross-sectional view along AA in fig. 9.

Fig. 11 is a schematic cross-sectional view of the structure obtained in step 3) of the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 12 is a schematic top view of the structure obtained in step 4) of the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 13 is a schematic cross-sectional view along AA in fig. 12.

Fig. 14 is a schematic view of the structure obtained in step 5) of the method for manufacturing a semiconductor structure according to the first embodiment of the present invention.

Fig. 15 is a schematic cross-sectional view along AA in fig. 14.

Fig. 16 is a flowchart illustrating a method for manufacturing a memory structure according to a third embodiment of the invention.

Fig. 17 to 23 are schematic structural diagrams illustrating the structure obtained in step 1) of the method for manufacturing a memory structure according to the third embodiment of the invention; fig. 19 is a schematic top view of a structure obtained after forming a shallow trench isolation structure in a semiconductor substrate, and fig. 20 is a schematic cross-sectional view along the AA direction in fig. 19.

Fig. 24 is a schematic top view of the structure obtained in step 2) in the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 25 is a schematic cross-sectional view along AA in fig. 24.

Fig. 26 is a schematic cross-sectional view illustrating a structure obtained in step 3) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 27 is a schematic top view of the structure obtained in step 4) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 28 is a schematic cross-sectional view along AA in fig. 27.

Fig. 29 is a schematic top view illustrating the structure obtained in step 5) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 30 is a schematic cross-sectional view along AA in fig. 29.

Fig. 31 is a schematic cross-sectional view of the structure obtained in step 6) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 32 to 33 are schematic cross-sectional structures of the structures obtained in step 7) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 34 to fig. 36 are schematic cross-sectional structures of the structures obtained in step 8) of the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 37 is a schematic top view illustrating the structure obtained in step 9) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 38 is a schematic cross-sectional view along AA in fig. 37.

Fig. 39 to 41 are schematic cross-sectional structures of the structures obtained in step 10) of the method for manufacturing a memory structure according to the third embodiment of the present invention.

Fig. 42 is a schematic cross-sectional view illustrating a structure obtained in step 11) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 43 is a schematic top view of the structure obtained in step 12) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 44 is a schematic cross-sectional view along AA in fig. 43.

Fig. 45 is a schematic top view illustrating the structure obtained in step 13) of the method for manufacturing a memory structure according to the third embodiment of the invention.

Fig. 46 is a schematic cross-sectional view along AA in fig. 44.

Description of the element reference numerals

10 semiconductor substrate

11 cushion layer structure

111 pad oxide layer

112 pad nitride layer

12 shallow trench isolation structure

13 active region

131 deep well region

14 hard mask layer

141 first hard mask layer

142 second hard mask layer

15 bottom anti-reflection layer

151 second opening pattern

16 photo resist layer

161 first opening pattern

162 bit line contact region

163 buried gate word line region

17 side wall structure

18 filling layer

19-figure channel

20 buried gate word line trench

21 buried gate word line

211 gate oxide layer

212 gate conductive layer

22 dielectric layer

23 bit line contact hole

24 bit line contact

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 46. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

As shown in fig. 1, the present invention provides a method for fabricating a semiconductor structure, which comprises the following steps:

In step 1), please refer to step S11 of fig. 1 and fig. 2 to 5, providing a semiconductor substrate 10, and forming a pad layer structure 11 on a surface of the semiconductor substrate 10; shallow trench isolation structures 12 are formed in the semiconductor substrate 10 and the pad layer structure 11, and the shallow trench isolation structures 12 isolate a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10.

As an example, the semiconductor substrate 10 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate 10 is a single crystal substrate or a polycrystalline substrate, it may also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

As an example, the pad layer structure 11 may be formed by a physical vapor deposition process or a chemical vapor deposition process, and specifically, the pad layer structure 11 may include a pad oxide layer 111 and a pad nitride layer 112, where the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 3.

As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10, and then depositing an insulating layer in the isolation trench by using chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc. The cross-sectional shape of the shallow trench isolation structure 12 may be set according to actual needs, wherein the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example in fig. 5, but is not limited thereto in the actual example. It should be noted that, when depositing the insulating layer in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required to remove the insulating layer on the surface of the pad layer structure 11.

As an example, the plurality of active regions 13 that can be isolated by the shallow trench isolation structures 12 in the semiconductor substrate 10 may be, but not limited to, arranged in an array as shown in fig. 4.

As an example, a MOS device (not shown) is formed in the active region 13, and the MOS device includes a gate, a source and a drain, wherein the source and the drain are respectively located at two opposite sides of the gate.

As an example, the following steps are also included after step 1):

removing the pad structure 11, as shown in fig. 6; specifically, the pad layer structure 11 may be removed by a dry etching process or a wet etching process;

performing ion implantation in the active region 13 to form a deep well region 131 in the active region 13, as shown in fig. 7; specifically, the type of the deep well region 131 to be formed may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs; and

a pad layer structure 11 is formed on the surface of the semiconductor substrate 10 after ion implantation, as shown in fig. 8.

The cushion layer structure 11 on the surface of the semiconductor substrate 10 is removed before ion implantation, so that the requirements of ion implantation on energy and dosage can be effectively reduced, and the difficulty of ion implantation is reduced; meanwhile, the accumulation of the edge effect of the subsequent process can be reduced.

The cushion layer structure 11 is used as an etching stop layer for removing a hard mask layer formed subsequently, so that plasma damage to the semiconductor substrate 10 caused by plasma when the hard mask layer is removed can be effectively prevented; meanwhile, the pad layer structure 11 may also serve as a stop layer for a planarization process of a subsequently formed gate conductive layer.

In step 2), please refer to step S12 in fig. 1 and fig. 9 to 10, a hard mask layer 14, a bottom anti-reflection layer 15 and a photoresist layer 16 are sequentially formed on the surface of the pad layer structure 11, wherein the hard mask layer 14, the bottom anti-reflection layer (BARC)15 and the photoresist layer 16 are sequentially stacked from bottom to top, and a first opening pattern 161 is formed in the photoresist layer 16, and the first opening pattern 161 exposes a bit line contact region 162 where a bit line contact needs to be formed and an embedded gate word line region 163 where an embedded gate word line needs to be formed.

As an example, forming the hard mask layer 14 on the surface of the pad layer structure 11 may include the following steps:

forming a first hard mask layer 141 on the surface of the pad layer structure 11; and

a second hard mask layer 142 is formed on the surface of the first hard mask layer 141.

As an example, the first hard mask layer 141 may include an amorphous carbon (α -C) layer, an amorphous silicon (α -Si) layer, or a silicon oxynitride layer (SiON), the second hard mask layer 142 may also include an amorphous carbon layer, an amorphous silicon layer, or a silicon oxynitride layer, the material of the first hard mask layer 141 may be the same as or different from the material of the second hard mask layer 142, and preferably, the material of the first hard mask layer 141 is different from the material of the second hard mask layer 142 in this embodiment.

In step 3), referring to step S13 in fig. 1 and fig. 11, the bottom anti-reflective layer 15 is etched according to the photoresist layer 16, and the first opening pattern 161 is transferred into the bottom anti-reflective layer 15, so as to form a second opening pattern 151 in the bottom anti-reflective layer 15.

As an example, the bottom anti-reflective layer 15 may be etched using, but not limited to, a dry etching process depending on the photoresist layer 16 to form the second opening patterns 151 in correspondence with the first opening patterns 161 within the bottom anti-reflective layer 15.

For example, after the second opening pattern 151 is formed in the bottom anti-reflective layer 15, a step of removing the photoresist layer 16 is further included.

In step 4), referring to step S14 in fig. 1 and fig. 12 to fig. 13, a sidewall structure 17 is formed on the sidewall of the second opening pattern 151, the sidewall structure 17 defines the position and shape of the embedded gate word line region 163, and the second opening pattern 151 outside the sidewall structure 17 defines the position and shape of the bit line contact region 162.

As an example, the forming the sidewall structure 17 on the sidewall of the second opening pattern 151 may include the following steps:

4-1) forming a side wall material layer on the surface of the bottom anti-reflection layer 15, the side wall and the bottom of the second opening pattern 151 by adopting an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process; and

4-2) removing the side wall material layer on the surface of the bottom anti-reflection layer 15 and at the bottom of the second opening pattern 151 by using a dry etching process, wherein the side wall material layer remained on the side wall of the second opening pattern 151 forms the side wall structure 17.

As an example, the sidewall structure 17 may comprise an oxide sidewall structure, i.e. the material of the sidewall structure 17 may comprise an oxide, such as silicon oxide or the like.

It should be noted that "the second opening patterns 151 outside the sidewall structures 17" refer to regions remaining after the sidewall structures 17 are formed in the second opening patterns 151.

In step 5), please refer to step S15 in fig. 1 and fig. 14 to fig. 15, a filling layer 18 is formed in the second opening pattern 151 outside the sidewall structure 17, wherein, under the same etching condition, the removal rate of the filling layer 18 is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17.

As an example, the step of forming the filling layer 18 in the second opening pattern 151 outside the sidewall structure 17 includes the following steps:

5-1) forming a filling layer 18 in the opening pattern 151 outside the sidewall structure 17 and on the surface of the bottom anti-reflection layer 15; and

5-2) etching back by adopting a dry etching process to remove the filling layer 18 on the surface of the bottom anti-reflection layer 15.

As an example, the material of the filling layer 18 should be different from the material of the bottom anti-reflection layer 15 and the material of the sidewall structure 17, so that the filling layer 18 has a different etching selection ratio from the bottom anti-reflection layer 15 and the sidewall structure 17; preferably, under the same etching condition, the removal rate of the filling layer 18 is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17, that is, under the same etching condition, the filling layer 18 has a higher selectivity ratio to the bottom anti-reflection layer 15 and the sidewall structure 17. More preferably, in the present embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, that is, the material of the filling layer 18 may include, but is not limited to, a nitride, such as silicon nitride. The selection ratio of the material of the filling layer 18 is higher than that of the bottom anti-reflection layer 15 and the sidewall structure 17, so that the filling layer 18 can be reserved when the bottom anti-reflection layer 15 and the sidewall structure 17 are removed by etching, and self-alignment can be realized when a bit line contact hole needs to be formed.

The semiconductor structure prepared by the preparation method of the semiconductor structure can define the position and the shape of the embedded grid word line region 163 needing to form the embedded grid word line and the bit line contact region 162 needing to form the bit line contact in a self-alignment manner when the side wall structure 17 and the filling layer 18 are formed, and does not need an additional photoetching process to define the bit line contact hole when the embedded grid word line and the bit line contact are prepared on the basis of the semiconductor structure, so that exposure deviation existing when the bit line contact hole is formed by photoetching is avoided, and accurate alignment of the bit line contact is further ensured; meanwhile, the preparation method of the semiconductor structure has simple process steps, and can effectively save material cost and process cost.

Example two

With continuing reference to fig. 2-15, the present invention further provides a semiconductor structure, comprising: a semiconductor substrate 10; a pad layer structure 11, wherein the pad layer structure 11 is located on the surface of the semiconductor substrate 10; the shallow trench isolation structure 12 is positioned in the semiconductor substrate 10 and the pad layer structure 11, so as to isolate a plurality of active regions 13 which are arranged at intervals in the semiconductor substrate 10; a hard mask layer 14, wherein the hard mask layer 14 is positioned on the surface of the cushion layer structure 11; a bottom anti-reflective coating 15, wherein the bottom anti-reflective coating 15 is positioned on the surface of the hard mask layer 14; a filling layer 18, wherein the filling layer 18 is located in the BARC layer 15, and the filling layer 18 defines the position and shape of the bit line contact to be formed; the side wall structure 17 is positioned in the bottom anti-reflection coating 15 and outside the filling layer 18, and the side wall structure 17 defines the position and the shape of an embedded gate word line to be formed; under the same etching condition, the removal rate of the filling layer 18 is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17.

As an example, the pad layer structure 11 includes a pad oxide layer 111 and a pad nitride layer 112, wherein the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 3.

As an example, a deep well region 131 is further formed in the active region 13, as shown in fig. 7; specifically, the type of the deep well region 131 may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs.

As an example, the hard mask layer 14 includes: the first hard mask layer 141, wherein the first hard mask layer 141 is located on the surface of the pad layer structure 11; and a second hard mask layer 142, wherein the second hard mask layer 142 is located on the surface of the first hard mask layer 141.

As an example, the sidewall structure 17 defines the position and the shape of the buried gate word line region 163 where the buried gate word line is to be formed, and the sidewall structure 17 may comprise an oxide sidewall structure, i.e. the material of the sidewall structure 17 may comprise an oxide, such as silicon oxide, etc.

As an example, the filling layer 18 defines a position and a shape of a bit line contact region 162 where the bit line contact needs to be formed, and a material of the filling layer 18 should be different from a material of the bottom anti-reflection layer 15 and a material of the sidewall structure 17, so that the filling layer 18 has a different etching selection ratio from the bottom anti-reflection layer 15 and the sidewall structure 17; preferably, under the same etching condition, the removal rate of the filling layer 18 is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17, that is, under the same etching condition, the filling layer 18 has a higher selectivity ratio to the bottom anti-reflection layer 15 and the sidewall structure 17. More preferably, in the present embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, that is, the material of the filling layer 18 may include, but is not limited to, a nitride, such as silicon nitride. The selection ratio of the material of the filling layer 18 is higher than that of the bottom anti-reflection layer 15 and the sidewall structure 17, so that the filling layer 18 can be reserved when the bottom anti-reflection layer 15 and the sidewall structure 17 are removed by etching, and self-alignment can be realized when a bit line contact hole needs to be formed.

EXAMPLE III

Referring to fig. 16, the present invention further provides a method for manufacturing a memory structure, which includes the following steps:

7) removing the filling layer and the bottom anti-reflection layer;

12) removing the hard mask layer in the bit line contact area and etching the semiconductor substrate to form bit line contact holes in the dielectric layer and the semiconductor substrate, wherein the bottoms of the bit line contact holes are sunk into the semiconductor substrate; and

In step 1), please refer to S21 in fig. 16 and fig. 17 to 20, providing a semiconductor substrate 10, and forming a pad layer structure 11 on a surface of the semiconductor substrate 10; shallow trench isolation structures 12 are formed in the semiconductor substrate 10 and the pad layer structure 11, and the shallow trench isolation structures 12 isolate a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10.

As an example, the pad layer structure 11 may be formed by a physical vapor deposition process or a chemical vapor deposition process, and specifically, the pad layer structure 11 may include a pad oxide layer 111 and a pad nitride layer 112, where the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 20.

As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10, and then depositing an insulating layer in the isolation trench by using chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc. The cross-sectional shape of the shallow trench isolation structure 12 may be set according to actual needs, wherein the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example in fig. 20, but is not limited thereto in the actual example. It should be noted that, when depositing the insulating layer in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required to remove the insulating layer on the surface of the pad layer structure 11.

As an example, the plurality of active regions 13 that can be isolated by the shallow trench isolation structures 12 in the semiconductor substrate 10 may be, but not limited to, arranged in an array as shown in fig. 19.

As an example, the following steps are also included after step 1):

removing the pad structure 11, as shown in fig. 21; specifically, the pad layer structure 11 may be removed by a dry etching process or a wet etching process;

performing ion implantation in the active region 13 to form a deep well region 131 in the active region 13, as shown in fig. 22; specifically, the type of the deep well region 131 to be formed may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs; and

a pad structure 11 is formed on the surface of the semiconductor substrate 10 after ion implantation again, as shown in fig. 23.

In step 2), referring to step S22 in fig. 16 and fig. 24 to fig. 25, a hard mask layer 14, a bottom anti-reflection layer 15 and a photoresist layer 16 are sequentially formed on the surface of the pad layer structure 11, wherein the hard mask layer 14, the bottom anti-reflection layer (BARC)15 and the photoresist layer 16 are sequentially stacked from bottom to top, and a first opening pattern 161 is formed in the photoresist layer 16, and the first opening pattern 161 exposes a bit line contact region 162 where a bit line contact needs to be formed and an embedded gate word line region 163 where an embedded gate word line needs to be formed.

In step 3), referring to step S23 in fig. 16 and fig. 26, the bottom anti-reflective layer 15 is etched according to the photoresist layer 16, and the first opening pattern 161 is transferred into the bottom anti-reflective layer 15, so as to form a second opening pattern 151 in the bottom anti-reflective layer 15.

In step 4), referring to step S24 in fig. 16 and fig. 27 to 28, a sidewall structure 17 is formed on the sidewall of the second opening pattern 151, the sidewall structure 17 defines the position and shape of the embedded gate word line region 163, and the second opening pattern 151 outside the sidewall structure 17 defines the position and shape of the bit line contact region 162.

In step 5), please refer to step S25 in fig. 16 and fig. 29 to fig. 30, forming a filling layer 18 in the second opening pattern 151 outside the sidewall structure 17, wherein, under the same etching condition, the removal rate of the filling layer 18 is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17.

In step 6), please refer to step S26 in fig. 16 and fig. 31, the hard mask layer 14 on the buried gate word line region 163 and the sidewall structures 17 are etched away, so as to form a pattern channel 19 in the bottom anti-reflection layer 15 and the hard mask layer 14, wherein the pattern channel 19 defines the position and shape of the buried gate word line.

As an example, but not limited to, the sidewall structure 17, the hard mask layer 14 located directly under the sidewall structure 17 (i.e., located in the buried gate word line region 163), and the etching process is stopped at the pad layer structure 11, that is, the pad layer structure 11 serves as an etching stop layer.

In step 7), please refer to S27 in fig. 16 and fig. 32 to 33, the filling layer 18 and the bottom anti-reflection layer 15 are removed.

As an example, the removal of the filling layer 18 and the bottom anti-reflection layer 15 includes the following steps:

7-1) etching to remove the bottom anti-reflection layer 15, as shown in FIG. 32; specifically, the bottom anti-reflection layer 15 may be removed by etching using a dry etching process;

7-2) etching to remove the second hard mask layer 142 except the bit line contact region 162, namely removing the second hard mask layer 142 except the part right below the filling layer 18; specifically, the second hard mask layer 142 outside the bit line contact region 162 may be removed by etching using, but not limited to, a dry etching process according to the filling layer 18 as a mask layer; and

7-3) removing the filling layer 18, as shown in FIG. 33; specifically, the filling layer 18 may be removed by, but not limited to, a dry etching process.

In step 8), referring to step S28 in fig. 16 and fig. 34 to fig. 36, the pad layer structure 11 at the bottom of the patterned trench 19 is removed, and the hard mask layer 14 outside the bit line contact region 162 is removed.

As an example, the step of removing the pad layer structure 11 at the bottom of the patterned trench 19 and removing the hard mask layer 14 outside the bit line contact region 162 includes the following steps:

8-1) removing the pad layer structure 11 at the bottom of the pattern trench 19, as shown in fig. 34; specifically, the pad layer structure 11 is etched according to the hard mask layer 14 to remove the exposed pad layer structure 11 located at the bottom of the pattern trench 19; more specifically, the pad layer structure 11 located at the bottom of the pattern channel 19 may be etched by, but not limited to, a dry etching process;

8-2) removing the first hard mask layer 141 outside the bit line contact region 162, as shown in FIG. 35; specifically, the first hard mask layer 141 outside the bit line contact region 162 may be removed by etching using, but not limited to, a dry etching process according to the retained second hard mask layer 142 as a mask; it should be noted that, in the process of removing the first hard mask layer 141, etching is terminated at the pad layer structure 11, that is, the pad layer structure 11 is used as an etching barrier layer; and

8-3) removing the second hard mask layer 142 of the bit line contact region 162, as shown in fig. 36; specifically, the second hard mask layer 142 located in the bit line contact region 162 may be removed by, but not limited to, a dry etching process; specifically, when the second hard mask layer 142 is removed, the pad layer structure 11, the first hard mask layer 141 located in the bit line contact region 162, and the semiconductor substrate 10 are not etched, and the etching removal rate of the etching gas for immediately removing the second hard mask layer 142 on the pad layer structure 11, the first hard mask layer 141, and the semiconductor substrate 10 is very small and can be almost ignored; this ensures that the first hard mask layer 141 in the bitline release region 162 remains when the second hard mask layer 142 is removed.

In step 9), referring to step S29 in fig. 16 and fig. 37 to 38, the semiconductor substrate 10 is etched according to the patterned trench 19 to form a buried gate word line trench 20 in the semiconductor substrate 10.

As an example, but not limited to, a dry etching process may be used to etch the semiconductor substrate 10 to form the buried gate word line trench 20 in the semiconductor substrate 10. It should be noted that, in the etching process, the semiconductor substrate 10 may be etched according to the remaining first hard mask layer 141 and the pad layer structure 11 as masks.

In step 10), referring to S210 in fig. 16 and fig. 39 to 41, a buried gate word line 21 is formed in the buried gate word line trench 20, wherein an upper surface of the buried gate word line 21 is lower than an upper surface of the semiconductor substrate 10.

As an example, forming the buried gate word line 21 in the buried gate word line trench 20 includes the following steps:

10-1) forming a gate oxide layer 211 on the sidewalls and bottom of the buried gate word line trench 20, as shown in fig. 39; specifically, the gate oxide layer 211 may be formed on the sidewall and the bottom of the buried gate word line trench 20 by, but not limited to, a thermal oxidation process;

10-2) forming a gate conductive layer 212 in the embedded gate word line trench 20 and on the surface of the pad layer structure 11, where the gate conductive layer 212 fills a gap between the embedded gate word line trench 20 and the bit line contact region 162 (i.e., a gap between the remaining first hard mask layers 141), and covers the remaining hard mask layer 14 (at this time, the remaining hard mask layer 14 is the first hard mask layer 141);

10-3) removing a portion of the gate conductive layer 212 by using a chemical polishing (CMP) process, such that the upper surface of the remaining gate conductive layer 212 is flush with the upper surface of the remaining hard mask layer 14 (i.e., the first hard mask layer 141 in fig. 40), as shown in fig. 40; and

10-4) etching back the gate conductive layer 212 to remove the gate conductive layer 212 on the surface of the pad layer structure 11 and remove a portion of the gate conductive layer 212 in the buried gate word line trench 20 to form the buried gate word line 21, as shown in fig. 41. It should be noted that the phrase "the upper surface of the buried gate word line 21 is lower than the upper surface of the semiconductor substrate 10" in this example means that the upper surface of the dummy gate conductive layer 212 in the buried gate word line 21 is lower than the upper surface of the semiconductor substrate 10.

As an example, the material of the gate conductive layer 212 in the buried gate word line 21 includes at least one of titanium nitride, tantalum nitride, and tungsten, that is, the material of the gate conductive layer 212 may include a low resistivity metal such as titanium nitride, tantalum nitride, or tungsten, or may include at least two of titanium nitride, tantalum nitride, and tungsten, in this case, the gate conductive layer 212 may be a conductive layer of a composite material composed of at least two materials of titanium nitride, tantalum nitride, and tungsten, or may be a conductive layer including at least two layers of titanium nitride, tantalum nitride, and tungsten.

In step 11), referring to step S211 and fig. 42 in fig. 16, a dielectric layer 22 is formed in the buried gate word line trench 20 and on the surface of the pad layer structure 11; the dielectric layer 22 fills the buried gate word line trench 20 and covers the surface of the pad layer structure 11.

By way of example, the dielectric layer 22 may be formed using, but is not limited to, a physical vapor deposition process or a chemical vapor deposition process, and the dielectric layer 22 may include, but is not limited to, an oxide layer or a nitride layer, i.e., the material of the dielectric layer 22 may include, but is not limited to, an oxide or a nitride. Specifically, the oxide may include silicon oxide, and the nitride may include silicon nitride. In this step, the first hard mask layer 141 is remained, and the first hard mask layer 141 defines the position of the bit line contact hole 23 to be formed subsequently, so that the self-alignment of the bit line contact hole 23 to be formed subsequently can be realized.

In step 12), referring to step S212 in fig. 16 and fig. 43 to 44, the hard mask layer 14 in the bit line contact region 162 is removed and the semiconductor substrate 10 is etched, so as to form a bit line contact hole 23 in the dielectric layer 22 and the semiconductor substrate 10, and the bottom of the bit line contact hole 23 is sunk into the semiconductor substrate 10.

As an example, the hard mask layer 14 and the semiconductor substrate 10 may be etched by a dry etching process to form the bit line contact hole 23, and since the position and the shape of the bit line contact hole 23 are predefined in the retained first hard mask layer 141, the bit line contact hole 23 may be etched according to the retained first hard mask layer 141 without a photolithography process, thereby implementing precise self-alignment of the bit line contact hole 23.

It should be noted that, because the pad layer structure 11 is disposed below the first hard mask layer 141, when the first hard mask layer 141 is removed by etching, the pad layer structure 11 located right below the first hard mask layer 141 is also removed.

The bit line contact hole 23 extends into the semiconductor substrate 10 in addition to the dielectric layer 22, so that the contact area of the subsequently formed bit line contact and the active region 13 can be increased, that is, the contact area of the subsequently formed bit line contact and the active region 13 can be increased, and thus the contact resistance can be reduced.

It should be noted that the size of the bit line contact hole 23 extending to the active region 13 may be the same as the size of the portion of the bit line contact hole 23 located in the dielectric layer 22, and the size of the bit line contact hole 23 extending to the active region 13 may also be larger than the size of the portion of the bit line contact hole 23 located in the dielectric layer 22.

In step 13), referring to step S213 in fig. 16 and fig. 45 to 46, the bit line contact hole 23 is filled with a contact material to form a bit line contact 24.

As an example, filling the bit line contact hole 23 with a contact material to form the bit line contact 24 may include the following steps:

13-1) forming contact materials in the bit line contact holes 23 and on the surface of the dielectric layer 22 by adopting a physical vapor deposition process or a chemical vapor deposition process;

13-2) removing the contact material on the surface of the dielectric layer 22 by using a chemical mechanical polishing process, wherein the contact material remained in the bit line contact hole 23 constitutes the bit line contact 24.

By way of example, the material of the bitline contact 24 includes, but is not limited to, polysilicon. In particular, the material of the bit line contact 24 may include doped polysilicon to make the bit line contact 24 conductive. The bit line contact 24 serves as a structure for a subsequently formed bit line to be connected to the active region 13.

Example four

Referring to fig. 17 to 46, the present invention further provides a memory structure, which includes a semiconductor substrate 10, a shallow trench isolation structure 12 formed in the semiconductor substrate 10, the shallow trench isolation structure 12 isolating a plurality of active regions 13 arranged at intervals in the semiconductor substrate 10; a plurality of buried gate word lines 21 arranged at intervals, located in the active region 13, and an upper surface of the buried gate word lines 21 is lower than an upper surface of the semiconductor substrate 10; a bit line contact 24, the bit line contact 24 being located on the semiconductor substrate 10; and a dielectric layer 22, wherein the dielectric layer 22 is located on the surface of the buried gate word line 21 and fills the gap between the bit line contacts 24.

As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10, and then depositing an insulating layer in the isolation trench by using chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, etc. The cross-sectional shape of the shallow trench isolation structure 12 may be set according to actual needs, wherein the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example in fig. 46, but is not limited thereto in the actual example. It should be noted that, when depositing the insulating layer in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required to remove the insulating layer on the surface of the pad layer structure 11.

As an example, the plurality of active regions 13 that can be isolated by the shallow trench isolation structures 12 in the semiconductor substrate 10 may be, but not limited to, arranged in an array as shown in fig. 45.

As an example, a deep well region 131 is also formed in the active region 13, as shown in fig. 46; specifically, the type of the deep well region 131 may be selected according to actual needs, and may be selected as a P-type doped region or an N-type doped region according to actual needs.

As an example, the memory structure further includes a pad structure 11, where the pad structure 11 is located on the surface of the semiconductor substrate 10 between the buried gate word line 21 and the bit line contact 24.

As an example, the pad layer structure 11 includes a pad oxide layer 111 and a pad nitride layer 112, wherein the pad oxide layer is located on the surface of the semiconductor substrate 10, and the pad nitride layer 112 is located on the surface of the pad oxide layer 111, as shown in fig. 46. The cushion layer structure 11 is used as an etching stop layer for removing a hard mask layer formed subsequently, so that plasma damage to the semiconductor substrate 10 caused by plasma when the hard mask layer is removed can be effectively prevented; meanwhile, the pad layer structure 11 may also serve as a stop layer for a planarization process of a subsequently formed gate conductive layer.

As an example, the buried gate word line 21 includes a gate oxide layer 211 and a gate conductive layer 212, the gate conductive layer 212 is located in the active region 13, and an upper surface of the gate conductive layer 212 is lower than an upper surface of the semiconductor substrate 10; the gate oxide layer 211 is located in the active region 13 and located between the gate conductive layer 212 and the semiconductor substrate 10.

As an example, the bottom of the bitline contact 24 is recessed within the semiconductor body 10. The bottom of the bit line contact 24 is sunk into the semiconductor substrate 10, so that the contact area of the bit line contact 24 and the active region 13 can be increased, the contact area of the bit line 25 and the active region 13 is increased, and the contact resistance is reduced.

In summary, the present invention provides a semiconductor structure, a memory structure and a method for fabricating the same, wherein the method for fabricating the semiconductor structure comprises the following steps: 1) providing a semiconductor substrate, and forming a cushion layer structure on the surface of the semiconductor substrate; forming shallow trench isolation structures in the semiconductor substrate and the cushion layer structure, wherein the shallow trench isolation structures isolate a plurality of active regions which are distributed at intervals in the semiconductor substrate; 2) sequentially forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the cushion layer structure, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially overlapped from bottom to top, a first opening pattern is formed in the photoresist layer, and the first opening pattern exposes a bit line contact area needing to form bit line contact and an embedded grid word line area needing to form an embedded grid word line; 3) etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer so as to form a second opening pattern in the bottom anti-reflection layer; 4) forming a side wall structure on the side wall of the second opening pattern, wherein the side wall structure defines the position and the shape of the word line region of the embedded grid, and the second opening pattern outside the side wall structure defines the position and the shape of the bit line contact region; and 5) forming a filling layer in the second opening pattern outside the side wall structure, wherein under the same etching condition, the removal rate of the filling layer is less than that of the bottom anti-reflection layer and that of the side wall structure. According to the semiconductor structure and the preparation method thereof, the position and the shape of the contact of the embedded grid word line and the bit line are defined when the side wall structure and the filling layer are formed, and the bit line contact hole is defined without an additional photoetching process when the embedded grid word line and the bit line contact are prepared on the basis of the semiconductor structure, so that photoetching exposure deviation can be avoided, and accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the semiconductor structure is simple, the process steps are simple, and the material cost and the process cost are saved; according to the memory structure and the preparation method thereof, the positions and the shapes of the embedded grid word line and the embedded grid bit line contact are respectively defined by forming the side wall structure and the filling layer, and the bit line contact hole is defined without an additional photoetching process when the bit line contact hole is formed, so that photoetching exposure deviation can be avoided, and accurate alignment of the bit line contact is ensured; meanwhile, the preparation method of the memory structure is simple, the process steps are simple, and the material cost and the process cost are saved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, comprising the steps of:

2. The method for manufacturing a semiconductor structure according to claim 1, further comprising the following steps between the step 1) and the step 2):

removing the cushion layer structure;

3. The method of claim 1 or 2, wherein the pad layer structure comprises:

a pad oxide layer on the surface of the semiconductor substrate; and

and the pad nitride layer is positioned on the surface of the pad oxide layer.

4. The method of claim 1, wherein the step 2) of forming the hard mask layer on the surface of the pad layer structure comprises the steps of:

5. A semiconductor structure, comprising:

a semiconductor substrate;

6. The semiconductor structure of claim 5, wherein a deep well region is further formed within the active region.

7. The semiconductor structure of claim 5, wherein the pad layer structure comprises:

a pad oxide layer on the surface of the semiconductor substrate;

and the pad nitride layer is positioned on the surface of the pad oxide layer.

8. The semiconductor structure of claim 5, wherein the hard mask layer comprises:

9. A method for preparing a memory structure is characterized by comprising the following steps:

7) removing the filling layer and the bottom anti-reflection layer;

12) removing the hard mask layer in the bit line contact area and etching the semiconductor substrate to form a bit line contact hole in the dielectric layer and the semiconductor substrate, wherein the bottom of the bit line contact hole is sunk into the semiconductor substrate;

and

10. The method for manufacturing the memory structure according to claim 9, further comprising the following steps between the step 1) and the step 2):

removing the cushion layer structure;

11. The method of manufacturing a memory structure according to claim 9 or 10, wherein the pad layer structure comprises:

a pad oxide layer on the surface of the semiconductor substrate; and

and the pad nitride layer is positioned on the surface of the pad oxide layer.

12. The method for manufacturing a memory structure according to claim 9, wherein the step 2) of forming the hard mask layer on the surface of the pad layer structure comprises the steps of:

13. The method for manufacturing a memory structure according to claim 12, wherein the step 7) comprises the steps of:

7-1) etching to remove the bottom anti-reflection layer;

7-3) removing the filling layer.

14. The method of manufacturing a memory structure according to claim 13, wherein step 8) comprises the steps of:

8-1) removing the cushion layer structure at the bottom of the pattern channel;

8-2) removing the first hard mask layer outside the bit line contact area; and

8-3) removing the second hard mask layer in the bit line contact area.

15. The method of manufacturing a memory structure according to claim 9, wherein step 10) comprises the steps of:

16. A memory structure, comprising:

bit line contacts on the semiconductor substrate; and

17. The memory structure of claim 16, wherein a deep well region is further formed within the active region.

18. The memory structure of claim 16, further comprising a pad structure on a surface of the semiconductor substrate between the buried gate word line and the bit line contact.

19. The memory structure of claim 18, wherein the pad structure comprises:

a pad oxide layer on the surface of the semiconductor substrate; and

and the pad nitride layer is positioned on the surface of the pad oxide layer.

20. The memory structure of claim 16, wherein a bottom portion of the bitline contact is recessed within the semiconductor substrate.

21. The memory structure of claim 16, wherein the buried gate word line comprises: