CN114792624A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

Info

Publication number
CN114792624A
CN114792624A CN202110106512.6A CN202110106512A CN114792624A CN 114792624 A CN114792624 A CN 114792624A CN 202110106512 A CN202110106512 A CN 202110106512A CN 114792624 A CN114792624 A CN 114792624A
Authority
CN
China
Prior art keywords
layer
forming
core
semiconductor structure
core layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110106512.6A
Other languages
Chinese (zh)
Inventor
徐晓伟
朱辰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202110106512.6A priority Critical patent/CN114792624A/en
Publication of CN114792624A publication Critical patent/CN114792624A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region; forming a first core layer on the first region; forming a side wall material layer on the side wall of the first core layer; forming a second core layer on the layer to be etched; forming a barrier layer on the second region, wherein part of the barrier layer is internally provided with a partition groove; modifying the second core layer to form a modified zone in the second core layer; and removing the first core layer and the second core layer covered by the barrier layer to form a first opening and a second opening. Through forming the wall slot in the barrier layer in this technical scheme, after getting rid of the second core layer that the barrier layer covered, the modification zone that exposes by the isolation slot is overall structure with other modification zones, has stronger stability, and consequently the modification zone that exposes by the isolation slot is difficult for the slope collapse, and then has reduced the risk that the short circuit appears in the second conducting layer of follow-up formation for the performance of the semiconductor structure who finally forms effectively promotes.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the increase of circuit integration and scale, the unit device size in the circuit is continuously reduced, and the requirements on the integrated circuit manufacturing process are continuously increased, for example, the critical dimension is continuously reduced, and the requirements on the photoetching resolution in the chip manufacturing are higher and higher.
In the process of manufacturing semiconductor devices, a pattern on a reticle is generally transferred onto a substrate using a photolithography process. The photoetching process comprises the following steps: providing a substrate; forming a photoresist on a semiconductor substrate; exposing and developing the photoresist to form a patterned photoresist, so that the pattern on the mask is transferred into the photoresist; etching the substrate by taking the patterned photoresist as a mask so as to transfer the pattern on the photoresist to the substrate; and removing the photoresist.
However, the prior art pattern transfer process still has problems.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, wherein the layer to be etched comprises a plurality of first areas and a plurality of second areas, the first areas and the second areas are arranged along a first direction, and the first areas are positioned between the adjacent second areas; forming a first core layer on the first region, the first core layer extending in a second direction, the first direction and the second direction being perpendicular; forming a side wall material layer on the surface of the side wall of the first core layer; forming a second core layer on the layer to be etched, wherein the second core layer covers the side wall of the side wall material layer; after forming the second core layer, forming a barrier layer on the second region, wherein the barrier layer covers a part of the top surface of the second core layer, the barrier layer extends along the second direction, and a part of the barrier layer is internally provided with an isolation groove which penetrates through the barrier layer along the first direction; modifying the second core layer by taking the barrier layer as a mask, and forming a modified area in the second core layer, wherein modified ions are arranged in the modified area; after the modified area is formed, the barrier layer, the first core layer and the second core layer covered by the barrier layer are removed, and a first opening and a second opening are formed in the second core layer.
Optionally, the method for forming the first core layer includes: forming a first core material layer on the layer to be etched; forming a first patterned layer on the first core material layer, the first patterned layer exposing a portion of a top surface of the first core material layer; and etching the first core material layer by taking the first patterning layer as a mask until the top surface of the layer to be etched is exposed, so as to form the first core layer.
Optionally, the material of the first core layer includes: one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterning materials, spin-on carbon, and silicon carbide.
Optionally, the method for modifying the zone includes: and performing injection treatment on the modified ions on the second core layer by taking the barrier layer as a mask to form the modified area.
Optionally, the modifying ions include: one or more of boron ions, carbon ions, phosphorus ions, and arsenic ions.
Optionally, the implantation parameters of the modified ions include: the injection energy is 1.5 KeV-13 KeV; the implantation dose is 1.0E14atoms/cm 2 ～1.0E16atoms/cm 2 。
Optionally, the side wall material layer is further located on the top surface of the first core layer and the top surface of the layer to be etched; and after the modified region is formed, removing the side wall material layer positioned at the top of the first core layer.
Optionally, the forming process of the side wall material layer includes an atomic layer deposition process.
Optionally, the material of the sidewall material layer includes: one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.
Optionally, a part of the barrier layer covers the side wall material layer on the side wall of the first core layer.
Optionally, the method for forming the second core layer includes: forming a core material film on the layer to be etched, wherein the core material film covers the side wall material layer; and carrying out planarization treatment on the core material film until the side wall material layer positioned on the top surface of the first core layer is exposed, and forming the second core layer.
Optionally, the process of performing the planarization treatment on the core material film includes one or more of a chemical mechanical polishing process, a wet etching process, and a dry etching process.
Optionally, the material of the second core layer includes: one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterning materials, spin-on carbon, and silicon carbide.
Optionally, the method for forming the barrier layer includes: forming an initial barrier layer on the layer to be etched; forming a second patterned layer on the initial barrier layer, the second patterned layer exposing a portion of a top surface of the initial barrier layer; and etching the initial barrier layer by taking the second patterning layer as a mask until the top surface of the second core layer is exposed to form the barrier layer.
Optionally, the material of the barrier layer is different from the material of the second core layer.
Optionally, the material of the barrier layer includes: nitride, oxide or oxynitride.
Optionally, the layer to be etched includes: the side wall material layer and the first core layer are located on the first mask layer.
Optionally, the material of the first mask layer includes: silicon oxide, silicon nitride, titanium oxide, tungsten carbide, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.
Optionally, after the first opening and the second opening are formed, the first mask layer is etched by using the second core layer and the side wall material layer as masks, a first trench and a second trench are formed in the first mask layer, the first trench is exposed through the first opening, and the second trench is exposed through the second opening.
Optionally, after forming the first groove and the second groove, the method further includes: and etching the substrate by taking the first mask layer as a mask, and forming a first target groove and a second target groove in the substrate, wherein the first target groove is exposed out of the first groove, and the second target groove is exposed out of the second groove.
Optionally, after forming the first target groove and the second target groove, the method further includes: forming a first conductive layer in the first target groove; and forming a second conductive layer in the second target groove.
Optionally, the material of the first conductive layer includes: copper, aluminum, tungsten, cobalt, tantalum nitride, titanium nitride, ruthenium nitride, and graphene.
Optionally, the material of the second conductive layer includes: copper, aluminum, tungsten, cobalt, tantalum nitride, titanium nitride, ruthenium nitride, and graphene.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, a blocking groove is formed in part of the blocking layer, and the blocking groove penetrates through the blocking layer along the first direction; and modifying the second core layer by taking the barrier layer as a mask, and forming a modified area in the second core layer, wherein the modified area has modified ions. Due to the fact that after modification treatment, the etching rates of the modified area and the second core layer are different, in the subsequent process of removing the second core layer covered by the barrier layer, the modified area exposed by the partition groove can be guaranteed to be less damaged, then partitions are formed among parts of the second target grooves formed subsequently, partitions are formed among parts of the second conductive layers formed subsequently, and therefore the requirements of electrical design are met. In the technical scheme, the isolation groove is formed in part of the barrier layer, the barrier layer with larger characteristic dimension is reserved, the whole structure is stable, and after the second core layer covered by the barrier layer is removed, the modified area exposed by the isolation groove and the modified area formed without being covered are of the whole structure and have stronger stability, so that the modified area exposed by the isolation groove is not prone to tilting and collapsing, the risk of short circuit of the subsequently formed second conducting layer is reduced, and the performance of the finally formed semiconductor structure is effectively improved.
Further, part of the barrier layer covers the side wall material layer on the side wall of the first core layer. The barrier layer partially covers the side wall material layer on the side wall of the first core layer, so that the distance between the first conducting layer and the second conducting layer which are correspondingly formed subsequently is the thickness of the side wall material layer, the distance between the first conducting layer and the second conducting layer can be effectively reduced, and the integration level of the semiconductor device structure is favorably improved.
Drawings
Fig. 1 to 7 are schematic structural views of a semiconductor structure;
fig. 8 to 21 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the prior art pattern transfer process still has problems. The following detailed description will be made in conjunction with the accompanying drawings.
Fig. 1 to 7 are schematic structural diagrams illustrating a process of forming a semiconductor structure.
Referring to fig. 1 and fig. 2, fig. 2 is a schematic cross-sectional view taken along line a-a in fig. 1, providing a layer to be etched 100, and forming a plurality of core layers 101 arranged in parallel on the layer to be etched 100; side walls 102 are formed on the side walls of the core layer 101.
Referring to fig. 3, the directions of the views in fig. 3 and fig. 2 are the same, the core layer 101 is removed, and a first opening 103 is formed in the side wall 102; a partition structure 104 is formed in a portion of the first opening 103.
Referring to fig. 4 and fig. 5, fig. 5 is a schematic cross-sectional view taken along line B-B in fig. 4, a sacrificial layer 105 is formed on the layer to be etched 100, the sacrificial layer 105 covers a portion of the first opening 103 and a portion of the sidewall 102, and the sacrificial layer 105 exposes the blocking structure 104; and etching the layer to be etched 100 by using the sacrificial layer 105, the partition structure 104 and part of the side wall 102 as masks, and forming a groove 106 in the layer to be etched 100.
Referring to fig. 6 and 7, fig. 7 is a schematic cross-sectional view taken along line C-C in fig. 6, after the trench 106 is formed, the sacrificial layer 105, the sidewall spacers 102 and the isolation structures 104 are removed; a conductive layer 107 is formed within the trench 105.
In this embodiment, the purpose of forming the partition structure 104 in a part of the first opening 103 is to: a mask is provided through the isolation structure 104, so that a portion of the trench 106 formed subsequently is isolated, and a portion of the conductive layer 107 formed finally is isolated, thereby meeting the requirements of electrical design. However, as the size of the unit devices in the circuit is reduced, the feature size of the position where the conductive layer 107 is blocked is small, and thus the feature size of the blocking structure 104 is required to be small. When the feature size of the partition structure 104 is small, the partition structure 104 is prone to tilt and collapse or be partially etched and removed in a subsequent etching process, so that the conductive layer 107 to be partitioned is prone to short-circuiting (as shown in a portion a in fig. 6), and does not meet the electrical design requirement, thereby affecting the performance of the finally formed semiconductor structure.
On the basis, the invention provides a method for forming a semiconductor structure, which is characterized in that a blocking groove is formed in part of the blocking layer, so that the blocking layer with larger characteristic dimension is reserved, the whole structure is more stable, and after the second core layer covered by the blocking layer is removed, the modified area exposed by the isolation groove and the modified area formed without being covered are of an integral structure and have stronger stability, so that the modified area exposed by the isolation groove is not easy to incline and collapse, the risk of short circuit of the subsequently formed second conducting layer is further reduced, and the performance of the finally formed semiconductor structure is effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 8 to 21 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 8 and 9, fig. 9 is a schematic cross-sectional view taken along line D-D in fig. 8, and a layer to be etched is provided, where the layer to be etched includes a plurality of first regions I and a plurality of second regions II, the first regions I and the second regions II are arranged along a first direction X, and the first regions I are located between the adjacent second regions II.
In this embodiment, the layer to be etched includes: a substrate 200 and a first mask layer 201 on the substrate 200.
In this embodiment, the substrate 200 is a low K dielectric layer (K is less than or equal to 3.9); in other embodiments, the material of the substrate comprises silicon oxide.
The material of the first mask layer 201 includes: silicon oxide, silicon nitride, titanium oxide, tungsten carbide, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride. In this embodiment, the material of the first mask layer 201 is silicon oxide.
Referring to fig. 10, the view directions of fig. 10 and fig. 9 are the same, a first core layer 202 is formed on the first region I, the first core layer 202 extends along a second direction Y, and the first direction X is perpendicular to the second direction Y.
In this embodiment, the first core layer 202 is used to provide size and occupation position for a first conductive layer to be formed later.
In this embodiment, the method for forming the first core layer 202 includes: forming a first core material layer (not shown) on the layer to be etched; forming a first patterned layer (not shown) on the first core material layer, the first patterned layer exposing a portion of a top surface of the first core material layer; and etching the first core material layer by using the first patterning layer as a mask until the top surface of the layer to be etched is exposed, so as to form the first core layer 202.
The material of the first core layer 202 includes: amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, Advanced Patterning Film (APF), spin-on carbon, and silicon carbide. In this embodiment, amorphous silicon is used as the material of the first core layer 202.
Referring to fig. 11, a side wall material layer 203 is formed on the surface of the side wall of the first core layer 202.
In this embodiment, a spacer material layer 203 is formed on the sidewall of the first core layer 202 to provide a space mask for the first conductive layer and the second conductive layer to be formed subsequently.
In this embodiment, the side wall material layer 203 is also located on the top surface of the first core layer 202 and the top surface of the layer to be etched.
In this embodiment, the forming process of the sidewall material layer 203 includes an atomic layer deposition process.
The material of the sidewall material layer 203 comprises: one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In this embodiment, the material of the sidewall material layer 203 is silicon nitride.
Referring to fig. 12, a second core layer 204 is formed on the layer to be etched, and the second core layer 204 covers the sidewall of the sidewall material layer 203.
In this embodiment, the method for forming the second core layer 204 includes: forming a core material film (not shown) on the layer to be etched, wherein the core material film covers the side wall material layer 203; the core material film is planarized until the sidewall material layer 203 on the top surface of the first core layer 202 is exposed, forming the second core layer 204.
The process for carrying out the planarization treatment on the core material film comprises one or more of a chemical mechanical polishing process, a wet etching process and a dry etching process. In this embodiment, the planarization process for the core material film is a chemical mechanical polishing process.
The material of the second core layer 204 includes: one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterning materials, spin-on carbon, and silicon carbide. In this embodiment, amorphous silicon is used as the material of the second core layer 204.
Referring to fig. 13 and 14, fig. 14 is a schematic cross-sectional view taken along line E-E in fig. 13, after forming the second core layer 204, forming a barrier layer 205 on the second region II, where the barrier layer 205 covers a portion of the top surface of the second core layer 204, the barrier layer 205 extends along the second direction Y, and a portion of the barrier layer 205 has an isolation trench 206 therein, and the isolation trench 206 penetrates through the barrier layer 205 along the first direction X.
In this embodiment, the blocking layer 205 is used to provide a size and a footprint for a subsequently formed second conductive layer.
In this embodiment, an isolation trench 206 is provided in a portion of the barrier layer 205, which aims to: the second conductive layer is used for isolating a part of the second conductive layer formed subsequently, so that the requirement of electrical design is met.
In this embodiment, the method for forming the barrier layer 205 includes: forming an initial barrier layer (not shown) on the layer to be etched; forming a second patterned layer (not shown) on the initial barrier layer, the second patterned layer exposing a portion of a top surface of the initial barrier layer; and etching the initial barrier layer by using the second patterning layer as a mask until the top surface of the second core layer is exposed, thereby forming the barrier layer 205.
In this embodiment, the material of the barrier layer is different from the material of the second core layer.
The material of the barrier layer 205 includes: nitride, oxide or oxynitride. In this embodiment, the material of the barrier layer 205 is silicon oxide.
In this embodiment, a portion of the barrier layer 205 covers the side wall material layer 203 on the side wall of the first core layer 202. By covering part of the barrier layer 205 on the side wall material layer 203 on the side wall of the first core layer 202, the distance between the first conductive layer and the second conductive layer which are formed correspondingly subsequently is the thickness of the side wall material layer 203, so that the distance between the first conductive layer and the second conductive layer can be effectively reduced, and the integration level of the semiconductor device structure can be improved.
Referring to fig. 15 and 16, fig. 16 is a schematic cross-sectional view taken along line F-F in fig. 15, in which the barrier layer 205 is used as a mask to perform a modification process on the second core layer 204, so as to form a modified region 207 in the second core layer 204, and the modified region 207 has modified ions therein.
In this embodiment, by forming the modified region 207 within the second core layer 204, the purpose is to: the etching rates of the modified region 207 and the second core layer 204 are different, so that in the subsequent process of removing the second core layer 204 covered by the blocking layer 205, the modified region 207 exposed by the partition groove 206 can be ensured to be less damaged, a partition is formed between parts of the second target grooves formed subsequently, and a partition is formed between parts of the second conductive layers formed subsequently, so that the requirement of electrical design is met.
In this embodiment, the method for forming the modified region 207 includes: the second core layer 204 is implanted with the modified ions using the blocking layer 205 as a mask, so as to form the modified region 207.
The modifying ions include: one or more of boron ions, carbon ions, phosphorus ions, and arsenic ions. In this embodiment, the modifying ion is a carbon ion.
In this embodiment, the implantation parameters of the modified ions include: the injection energy is 1.5 KeV-13 KeV; the implantation dose is 1.0E14atoms/cm 2 ～1.0E16atoms/cm 2 。
Referring to fig. 17, the view directions of fig. 17 and fig. 16 are the same, after the modified region 207 is formed, the barrier layer 205, the first core layer 202 and the second core layer 204 covered by the barrier layer 205 are removed, and a first opening 208 and a second opening 209 are formed in the second core layer 204.
In the present technical solution, the blocking trench 206 is formed in a portion of the blocking layer 205, so that the blocking layer 205 with a large feature size is retained, so that the overall structure is relatively stable, and after the second core layer 204 covered by the blocking layer 205 is removed, the modified region 207 exposed by the blocking trench 206 and the modified region 207 formed without being covered are of an overall structure and have relatively strong stability, so that the modified region 207 exposed by the blocking trench 206 is not prone to tilt and collapse, thereby reducing the risk of short circuit of the subsequently formed second conductive layer, and effectively improving the performance of the finally formed semiconductor structure.
In this embodiment, in the process of removing the barrier layer 205, the first core layer 202, and the second core layer 204 covered by the barrier layer 205, the method further includes: the side wall material layer 203 on top of the first core layer 202 is removed.
In this embodiment, the process of removing the barrier layer 205, the first core layer 202, and the second core layer 204 covered by the barrier layer 205 adopts a dry etching process; in other embodiments, the barrier layer, the first core layer, and the second core layer covered by the barrier layer may also be removed by etching using a wet etching process or a combination of a dry etching process and a wet etching process.
Referring to fig. 18, after the first opening 208 and the second opening 209 are formed, the first mask layer 201 is etched by using the second core layer 204 and the sidewall spacer material layer 203 as masks, a first trench 210 and a second trench 211 are formed in the first mask layer 201, the first opening 208 exposes the first trench 210, and the second opening 209 exposes the second trench 211.
In this embodiment, after the first trench 210 and the second trench 211 are formed, the modified region 207 and the sidewall material layer 203 are removed. In other embodiments, after the first trench and the second trench are formed, the modified region and the sidewall spacer material layer may not be removed, and in a subsequent process, the substrate is etched by using the second core layer, the sidewall spacer material layer, and the first mask layer as masks.
In this embodiment, a dry etching process is used to etch the first mask layer 201; in other embodiments, the first mask layer may also be removed by a wet etching process or by etching combining dry etching and wet etching.
Referring to fig. 19, after the first trench 210 and the second trench 211 are formed, the substrate 200 is etched by using the first mask layer 201 as a mask, and a first target trench 212 and a second target trench 213 are formed in the substrate 200, wherein the first trench 210 exposes the first target trench 212, and the second trench 211 exposes the second target trench 213.
The process for etching the substrate by using the first mask layer 201 as a mask includes one or a combination of a dry etching process and a wet etching process. In this embodiment, a dry etching process is adopted in the process of etching the substrate by using the first mask layer 201 as a mask.
In this embodiment, after the first target groove 212 and the second target groove 213 are formed, the first mask layer 201 is removed.
Referring to fig. 20 and 21, fig. 21 is a schematic cross-sectional view taken along line G-G of fig. 20, after the first target groove 212 and the second target groove 213 are formed, a first conductive layer 214 is formed in the first target groove 212; a second conductive layer 215 is formed within the second target groove 213.
In this embodiment, the method of forming the first conductive layer 214 and the second conductive layer 215 includes: forming a conductive film (not shown) in the first target groove 212 and the second target groove 213, the conductive film covering the substrate; the conductive film is planarized until the substrate 200 is exposed, the first conductive layer 214 is formed in the first target groove 212, and the second conductive layer 215 is formed in the second target groove 213.
The material of the first conductive layer 214 includes: copper, aluminum, tungsten, cobalt, tantalum nitride, titanium nitride, ruthenium nitride, and graphene. In this embodiment, the material of the first conductive layer 214 is copper.
The material of the second conductive layer 215 includes: copper, aluminum, tungsten, cobalt, tantalum nitride, titanium nitride, ruthenium nitride, and graphene. In this embodiment, the material of the second conductive layer 215 is copper.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (23)

1. A method of forming a semiconductor structure, comprising:
providing a layer to be etched, wherein the layer to be etched comprises a plurality of first areas and a plurality of second areas, the first areas and the second areas are arranged along a first direction, and the first areas are positioned between the adjacent second areas;
forming a first core layer on the first region, the first core layer extending in a second direction, the first direction and the second direction being perpendicular;
forming a side wall material layer on the surface of the side wall of the first core layer;
forming a second core layer on the layer to be etched, wherein the second core layer covers the side wall of the side wall material layer;
after forming the second core layer, forming a barrier layer on the second region, wherein the barrier layer covers a part of the top surface of the second core layer, the barrier layer extends along the second direction, and a part of the barrier layer is internally provided with an isolation groove which penetrates through the barrier layer along the first direction;
modifying the second core layer by taking the barrier layer as a mask, and forming a modified area in the second core layer, wherein modified ions are arranged in the modified area;
after the modified area is formed, the barrier layer, the first core layer and the second core layer covered by the barrier layer are removed, and a first opening and a second opening are formed in the second core layer.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first core layer comprises: forming a first core material layer on the layer to be etched; forming a first patterned layer on the first layer of core material, the first patterned layer exposing a portion of a top surface of the first layer of core material; and etching the first core material layer by taking the first patterning layer as a mask until the top surface of the layer to be etched is exposed, so as to form the first core layer.
3. The method of forming a semiconductor structure according to claim 1, wherein the material of the first core layer comprises: one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterning materials, spin-on carbon, and silicon carbide.
4. The method of forming a semiconductor structure of claim 1, wherein the method of forming the modified region comprises: and performing the implantation treatment of the modified ions on the second core layer by taking the barrier layer as a mask to form the modified area.
5. The method of forming a semiconductor structure of claim 1, wherein the modifying ions comprise: one or more of boron ions, carbon ions, phosphorus ions, and arsenic ions.
6. The method of forming a semiconductor structure of claim 4, wherein the parameters of the modified ion implantation process comprise: the injection energy is 1.5 KeV-13 KeV; the implantation dose is 1.0E14atoms/cm 2 ～1.0E16atoms/cm 2 。
7. The method according to claim 1, wherein the spacer material layer is further disposed on a top surface of the first core layer and a top surface of the layer to be etched; and after the modified region is formed, removing the side wall material layer positioned at the top of the first core layer.
8. The method for forming the semiconductor structure according to claim 7, wherein the forming process of the side wall material layer comprises an atomic layer deposition process.
9. The method of claim 1, wherein the material of the sidewall spacer material layer comprises: one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.
10. The method of claim 1, wherein a portion of the barrier layer covers the sidewall spacer material layer on the sidewall of the first core layer.
11. The method of forming a semiconductor structure according to claim 7, wherein the method of forming the second core layer comprises: forming a core material film on the layer to be etched, wherein the core material film covers the side wall material layer; and carrying out planarization treatment on the core material film until the side wall material layer positioned on the top surface of the first core layer is exposed to form the second core layer.
12. The method of forming a semiconductor structure according to claim 11, wherein the planarization process for the core material film comprises one or more of a chemical mechanical polishing process, a wet etching process, and a dry etching process.
13. The method of forming a semiconductor structure according to claim 1, wherein the material of the second core layer comprises: one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterning materials, spin-on carbon, and silicon carbide.
14. The method of forming a semiconductor structure of claim 1, wherein the method of forming the barrier layer comprises: forming an initial barrier layer on the layer to be etched; forming a second patterned layer on the initial barrier layer, the second patterned layer exposing a portion of a top surface of the initial barrier layer; and etching the initial barrier layer by taking the second patterning layer as a mask until the top surface of the second core layer is exposed to form the barrier layer.
15. The method of forming a semiconductor structure of claim 1, wherein a material of the barrier layer is different from a material of the second core layer.
16. The method of forming a semiconductor structure of claim 15, wherein the material of the barrier layer comprises: nitride, oxide or oxynitride.
17. The method of forming a semiconductor structure of claim 1, wherein the layer to be etched comprises: the side wall material layer and the first core layer are located on the first mask layer.
18. The method of forming a semiconductor structure of claim 17, wherein the material of the first mask layer comprises: silicon oxide, silicon nitride, titanium oxide, tungsten carbide, silicon carbonitride, silicon oxycarbide, aluminum oxide, and aluminum nitride.
19. The method for forming a semiconductor structure according to claim 17, wherein after the first opening and the second opening are formed, the first mask layer is etched using the second core layer and the sidewall spacer material layer as a mask, a first trench and a second trench are formed in the first mask layer, the first trench is exposed through the first opening, and the second trench is exposed through the second opening.
20. The method of forming a semiconductor structure of claim 19, further comprising, after forming the first trench and the second trench: and etching the substrate by taking the first mask layer as a mask, and forming a first target groove and a second target groove in the substrate, wherein the first groove exposes the first target groove, and the second groove exposes the second target groove.
21. The method of forming a semiconductor structure of claim 20, further comprising, after forming the first target trench and the second target trench: forming a first conductive layer in the first target groove; and forming a second conductive layer in the second target groove.
22. The method of forming a semiconductor structure according to claim 21, wherein a material of the first conductive layer comprises: copper, aluminum, tungsten, cobalt, tantalum nitride, titanium nitride, ruthenium nitride, and graphene.
23. The method of forming a semiconductor structure according to claim 21, wherein a material of the second conductive layer comprises: copper, aluminum, tungsten, cobalt, tantalum nitride, titanium nitride, ruthenium nitride, and graphene.
CN202110106512.6A 2021-01-26 2021-01-26 Method for forming semiconductor structure Pending CN114792624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110106512.6A CN114792624A (en) 2021-01-26 2021-01-26 Method for forming semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110106512.6A CN114792624A (en) 2021-01-26 2021-01-26 Method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
CN114792624A true CN114792624A (en) 2022-07-26

Family

ID=82459700

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110106512.6A Pending CN114792624A (en) 2021-01-26 2021-01-26 Method for forming semiconductor structure

Country Status (1)

Country Link
CN (1) CN114792624A (en)

Similar Documents

Publication Publication Date Title
KR101449772B1 (en) Efficient pitch multiplication process
JP3320794B2 (en) Method for forming a corrugated element contact capacitor
JP5311116B2 (en) Method for creating a plurality of conductive lines in an array region of an integrated circuit
WO2009017982A2 (en) Methods for device fabrication using pitch reduction and associated structures
CN111524794A (en) Semiconductor structure and forming method thereof
CN110957320A (en) Semiconductor structure, memory structure and preparation method thereof
EP3910670A1 (en) Capacitors and forming method therefor, and dram unit
CN209785930U (en) Capacitor, DRAM cell and memory
EP3267474A1 (en) Contact structure and associated method for flash memory
CN112713087B (en) Semiconductor structure and forming method thereof
US11769672B2 (en) Semiconductor structure and forming method thereof
CN111668093B (en) Semiconductor device and method of forming the same
CN111640659B (en) Semiconductor device and method of forming the same
CN112951720A (en) Forming method of semiconductor structure and semiconductor device
CN114792624A (en) Method for forming semiconductor structure
US11651964B2 (en) Semiconductor structure and forming method thereof
CN111640667B (en) Semiconductor device and method of forming the same
CN112053947B (en) Patterning method and semiconductor device formed thereby
CN114388430A (en) Method for forming semiconductor structure and mask
CN111952170B (en) Semiconductor device and method of forming the same
CN111668156B (en) Patterning method and semiconductor device formed thereby
CN113782488B (en) Semiconductor structure and forming method thereof
CN113097065B (en) Semiconductor structure and forming method thereof
CN114334817A (en) Semiconductor structure and forming method thereof
CN114551333A (en) Method for forming semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination