CN113782488B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113782488B
CN113782488B CN202010526154.XA CN202010526154A CN113782488B CN 113782488 B CN113782488 B CN 113782488B CN 202010526154 A CN202010526154 A CN 202010526154A CN 113782488 B CN113782488 B CN 113782488B
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layer
forming
core
region
filling
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CN113782488A (en
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: patterning the core material layer to form a core layer positioned in the first extension region; forming a side wall on the side wall of the core layer; ion doping is carried out on the core material layer, so that the etching resistance of the core material layer of the first interval region is larger than that of the core material layer of the first connection region; forming a filling layer filled between adjacent side walls and a first groove positioned in a second connecting region on the second interval region; removing the core layer positioned in the first connecting region after ion doping and forming the core layer, the side wall and the filling layer to form a second groove, wherein the second groove and the first groove are arranged at intervals along the second direction; and etching the dielectric layers below the first groove and the second groove by taking the filling layer, the side wall and the core layer positioned in the first interval region as masks to form a plurality of interconnection grooves. The embodiment of the invention is beneficial to improving the degree of freedom and flexibility of the graphic design of the interconnection groove.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid growth of the semiconductor integrated circuit (Integrated circuit, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in integrated circuits that are smaller, more precise, and more complex.
As integrated circuits develop, the geometry (i.e., the minimum device size that can be created using process steps) generally decreases as the functional density (i.e., the number of interconnect structures per chip) increases, which correspondingly increases the difficulty and complexity of integrated circuit fabrication.
Currently, with the continued scaling of technology nodes, how to increase the matching degree between the patterns formed on the wafer and the target patterns becomes a challenge.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to improving the degree of freedom and flexibility of pattern design of an interconnection groove.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises a first extension region and a second extension region which extend along a first direction and are arranged at intervals along a second direction, the first extension region comprises a first connection region and a first interval region which is positioned between the first connection regions along the first direction, and the second extension region comprises a second connection region and a second interval region which is positioned between the second connection regions along the first direction; forming a core material layer on the dielectric layer for forming a core layer separate from the first extension region; patterning the core material layer to form a core layer positioned in the first extension region; forming a side wall on the side wall of the core layer; ion doping is carried out on the core material layer positioned in the first interval region, so that the etching resistance of the core material layer of the first interval region is larger than that of the core material layer of the first connection region; forming a filling layer filled between adjacent side walls on the dielectric layer of the second interval region, and forming a first groove positioned in the second connection region between the adjacent filling layers along the first direction; removing the core layer positioned in the first connecting region after ion doping and forming the core layer, the side wall and the filling layer, and forming a second groove positioned in the first connecting region, wherein the second groove and the first groove are arranged at intervals along a second direction, and the second groove and the first groove are isolated by the side wall; and etching the dielectric layers below the first groove and the second groove by taking the filling layer, the side wall and the core layer positioned in the first interval region as masks to form a plurality of interconnection grooves.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; the dielectric layer is positioned on the substrate and comprises first extension regions and second extension regions which extend along a first direction and are arranged at intervals along a second direction, the first extension regions comprise first connection regions and first interval regions which are positioned between the first connection regions along the first direction, and the second extension regions comprise second connection regions and second interval regions which are positioned between the second connection regions along the first direction; the core layer is separated from the first extension region, wherein ions are doped in the core layer positioned in the first interval region, the ions are suitable for increasing the etching resistance of the core layer, or ions are doped in the core layer positioned in the first connection region, and the ions are suitable for reducing the etching resistance of the core layer; the side wall is positioned on the side wall of the core layer; the filling layer is positioned on the dielectric layer of the second interval region and is filled between the adjacent side walls, and the filling layer, the side walls and the core layer of the first interval region are used as masks for etching the dielectric layer to form interconnection grooves; and the first groove is positioned in the second connection region and positioned between the adjacent filling layers along the first direction.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the core material layer positioned in the first interval region is subjected to ion doping, so that the etching resistance of the core material layer of the first interval region is higher than that of the core material layer of the first connection region, and therefore, in the process of subsequently removing the core layer of the first connection region to form the second groove, the core layer of the first connection region and the core layer of the first interval region have a larger etching selection ratio, and the core layer of the first interval region can be reserved to serve as a mask for etching the dielectric layer; furthermore, a filling layer positioned in the second interval region and a first groove positioned in the first connection region are also formed; the process of ion doping comprises forming a first mask layer, wherein the first mask layer is used as an ion doping mask, the first mask layer correspondingly defines a pattern of a second groove, and the process of forming a filling layer comprises forming a second mask layer positioned in a second connection region, and the second mask layer correspondingly defines a pattern of the first groove; in the embodiment of the invention, in different steps, the first mask layer is used for defining the pattern of the second groove, the second mask layer is used for defining the pattern of the first groove, the first extension region and the second extension region are arranged at intervals along the second direction, so that the mutual influence of the ion doping step and the filling layer forming step is prevented, that is, the influence of the first mask layer on the pattern of the first groove and the influence of the second mask layer on the pattern of the second groove are prevented, the pattern complexity and the design freedom degree and the flexibility of the first mask layer and the second mask layer are correspondingly reduced, the first mask layer and the second mask layer are formed through a photoetching process, the difficulty of the photoetching process for forming the first mask layer and the second mask layer is reduced, the process window of the photoetching process is increased (for example, the optical proximity effect is reduced), the pattern precision, the pattern design freedom degree and the flexibility of the first groove and the second groove are further improved, the interval of the first groove and the second groove along the second direction can meet the minimum design interval, the pattern definition of the first groove and the second groove and the flexibility of the second groove are correspondingly reduced, and the interconnection distance between the interconnection heads and the interconnection heads is further improved, and the interconnection distance between the interconnection heads is reduced.
In addition, the filling layer, the side wall and the core layer located in the first spacer are used as masks for etching the dielectric layer to form the interconnection trench, that is, the filling layer, the side wall and the pattern of the interconnection trench required by the core layer located in the first spacer are defined, so that the process of forming the pseudo interconnection trench is omitted, and the interconnection line is formed in the interconnection trench subsequently.
Drawings
Fig. 1 to 10 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIGS. 11 through 39 are schematic views illustrating steps corresponding to the steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 40 to 47 are schematic views of steps corresponding to the method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
The current patterning method of the back-end interconnection structure is complex, and has larger process difficulty and smaller process window. The reason why the patterning method for forming the back-end interconnection structure is complicated is analyzed by combining a semiconductor structure forming method.
Referring to fig. 1 to 10, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1 and 2, fig. 1 is a top view, fig. 2 is a cross-sectional view of fig. 1 at a-a, providing a substrate 1; forming a dielectric layer 2 on the substrate 1; forming a discrete core layer 3 on the dielectric layer 2; a sidewall structure 4 is formed surrounding the sidewalls of the core layer 3.
Referring to fig. 3 and 4, fig. 3 is a top view, fig. 4 is a cross-sectional view of fig. 3 at a-a, the core layer 3 is removed, the sidewall structure 4 encloses a trench 5 extending along a first direction (as shown in a Y direction in fig. 3), and a plurality of the trenches 5 are sequentially arranged along a second direction (as shown in an X direction in fig. 3).
Referring to fig. 5 and 6, fig. 5 is a top view, and fig. 6 is a cross-sectional view of fig. 5 at a-a, a mask layer 6 covering a portion of the sidewall structure 4 is formed on the dielectric layer 2, a mask opening 7 is formed in the mask layer 6, and a portion of the trench 5 and a portion of the dielectric layer 2 between the sidewall structures 4 are exposed along the second direction.
Referring to fig. 7 and 8, fig. 7 is a top view, fig. 8 is a cross-sectional view of fig. 7 at a-a, and the mask opening 7 and the dielectric layer 2 exposed by the sidewall structure 4 are etched with the mask layer 6 and the sidewall structure 4 as masks, so as to form an opening 8 penetrating the dielectric layer 2.
Referring to fig. 9 and 10, fig. 9 is a top view, and fig. 10 is a cross-sectional view of fig. 9 at a-a, forming an interconnect line 9 in the opening 8.
In the above-mentioned forming method, the openings 8 are formed by using the sidewall structures 4 and the mask layer 6 together as a mask for etching the dielectric layer 2, that is, the patterns of the interconnection Lines 9 are defined by using the sidewall structures 4 and the mask layer 6 together, and no Dummy interconnection Lines (Dummy Lines) are formed, and no step of removing the Dummy interconnection Lines is required.
However, in the above method, the pattern of the mask layer 6 is complex, and the mask layer 6 is generally formed by a photolithography process, for example: forming the mask layer 6 includes a process of performing optical proximity correction, the pattern of the mask layer 6 is complex, resulting in a great difficulty in optical proximity correction, which easily results in that the pattern of the formed mask layer 6 is inconsistent with the pattern required by the design, and thus, the pattern of the interconnection line 9 is difficult to meet the design requirement, and the pattern quality and pattern precision of the interconnection line 9 are poor, even easily resulting in a problem of shorting (Bridge) of the interconnection line 9 at a position where connection is not required.
In order to solve the above-mentioned problems, another patterning method of the back-end interconnection structure is proposed. The method is the same as the previous method and is not described in detail herein, except that: after forming a side wall on the side wall of a core layer and removing the core layer, etching the dielectric layer by taking the side wall as a mask, and forming a plurality of interconnection grooves which extend along a first direction and are sequentially arranged along a second direction in the dielectric layer; forming a blocking structure filling a portion of the interconnect trench along the second direction; and forming interconnection lines in the interconnection grooves exposed by the blocking structures, wherein the interconnection lines positioned at two sides of the blocking structures along the first direction are isolated by the blocking structures.
In the above method, the interconnect line is disconnected at a position where connection is not required by forming the blocking structure. The method does not need to form a mask with complex patterns, and is beneficial to reducing the process difficulty. However, in the above-mentioned forming method, a plurality of floating interconnect lines are formed, that is, these interconnect lines are not electrically connected to an external circuit or other interconnect structures, and when the device is in operation, these floating interconnect lines tend to increase parasitic capacitance of the back-end interconnect, resulting in poor performance of the formed semiconductor structure.
Or, after the core layer is removed, before the dielectric layer is etched by using the side wall as a mask to form an interconnection trench, a blocking structure filled between adjacent side walls of the filling part along the second direction is formed, and the blocking structure and the side wall are jointly used as a mask of the patterned dielectric layer. In this formation method, after the interconnection line is formed, the interconnection line can also be disconnected at a position corresponding to the blocking structure in the dielectric layer. However, this approach still does not address the problem of excessive parasitic capacitance of the back-end interconnect.
Therefore, a method is needed to increase the process window of the back-end interconnect patterning, and to improve the problem of the parasitic capacitance of the back-end interconnect being too high.
In order to solve the technical problem, in the method for forming a semiconductor structure provided by the embodiment of the invention, in different steps, the first mask layer is used for defining the pattern of the second groove, the second mask layer is used for defining the pattern of the first groove, the first extension region and the second extension region are arranged at intervals along the second direction, so that the step of ion doping and the step of filling layer formation are prevented from being influenced by each other, that is, the first mask layer is prevented from influencing the pattern of the first groove, the second mask layer is prevented from influencing the pattern of the second groove, the complexity of the pattern of the first mask layer and the second mask layer, the degree of freedom and the degree of flexibility of design are correspondingly reduced, the first mask layer and the second mask layer are formed through a photoetching process, the difficulty of the photoetching process for forming the first mask layer and the second mask layer is reduced, the process window of the photoetching process is increased (for example, the optical proximity effect is reduced), the pattern precision, the degree of freedom and the flexibility of pattern design of the first groove and the second groove are further improved, the first groove and the second groove can meet the minimum design interval along the second direction, the first groove and the interconnection distance between the first groove and the second groove can be more flexibly designed, and the interconnection distance between the first groove and the second groove and the interconnection distance between the two grooves can be further improved, and the interconnection distance between the two grooves can be more flexibly designed at the positions can be realized. In addition, the filling layer, the side wall and the core layer located in the first interval region are used as masks for etching the dielectric layer to form the interconnection grooves, that is, the filling layer, the side wall and the pattern of the interconnection grooves required by the core layer located in the first interval region are defined, so that the process of forming the pseudo interconnection grooves is omitted, interconnection lines are formed in the interconnection grooves subsequently, and accordingly the formation of floating interconnection lines is avoided, parasitic capacitance between the rear-section interconnection structures is reduced, and performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 11 to 39 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 11 and 12, fig. 11 is a top view, and fig. 12 is a cross-sectional view of fig. 11 at c-c, providing a substrate 100.
The substrate 100 is used to provide a process platform for a process recipe.
In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate 100, and a functional structure such as a resistor structure or a conductive structure may be formed in the substrate 100.
With continued reference to fig. 11 and 12, a dielectric layer 110 is formed on the substrate 100, the dielectric layer 110 including first extension regions I and second extension regions II extending in a first direction (as shown in an X direction in fig. 11) and spaced apart in a second direction (as shown in a Y direction in fig. 11), the first extension regions I including first connection regions a1 and first spacing regions b1 located between the first connection regions a1 in the first direction, and the second extension regions II including second connection regions a2 and second spacing regions b2 located between the second connection regions a2 in the first direction. The subsequently formed interconnect trench extends in a first direction.
In this embodiment, the dielectric layer 110 is an inter-metal dielectric (Inter Metal Dielectric, IMD) layer. The dielectric layer 110 is a film layer to be patterned to form a target pattern. The dielectric layer 110 is subsequently patterned, a plurality of interconnect trenches are formed in the dielectric layer 110,
an interconnect line is then formed in the interconnect trench, and dielectric layer 110 is used to effect electrical isolation between the interconnect lines.
The dielectric layer 110 has a single-layer or stacked-layer structure. The material of the dielectric layer 110 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc. In this embodiment, the material of the dielectric layer 110 is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end metal interconnection structures, and further reduce the back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.
Referring to fig. 13 and 14, fig. 13 is a top view, and fig. 14 is a cross-sectional view of fig. 13 at c-c, a core material layer 120 is formed on the dielectric layer 110 for forming a core layer separate from the first extension region I.
The core material layer 120 is subsequently patterned to form a core layer that provides support for the subsequent sidewall formation. The material of the core material layer 120 includes amorphous silicon, polysilicon, silicon oxide, or silicon nitride.
In this embodiment, before forming the core material layer 120, the method for forming a semiconductor structure further includes: an etch stop layer 115 is formed on dielectric layer 110.
The patterning of the core material layer 120 and the subsequent formation of the sidewall, the first recess, and the second recess each include an etching process, and the etch stop layer 115 is used to define the location of the etch stop in the etching process.
The etching stop layer 115 has a single-layer or stacked-layer structure. As an example, in this embodiment, the etching stop layer 115 has a single-layer structure, and the material of the etching stop layer 115 is silicon nitride.
Referring to fig. 15 to 20, the core material layer 120 located in the first separation region b1 is ion-doped, and it is suitable to make the etching resistance of the core material layer 120 of the first separation region b1 greater than that of the core material layer 120 of the first connection region a 1.
Specifically, in this embodiment, the step of performing ion doping includes: the ion doping is performed on the core material layer 120 located in the first spacer region b1, which is suitable for increasing the etching resistance of the core material layer 120 of the first spacer region b 1.
In this embodiment, ion doping is performed before patterning the core material layer 120; after the subsequent patterning of the core material layer 120 to form a core layer, accordingly, the core layer located in the first spacer region b1 has a higher etching resistance than the core layer of the first connection region a 1.
In the embodiment of the present invention, the core material layer 120 located in the first spacer region b1 is ion doped, so that the etching resistance of the core material layer 120 in the first spacer region b1 is greater than that of the core material layer 120 in the first connection region a1, and thus, in the process of subsequently removing the core layer in the first connection region a1 to form the second recess, the core layer in the first connection region a1 and the core layer in the first spacer region b1 have a greater etching selection ratio, so that the core layer in the first spacer region b1 can be reserved for being used as a mask for etching the dielectric layer 110; further forming a filling layer positioned in the second interval region and a first groove positioned in the first connection region, wherein the first groove and the second groove are used for defining a pattern of the interconnection groove; the process of ion doping comprises forming a first mask layer used as an ion doping mask, wherein the first mask layer correspondingly defines a pattern of a second groove, and the process of forming a filling layer comprises forming a second mask layer positioned in a second connection region, and the second mask layer correspondingly defines a pattern of the first groove; in the embodiment of the invention, in different steps, the first mask layer is used for defining the pattern of the second groove, the second mask layer is used for defining the pattern of the first groove, so that the step of ion doping and the step of forming the filling layer are prevented from being influenced mutually, that is, the first mask layer is prevented from influencing the pattern of the first groove, the second mask layer is prevented from influencing the pattern of the second groove, the complexity of the pattern of the first mask layer and the second mask layer and the design freedom degree and flexibility degree of the second mask layer are correspondingly reduced, the first mask layer and the second mask layer are formed through photoetching, the difficulty of the photoetching process for forming the first mask layer and the second mask layer is reduced, the process window of the photoetching process is increased (for example, the optical proximity effect is reduced), the pattern precision, the pattern design freedom degree and the flexibility degree of the first groove and the second groove are further improved, the interval between the first groove and the second groove along the second direction can meet the minimum designed interval, the pattern of the first groove and the second groove is used for defining the pattern of the interconnection groove, and therefore the interconnection flexibility degree of the interconnection groove is improved, and the interconnection distance between the first groove and the interconnection distance between the Tip and the Tip are further reduced.
Specifically, during the ion doping process, even if the first mask layer is still located in the second extension region II, the pattern of the first groove will not be affected.
As an example, after forming the core material layer 120 and before patterning the core material layer 120, the core material layer 120 is ion doped.
Specifically, in the present embodiment, the core material layer 120 located in the first spacer b1 is ion doped, which is suitable for increasing the etching resistance of the core material layer 120 in the first spacer b1, and the doped ions include one or more of boron ions, phosphorus ions, and argon ions.
In other embodiments, the core material layer located in the first connection region may be further ion doped, which is adapted to reduce the etching resistance of the core material layer in the first connection region. Accordingly, in this embodiment, an appropriate implantation ion may be selected so as to be able to function to reduce the etching resistance of the core material layer.
As an example, the step of ion doping includes:
as shown in fig. 15 and 16, fig. 15 is a top view, and fig. 16 is a cross-sectional view of fig. 15 at c-c, a first mask layer 121 is formed on the dielectric layer 110 at the first extension region I and the second extension region II.
The first mask layer 121 is used as a mask for ion doping to be performed later.
In this embodiment, the following ion doping step includes: the ion doping is performed on the core material layer 120 located in the first spacer region b1, which is suitable for increasing the etching resistance of the core material layer 120 of the first spacer region b1. Therefore, the first mask layer 121 covers the first connection region a1 and exposes the first spacer region b1.
Since the core material layer 120 is patterned and then the core material layer 120 is located in the first extension region I, that is, the second extension region II, the core material layer 120 is removed, and therefore, although the first mask layer 121 is still located in the second extension region II, the first mask layer 121 and the subsequent ion doping process will not affect the pattern of the first recess, which is beneficial to reducing the difficulty of the photolithography process for forming the first mask layer 121, further to increasing the window of the photolithography process, and to precisely controlling the ion doped region, and accordingly to improving the pattern precision of the subsequent second recess.
In this embodiment, the material of the first mask layer 121 includes Spin-On Carbon (SOC).
In this embodiment, the step of forming the first mask layer 121 includes: forming a first planarization layer (not shown) on the dielectric layer 110, and a first pattern layer on the first planarization layer; and patterning the first flat layer by taking the first pattern layer as a mask to form a first mask layer.
The first pattern layer is used to define the pattern of the first mask layer 121. The material of the first pattern layer includes photoresist, and the first pattern layer can be formed by a photolithography process such as exposure, development, and the like.
As shown in fig. 17 and 18, fig. 17 is a top view, and fig. 18 is a cross-sectional view of fig. 17 at c-c, wherein the first mask layer 121 is used as a mask to ion dope the core material layer 120 exposed by the first mask layer 121. Specifically, in the present embodiment, the core material layer 120 of the first spacer b1 is ion doped.
In this embodiment, ion implantation is used to perform ion doping.
In this embodiment, in the process of performing ion doping, the core material layer 120 of the second extension region II exposed by the first mask layer 121 is further subjected to ion doping, and since only the core material layer 120 located in the first extension region I remains in the process of patterning the core material layer 120 subsequently, even if ions are doped in the core material layer 120 of the second extension region II, the influence on the subsequent process is small.
As shown in fig. 19 and 20, fig. 19 is a top view, fig. 20 is a cross-sectional view of fig. 19 at c-c, and the first mask layer 121 is removed. The first mask layer 121 is removed in preparation for subsequent processing.
In this embodiment, one or both of an ashing process and a wet photoresist removing process is used to remove the first mask layer 121.
Referring to fig. 21 and 22, fig. 21 is a top view, fig. 22 is a cross-sectional view of fig. 21 at c-c, and the core material layer 120 is patterned to form a core layer 130 at the first extension region I.
The core layer 130 is used to provide support for the subsequent formation of the sidewall.
In this embodiment, before patterning the core material layer 120, ion doping is performed on the core material layer 120 located in the first spacer region b1, so that ions are doped in the core layer 130 located in the first spacer region b1 in the step of patterning the core material layer 120, which is suitable for increasing the etching resistance of the core layer 130 in the first spacer region b 1. Accordingly, the core layer 130 located at the first spacer b1 has a higher etching resistance than the core layer 130 located at the first connection region a1, so that the core layer 130 of the first connection region a1 and the core layer 130 of the first spacer b1 have a higher etching selectivity in the subsequent step of removing the core layer 130 located at the first connection region a1, so that the core layer 130 of the first spacer b1 can be preserved as a mask for etching the dielectric layer 110.
In this embodiment, the core layer 130 doped with ions in the first isolation region b1 serves as the etching resist layer 31, and the core layer 130 undoped with ions in the first connection region a1 serves as the sacrificial layer 32.
The sacrificial layer 32 is used to occupy a spatial position for the subsequent formation of a second recess.
The resist layer 31 is used as a mask for the subsequent patterned dielectric layer 110.
In this embodiment, the core material layer 120 is patterned using a dry etching process.
Referring to fig. 23 and 24, fig. 23 is a top view, and fig. 24 is a cross-sectional view of fig. 23 at c-c, forming sidewalls 140 on the sidewalls of the core layer 130.
The sidewall 140 on the sidewall of the core layer 130 is used as an Outer sidewall (Outer Spacer) and is used as a mask for the subsequent patterned dielectric layer 110, and the sidewall 140 on the sidewall of the core layer 130 is also used to isolate the core layer 130 from the subsequent filling layer, so that after the core layer 130 of the first connection region a1 is removed to form the second groove and the filling layer is removed to form the first groove, the first groove and the second groove can be isolated by the sidewall 140, therefore, by adjusting the forming thickness of the sidewall 140, the embodiment is beneficial to enabling the first groove and the second groove to meet the minimum design interval, and correspondingly beneficial to enabling the interconnection grooves to meet the minimum design interval.
The sidewall 140 is made of a material having etching selectivity to the core layer 130, the dielectric layer 110 and the subsequent filling layer, and the material of the sidewall 140 includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon.
In this embodiment, in the step of forming the sidewall 140, the sidewall 140 is formed on the top surface and the sidewall of the core layer 130 and the dielectric layer 110 between the core layers 130.
In this embodiment, the process of forming the sidewall 140 includes an atomic layer deposition process. The atomic layer deposition process comprises multiple atomic layer deposition cycles to form a film with a required thickness, and the atomic layer deposition process is selected to be beneficial to improving the thickness uniformity and the density of the etched side wall 140, correspondingly beneficial to improving the hardness and the etching resistance of the side wall 140, and further improving the effect of the side wall 140 serving as an etching mask.
The core layer 130 located in the first connection region a1 is also removed later, so the method for forming a semiconductor structure further includes: after forming the sidewall 140, and before removing the core layer 130 (i.e., the sacrificial layer 32) located at the first connection region a1, the sidewall 140 located on the top surface of the core layer 130 is removed, thereby exposing the top surface of the core layer 130. The top surface of core layer 130 is exposed in preparation for subsequent removal of sacrificial layer 32.
Referring to fig. 25 to 33, a filling layer 150 filled between adjacent sidewalls 140 is formed on the dielectric layer 110 of the second spacer region b2, and a first groove 10 located in the second connection region a2 is formed between adjacent filling layers 150 in the first direction. The fill layer 150 is used as a mask for the subsequent patterned dielectric layer 110.
The dielectric layer 110 under the first recess 10 is subsequently patterned to form an interconnect trench.
In the embodiment of the invention, in the process of forming the filling layer 150, the second mask layer 141 for defining the patterns of the filling layer 150 and the first groove 10 is also required to be formed, since the filling layer 150 and the first groove 10 are located between the adjacent side walls 140 of the second spacer b2, even if the second mask layer 141 is still located in the first extension region I, the patterns of the etching layer 31 and the sacrificial layer 32 are not affected, which is beneficial to preventing the patterns of the second groove from being affected, correspondingly, the second mask layer 141 can cross the first extension region I and the second extension region II along the second direction, which is beneficial to reducing the pattern complexity of the second mask layer 141, and the second mask layer 141 is formed by a photolithography process, which is beneficial to reducing the difficulty of the photolithography process for forming the second mask layer 141, increasing the process window of the photolithography process (for example, reducing the optical proximity effect), further improving the pattern design freedom and flexibility of the interconnection trenches, and realizing smaller spacing between the interconnection trenches and smaller distance at the position of the head-to-head (top).
The material of the fill layer 150 includes silicon oxide, metal oxide, or silicon-containing organic (e.g., si-ARC), etc. Wherein the silicon oxide comprises Spin-On-Glass (SOG); the Metal Oxide includes Spin-On Metal Oxide (Spin-On Metal Oxide), such as: titanium oxide. The material of the filling layer 150 is suitable for a spin coating process, which is beneficial to reducing the difficulty of forming the filling layer 150. As an example, the filling layer 150 covers the sidewall 140 on the top surface of the dielectric layer 110 of the second spacer b 2.
As an example, the step of forming the filling layer 150 and the first groove 10 includes:
as shown in fig. 25 and 26, fig. 25 is a top view, fig. 26 is a cross-sectional view of fig. 25 at a c-c position, and a second mask layer 141 is formed on the dielectric layer 110 of the second connection region a2 to fill between the adjacent side walls 140, wherein the second mask layer 141 exposes the dielectric layer 110 located in the second spacer region b 2.
The second mask layer 141 is used for occupying a space position for forming the first groove, and the second mask layer 141 correspondingly defines a pattern and a position of the filling layer, that is, the subsequent filling layer is filled between the sidewalls of the sidewall 140 exposed by the second mask layer 141. In this embodiment, the material of the second mask layer 141 includes spin-on carbon (SOC).
In this embodiment, the step of forming the second mask layer 141 includes: forming a second planarization layer (not shown) covering the sidewall 140 and the core layer 130 and a second pattern layer (not shown) on the second planarization layer on the dielectric layer 110; and patterning the second flat layer by using the second pattern layer as a mask.
In this embodiment, the second pattern layer is used to define the pattern of the second mask layer 141.
In this embodiment, the material of the second pattern layer includes photoresist, and the second pattern layer can be formed by a photolithography process such as exposure, development, and the like.
As shown in fig. 27, a filling material layer 145 filled between the sidewalls of the sidewalls 140 exposed by the second mask layer 141 is formed on the dielectric layer 110, and the filling material layer 145 also covers the sidewalls 140, the core layer 130 and the second mask layer 141. The filling material layer 145 is used to form a filling layer through a subsequent etching process. The process of forming the filler material layer 145 includes one or more of an atomic layer deposition process, a chemical vapor deposition process, and a spin-on process. As an example, the filler material layer 145 is formed using a spin-coating process. The spin coating process is simple to operate and low in process cost.
As shown in fig. 28 and 29, fig. 28 is a top view, fig. 29 is a cross-sectional view of fig. 28 at the c-c position, the filling material layer 145 higher than the top surface of the core layer 130 is removed, and the remaining filling material layer 145 located at the second spacer b2 is used as the filling layer 150. In this embodiment, a dry etching process is used to remove the filler material layer 145 above the top surface of the core layer 130.
As shown in fig. 30 and 31, the second mask layer 141 is removed to form the first recess 10.
The second mask layer 141 is removed using one or both of an ashing process and a wet photoresist removing process.
Referring to fig. 32 and 33 in combination, fig. 32 is a top view, and fig. 33 is a cross-sectional view of fig. 32 at position c-c, in this embodiment, after forming the filling layer 150 and before removing the core layer 130 at the first connection region a1, the sidewall 140 on the top surface of the core layer 130 is removed.
The sidewall 140 on the top surface of the core layer 130 is removed, thereby exposing the top surface of the core layer 130, i.e., the top surface of the core layer 130 (the resist layer 31 and the sacrificial layer 32), in preparation for the subsequent removal of the core layer 130 (i.e., the sacrificial layer 32) of the first connection region a 1.
In this embodiment, in the step of removing the sidewall 140 on the top surface of the core layer 130, the sidewall 140 on the top surface of the dielectric layer 110 of the second connection region a2 is also removed.
In this embodiment, the process of removing the sidewall 140 on the top surface of the core layer 130 includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, and can remove the side wall 140 on the top surface of the core layer 130 and the top surface of the dielectric layer 110 of the second connection region a2 in a maskless environment, and simultaneously has a smaller lateral etching amount on the side wall 140 exposed from the side wall of the first groove 10, which is correspondingly beneficial to ensuring the effect of the side wall 140 serving as an etching mask for etching the dielectric layer 110.
In other embodiments, the sidewall on the top surface of the core layer can also be removed after forming the sidewall and before forming the filler layer; the method for forming the semiconductor structure further comprises the following steps: and removing the side wall on the dielectric layer between the core layers in the step of removing the side wall on the top surface of the core layers. Accordingly, in this embodiment, in the step of forming the filling layer, the filling layer covers the top surface of the dielectric layer of the second spacer.
Referring to fig. 34 and 35, fig. 34 is a top view, and fig. 35 is a cross-sectional view of fig. 34 at the cc position, after ion doping is performed and the core layer 130, the sidewall 140, and the filling layer 150 are formed, the core layer 130 (i.e., the sacrificial layer 32) located at the first connection region a1 is removed, the second grooves 20 located at the first connection region a1 are formed, the second grooves 20 and the first grooves 10 are spaced apart in the second direction, and the second grooves 20 and the first grooves 10 are separated by the sidewall 140.
In the embodiment of the invention, in different steps, the first mask layer 121 is used to define the pattern of the second groove 20, and the second mask layer 141 is used to define the pattern of the first groove 10; in the process of ion doping, even if the first mask layer 121 is still located in the second extension region II, the pattern of the first groove 10 is not affected, in the process of forming the filling layer 150, even if the second mask layer 141 is still located in the first extension region I, the pattern of the second groove 20 is not affected, so that the ion doping and the filling layer 150 forming are prevented from being affected, accordingly, the first mask layer 121 and the second mask layer 141 can both cross the first extension region I and the second extension region II along the second direction, the pattern complexity of the first mask layer 121 and the second mask layer 141 is reduced, the first mask layer 121 and the second mask layer 141 are formed through a photolithography process, the difficulty of the photolithography process for forming the first mask layer 121 and the second mask layer 141 is reduced, the process window of the photolithography process is increased (for example, the optical proximity effect is reduced), the pattern precision of the first groove 10 and the second groove 20 is further improved, the pattern design freedom and flexibility of the interconnection groove are correspondingly improved, and the distance between the interconnection grooves to the Tip is reduced, and the Tip distance between the interconnection grooves is reduced.
In addition, in the embodiment of the present invention, by forming the etching resist layer 31 on the first spacer b1 and forming the filling layer 150 on the second spacer b2, the etching resist layer 150, the filling layer 150 and the side wall 140 are used as masks for etching the dielectric layer 110 to form the interconnection trench, that is, the etching resist layer 31, the filling layer 150 and the side wall 140 define the pattern of the required interconnection trench, so that the embodiment of the present invention avoids forming the dummy interconnection trench, and the interconnection trench provides a spatial position for forming the interconnection line, and accordingly, the embodiment of the present invention avoids forming the Floating interconnection line, thereby being beneficial to reducing the parasitic capacitance between the interconnection structures at the back stage, and further being beneficial to improving the performance of the semiconductor structure.
The process of removing the core layer 130 (i.e., the sacrificial layer 32) located at the first connection region a1 includes one or both of wet etching and dry etching. As an example, the material of the sacrificial layer 32 includes amorphous silicon, and a wet etching process is used to remove the sacrificial layer 32. In the present embodimentThe etching solution of the wet etching process includes TMAH solution (tetramethylammonium hydroxide solution), SC1 solution or SC2 solution. Wherein the SC1 solution is NH 4 OH and H 2 O 2 The SC2 solution is HCl and H 2 O 2 Is a mixed solution of (a) and (b).
Referring to fig. 36 and 37, fig. 36 is a top view, and fig. 37 is a cross-sectional view of fig. 36 at position c-c, and the dielectric layer 110 under the first recess 10 and the second recess 20 is etched to form a plurality of interconnection trenches 30 using the filling layer 150, the sidewall 140, and the core layer 130 (i.e., the etch-resistant layer 31) located in the first spacer b1 as masks. The interconnect trenches 30 are used to provide spatial locations for forming interconnect lines.
As can be seen from the foregoing, the distances between the adjacent first grooves 10 and between the adjacent second grooves 20 are smaller in the first direction, and the first grooves 10 and the second grooves 20 have smaller distances at the head-to-head positions, so that the adjacent interconnection grooves 30 can achieve smaller distances at the head-to-head positions, thereby being beneficial to improving the flexibility and the degree of freedom of layout design of the interconnection grooves 30.
In addition, in the present embodiment, by forming the core layer 120 and the first sidewall 130 located on the sidewall of the core layer 120, and then forming the sacrificial layer 140, it is beneficial to make the space between the sacrificial layer 140 and the core layer 120 meet the design minimum interval, and correspondingly make the space between the second groove 20 and the first groove 10 along the second direction meet the design minimum interval, and further make the space between the interconnection grooves 30 meet the design minimum interval.
In addition, the present embodiment is advantageous in improving the pattern precision of the first groove 10 and the second groove 20, and correspondingly, in providing the interconnection trench 30 with higher pattern precision.
Specifically, the filling layer 150, the side wall 140 and the etching-resistant layer 31 are used as masks to etch the etching stop layer 115 and the dielectric layer 110 under the first recess 10 and the second recess 20, and a plurality of interconnection trenches 30 are formed in the dielectric layer 110.
In this embodiment, a dry etching process is used, for example: an anisotropic dry etching process etches the etch stop layer 115 and the dielectric layer 110 under the first recess 10 and the second recess 20. The anisotropic dry etching process has the characteristic of anisotropic etching, and is beneficial to improving the accuracy of pattern transfer.
Referring to fig. 38 and 39 in combination, fig. 38 is a top view, fig. 39 is a cross-sectional view at c-c in fig. 38, and after forming the plurality of interconnect trenches 30, the method of forming the semiconductor structure further includes: an interconnect line 160 is formed in the interconnect trench 30.
The interconnect trench 30 formed in this embodiment can achieve a smaller distance at the head-to-head position, and accordingly, the interconnect line 180 can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the wiring capability of the interconnect line 160 at the head-to-head position and also beneficial to improving the degree of freedom and flexibility of the layout design of the interconnect line 160.
Moreover, the pitch of the adjacent interconnect trenches 30 in the second direction is easy to satisfy the design minimum pitch, and the pattern accuracy of the interconnect trenches 30 is high, which is advantageous for the pitch of the interconnect lines 160 in the second direction to satisfy the design minimum pitch, and for the pattern accuracy of the interconnect lines 160 to be improved.
Interconnect lines 160 are used to make electrical connection of the semiconductor structure to external circuitry or other interconnect structures.
In this embodiment, the material of the interconnection line 160 is copper. In other embodiments, the interconnect material can also be a conductive material such as cobalt, tungsten, aluminum, etc.
In this embodiment, after forming the interconnection trench 30 and before forming the interconnection line 160, the method for forming the semiconductor structure further includes: the fill layer 150, sidewall 140, etch-resistant layer 31, and etch stop layer 115 are removed. The filling layer 150, the side wall 140, the anti-etching layer 31 and the etching stop layer 115 are removed, so that the interconnection line 160 can be formed only in the interconnection trench 30, the interconnection line 160 is prevented from being formed in the first groove 10 and the second groove 20 above the interconnection trench 30, the filling depth of the interconnection line 160 is reduced, the forming difficulty of the interconnection line 160 is reduced, and the filling quality of the interconnection line 160 in the interconnection trench 30 is improved.
The process of removing the filling layer 150, the sidewall 140, the etch-resistant layer 31, and the etch stop layer 115 includes one or both of wet etching and dry etching.
Accordingly, in the present embodiment, the step of forming the interconnection line 180 includes: forming a conductive layer (not shown) filling the interconnect trench 60 on the dielectric layer 110; the conductive layer above the top surface of dielectric layer 110 is removed and the remaining conductive layer in interconnect trench 30 serves as interconnect line 160.
In this embodiment, the process of forming the conductive layer includes one or more of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an electrochemical plating process. In this embodiment, a chemical mechanical polishing process is used to remove the conductive layer above the top surface of the dielectric layer 110.
Fig. 40 to 47 are schematic views of steps corresponding to the method for forming a semiconductor structure according to another embodiment of the present invention. The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that:
after patterning the core material layer and before removing the core layer located in the first connection region, ion doping is performed on the patterned core material layer. Specifically, ion doping is performed after patterning the core material layer and before forming the sidewall.
The steps of patterning the core material layer and performing ion doping in this embodiment will be described in detail with reference to the accompanying drawings.
Referring to fig. 40 and 41, fig. 40 is a top view, fig. 41 is a cross-sectional view of fig. 40 at the c-c position, and the core material layer is patterned to form a core layer 230 at the first extension region I.
The process steps of patterning the core material layer are the same as those of the previous embodiments, and will not be repeated here.
Referring to fig. 42 to 47, the core material layer is ion doped to make the etching resistance of the core material layer of the first spacer region greater than that of the core material layer of the first connection region.
As an example, ion doping of the core material layer located in the first spacer region is adapted to increase the etch resistance of the core material layer.
In this embodiment, after patterning the core material layer and before removing the core layer 230 of the first connection region, ion doping is performed on the patterned core material layer located in the first spacer region. Specifically, ion doping is performed after patterning the core material layer and before forming the sidewall.
Therefore, in this embodiment, the core layer 230 located in the first spacer is ion doped, where the core material layer refers to the patterned core material layer, i.e. refers to the core layer 230.. Accordingly, after ion doping is performed on the core layer 230 located in the first spacer, a portion of the core layer 230 located in the first spacer is used as the etching resist layer 231, and a portion of the core layer 230 located in the first connection region is used as the sacrificial layer 232, that is, the core layer 230 includes the etching resist layer 231 located in the first spacer and the sacrificial layer 232 located in the first connection region.
In this embodiment, the step of performing ion doping includes:
as shown in fig. 42 and 43, fig. 42 is a top view, fig. 43 is a cross-sectional view of fig. 42 at a c-c position, and a first mask layer 221 is formed on the dielectric layer 210 at the first extension region I and the second extension region II.
As an example, the subsequent ion doping of the core material layer located in the first spacer is adapted to increase the etch resistance of the core material layer. Accordingly, the first mask layer 221 covers the first connection region and exposes the first spacer region.
For a specific description of the first mask layer 221, reference may be made to the corresponding description in the foregoing embodiment, and a detailed description is omitted herein.
As shown in fig. 44 and 45, fig. 44 is a top view, and fig. 45 is a cross-sectional view of fig. 44 at the c-c position, wherein the first mask layer 221 is used as a mask to ion dope the core material layer exposed by the first mask layer 221.
In this embodiment, the core material layer located in the first spacer region is ion doped, which is suitable for increasing the etching resistance of the core material layer. Specifically, the core layer 230 located in the first spacer is ion-doped.
For a specific description of ion doping, reference is made to the corresponding description in the foregoing embodiments, and no further description is given here.
As shown in fig. 46 and 47, fig. 46 is a top view, and fig. 47 is a cross-sectional view of fig. 46 at a c-c position, with the first mask layer 221 removed.
The process of removing the first mask layer 221 is the same as that of the previous embodiment, and will not be described again.
It should be noted that, in other embodiments, ion doping may also be performed after forming the sidewall and before forming the filling layer; or after forming the side wall and before forming the filling layer, carrying out ion doping; alternatively, ion doping is performed after the filling layer is formed and before the core layer located in the first connection region is removed.
The subsequent steps are the same as those of the previous embodiment, and the present embodiment is not described herein.
For a specific description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and this embodiment will not be repeated here.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 32 and 33, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown. Wherein fig. 32 is a top view and fig. 33 is a cross-sectional view of fig. 32 at position c-c.
The semiconductor structure includes: a substrate 100; the dielectric layer 110 on the substrate 100, the dielectric layer 110 including first extension regions I (shown in fig. 13) and second extension regions II (shown in fig. 13) extending in a first direction and arranged at intervals in a second direction, the first extension regions I including first connection regions a1 (shown in fig. 13) and first spacing regions b1 (shown in fig. 13) located between the first connection regions in the first direction, the second extension regions II including second connection regions a2 (shown in fig. 13) and second spacing regions b2 (shown in fig. 13) located between the second connection regions a2 in the first direction; the core layer 130 is separated from the first extension region I, wherein ions are doped in the core layer 130 located in the first separation region b1, the ions are suitable for increasing the etching resistance of the core layer 130, or ions are doped in the core layer 130 located in the first connection region a1, and the ions are suitable for reducing the etching resistance of the core layer 130; a sidewall 140 on the sidewall of the core layer 130; the filling layer 150 is located on the dielectric layer 110 of the second spacer b2 and filled between the adjacent side walls 140, and the filling layer 150, the side walls 140 and the core layer 130 of the first spacer b1 are used as masks for etching the dielectric layer 110 to form interconnection trenches; the first grooves 10 are located in the second connection region a2 and located between the adjacent filling layers 150 in the first direction.
Subsequently removing the core layer 130 of the first connection region a1 to form a second groove; the dielectric layer 110 under the first recess 10 and the second recess is etched to form a plurality of interconnect trenches. The first recess and the second recess are used to define a pattern of interconnect trenches.
In the semiconductor structure provided in the embodiment of the present invention, ions are doped in the core layer 130 located in the first spacer region b1, the ions are suitable for increasing the etching resistance of the core layer 130, or ions are doped in the core layer 130 located in the first connection region a1, the ions are suitable for decreasing the etching resistance of the core layer 130; therefore, the etching resistance of the core layer 130 of the first spacer b1 is greater than that of the core layer 130 of the first connection region a1, and the filling layer 150 is located on the dielectric layer 110 of the second spacer b2 and filled between the adjacent side walls 140; wherein, the process of doping ions in the first spacer region b1 or the core layer 130 of the first connection region a1 includes forming a first mask layer for serving as an ion-doped mask, the first mask layer correspondingly defining a pattern of the second recess, and the process of forming the filling layer 150 includes forming a second mask layer located in the second connection region a2, the second mask layer correspondingly defining a pattern of the first recess; the embodiment of the invention utilizes the first mask layer to define the pattern of the first groove and utilizes the second mask layer to define the pattern of the second groove, thereby being beneficial to preventing the mutual influence of the steps of ion doping and forming the filling layer 150, correspondingly, the first mask layer and the second mask layer can cross the first extension region I and the second extension region II along the second direction, being beneficial to reducing the pattern complexity of the first mask layer and the second mask layer, being beneficial to reducing the difficulty of the photoetching process for forming the first mask layer and the second mask layer, increasing the process window of the photoetching process (such as reducing the optical proximity effect), further improving the pattern design freedom degree and the flexibility of the interconnection grooves, realizing smaller spacing between the interconnection grooves and realizing smaller distance at the position of head to head (Tip).
In addition, in the embodiment of the present invention, the etching resistance of the core layer 130 of the first spacer b1 is greater than that of the core layer 130 of the first connection region a1, and the filling layer 150 located in the second spacer b2 is provided, so that the filling layer 150 and the sidewall 140 and the core layer 130 of the first spacer b1 are used as masks for etching the dielectric layer 110 to form the interconnection trench, that is, the filling layer 150 and the sidewall 140 and the core layer 130 of the first spacer b1 define the required pattern of the interconnection trench, so that the embodiment of the present invention avoids forming the pseudo interconnection trench, and then forms the interconnection line in the interconnection trench, and accordingly avoids forming the Floating (Floating) interconnection line, thereby being beneficial to reducing the parasitic capacitance between the subsequent interconnection structures and further beneficial to improving the performance of the semiconductor structure.
The substrate 100 is used to provide a process platform for a process recipe.
In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate 100, and a functional structure such as a resistor structure or a conductive structure may be formed in the substrate 100.
The subsequently formed interconnect trench extends in a first direction.
The dielectric layer 110 is a film layer to be patterned to form a target pattern. In this embodiment, the dielectric layer 110 is an inter-metal dielectric layer. The dielectric layer 110 is patterned subsequently, a plurality of interconnect trenches are formed in the dielectric layer 110, and then interconnect lines are formed in the interconnect trenches, the dielectric layer 110 being used to achieve electrical isolation between the interconnect lines.
The dielectric layer 110 has a single-layer or stacked-layer structure. The material of the dielectric layer 110 is a low-k dielectric material, an ultra-low k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or the like.
The core layer 130 is used to provide support for forming the sidewalls 140.
The material of the core layer 130 includes amorphous silicon, polysilicon, silicon oxide, or silicon nitride.
The core layer 130 of the first spacer region b1 is doped with ions suitable for increasing the etching resistance of the core layer 130, or the core layer 130 located in the first connection region a1 is doped with ions suitable for decreasing the etching resistance of the core layer 130. Therefore, the etching resistance of the core layer 130 of the first spacer b1 is greater than that of the core layer 130 of the first connection region a1, and the core layer 130 of the first connection region a1 and the core layer 130 of the first spacer b1 have a larger etching selectivity in the process of subsequently removing the core layer 130 of the first connection region a1, so that the core layer 130 located in the first spacer b1 can be reserved as a mask for etching the dielectric layer 110.
As an example, the core layer 130 of the first spacer b1 is doped with ions adapted to increase the etching resistance of the core layer 130. In the present embodiment, the core layer 130 located in the first connection region a1 is used as the sacrificial layer 32, and the core layer 130 located in the first spacer region b1 is used as the etching resist layer 31, that is, the core layer 130 includes the etching resist layer 31 located in the first spacer region b1 and the sacrificial layer 32 located in the first connection region a1, and the etching resistance of the etching resist layer 31 is greater than that of the sacrificial layer 32.
The resist layer 31 is correspondingly used as a mask for etching the dielectric layer 110.
The sacrificial layer 32 is used to take up space for forming the second recess.
In this embodiment, the ions doped in the core layer 130 of the first spacer b1 include one or more of boron ions, phosphorus ions, and argon ions.
The semiconductor structure further includes: the etching stop layer 115 is located between the dielectric layer 110 and the core layer 130, between the dielectric layer 110 and the sidewall 140, between the filling layer 150 and the dielectric layer 110, and on the dielectric layer 110 where the core layer 130, the sidewall 140 and the filling layer 150 are exposed.
The formation of the core layer 130 and the formation of the sidewalls 140, the first recess 10 and the subsequent second recess each comprise an etching process, in which the etch stop layer 115 is used to define the location of the etch stop. As an example, the etch stop layer 115 has a single layer structure, and the material of the etch stop layer 115 is silicon nitride.
The sidewall 140 on the sidewall of the core layer 130 is an outer sidewall, and is used for isolating the core layer 130 and the filling layer 150, so that after the sacrificial layer is removed to form the second groove, the first groove 10 and the second groove can be isolated by the sidewall 140, which is beneficial to realizing the minimum design interval between the first groove 10 and the second groove, and correspondingly beneficial to realizing the minimum design interval between the subsequent interconnection grooves.
The sidewall 140 is made of a material having etching selectivity to the core layer 130, the dielectric layer 110 and the filling layer 150, and the material of the sidewall 140 includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon.
The fill layer 150 is used as a mask for the subsequent patterned dielectric layer 110. The material of the fill layer 150 includes a silicon-containing organic (e.g., si-ARC), silicon oxide, or metal oxide.
The dielectric layer 110 under the first recess 10 and the second recess is subsequently patterned to form a target pattern.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
Providing a substrate;
forming a dielectric layer on the substrate, wherein the dielectric layer comprises a first extension region and a second extension region which extend along a first direction and are arranged at intervals along a second direction, the first extension region comprises a first connection region and a first interval region which is positioned between the first connection regions along the first direction, and the second extension region comprises a second connection region and a second interval region which is positioned between the second connection regions along the first direction;
forming a core material layer on the dielectric layer for forming a core layer separate from the first extension region;
patterning the core material layer to form a core layer positioned in the first extension region;
forming a side wall on the side wall of the core layer;
ion doping is carried out on the core material layer, so that the etching resistance of the core material layer of the first interval region is larger than that of the core material layer of the first connection region;
forming a filling layer filled between adjacent side walls on the second interval region, and forming a first groove positioned in a second connection region between adjacent filling layers along a first direction;
removing the core layer positioned in the first connecting region after ion doping and forming the core layer, the side wall and the filling layer, and forming second grooves positioned in the first connecting region, wherein the second grooves and the first grooves are arranged at intervals along a second direction;
And etching the dielectric layers below the first groove and the second groove by taking the filling layer, the side wall and the core layer positioned in the first interval region as masks to form a plurality of interconnection grooves.
2. The method of forming a semiconductor structure of claim 1, wherein ion doping is performed on the core material layer after forming the core material layer and before patterning the core material layer.
3. The method of claim 1, wherein ion doping is performed on the patterned core material layer after patterning the core material layer and before removing the core layer in the first connection region.
4. The method of claim 3, wherein said ion doping is performed after patterning said core material layer and before forming said sidewall;
or after the side wall is formed and before the filling layer is formed, carrying out ion doping;
alternatively, the ion doping is performed after the filling layer is formed and before the core layer located in the first connection region is removed.
5. The method of forming a semiconductor structure of claim 1, wherein the step of performing the ion doping comprises: ion doping is carried out on the core material layer positioned in the first interval region, so that the etching resistance of the core material layer of the first interval region is increased; or, ion doping is performed on the core material layer located in the first connection region, so that the etching resistance of the core material layer of the first connection region is reduced.
6. The method of forming a semiconductor structure of claim 5, wherein performing the ion doping comprises: forming a first mask layer positioned in the first extension region and the second extension region on the dielectric layer; taking the first mask layer as a mask, and performing ion doping on the core material layer exposed by the first mask layer; and removing the first mask layer.
7. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the sidewall spacers, the sidewall spacers are formed on top and sidewalls of the core layer and on the dielectric layer between the core layers;
the method for forming the semiconductor structure further comprises the following steps: and after the side wall is formed and before the core layer positioned in the first connection region is removed, removing the side wall positioned on the top surface of the core layer, and exposing the top surface of the core layer.
8. The method of forming a semiconductor structure of claim 7, wherein the sidewall is removed on a top surface of the core layer after forming the sidewall and before forming the filler layer;
the method for forming the semiconductor structure further comprises the following steps: and removing the side wall on the dielectric layer between the core layers in the step of removing the side wall on the top surface of the core layers.
9. The method of forming a semiconductor structure of claim 7, wherein after forming the fill layer and before removing the core layer at the first connection region, removing the sidewall on a top surface of the core layer;
in the step of forming the filling layer, the filling layer covers the side wall on the dielectric layer of the second interval region;
and in the step of removing the side wall on the top surface of the core layer, the side wall on the dielectric layer of the second connection region is also removed.
10. The method of claim 7, wherein removing the sidewall on the top surface of the core layer comprises an anisotropic dry etching process.
11. The method of forming a semiconductor structure of claim 1, wherein the step of forming the fill layer and the first recess comprises: forming a second mask layer filled between adjacent side walls on the dielectric layer of the second connection region, wherein the second mask layer exposes the dielectric layer positioned in the second interval region;
forming a filling material layer which covers and fills between the side walls of the side walls exposed by the second mask layer on the dielectric layer, wherein the filling material layer also covers the side walls, the core layer and the second mask layer;
removing the filling material layer higher than the top surface of the core layer, wherein the remaining filling material layer positioned in the second interval region is used as the filling layer;
and removing the second mask layer to form the first groove.
12. The method of forming a semiconductor structure of claim 11, wherein the process of forming the filler material layer comprises one or more of an atomic layer deposition process, a chemical vapor deposition process, and a spin-on process.
13. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a filler material layer, the filler layer material comprises silicon oxide or a metal oxide.
14. The method of forming a semiconductor structure of claim 5, wherein performing the ion doping comprises: ion doping is carried out on the core material layer positioned in the first interval region, so that the etching resistance of the core material layer of the first interval region is increased; the doped ions that ion dope the core material layer at the first spacer region include one or more of boron ions, phosphorus ions, and argon ions.
15. The method of forming a semiconductor structure of claim 1, wherein the material of the core material layer comprises amorphous silicon, polysilicon, silicon oxide, or silicon nitride.
16. A semiconductor structure, comprising:
a substrate;
the dielectric layer is positioned on the substrate and comprises first extension regions and second extension regions which extend along a first direction and are arranged at intervals along a second direction, the first extension regions comprise first connection regions and first interval regions which are positioned between the first connection regions along the first direction, and the second extension regions comprise second connection regions and second interval regions which are positioned between the second connection regions along the first direction;
the core layer is separated from the first extension region, wherein ions are doped in the core layer positioned in the first interval region, the ions are suitable for increasing the etching resistance of the core layer, or ions are doped in the core layer positioned in the first connection region, and the ions are suitable for reducing the etching resistance of the core layer;
The side wall is positioned on the side wall of the core layer;
the filling layer is positioned on the dielectric layer of the second interval region and is filled between the adjacent side walls, and the filling layer, the side walls and the core layer of the first interval region are used as masks for etching the dielectric layer to form interconnection grooves;
and the first groove is positioned in the second connection region and positioned between the adjacent filling layers along the first direction.
17. The semiconductor structure of claim 16, wherein the material of the fill layer comprises a silicon-containing organic, silicon oxide, or metal oxide.
18. The semiconductor structure of claim 16, wherein the core layer in the first spacer region is doped with ions adapted to increase the etch resistance of the core layer;
the ions doped in the core layer at the first spacer include one or more of boron ions, phosphorous ions, and argon ions.
19. The semiconductor structure of claim 16, wherein the material of the core layer comprises amorphous silicon, polysilicon, silicon oxide, or silicon nitride.
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CN108389796A (en) * 2017-02-03 2018-08-10 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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