CN113948461B - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN113948461B
CN113948461B CN202010691425.7A CN202010691425A CN113948461B CN 113948461 B CN113948461 B CN 113948461B CN 202010691425 A CN202010691425 A CN 202010691425A CN 113948461 B CN113948461 B CN 113948461B
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layer
forming
groove
side wall
opening
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CN113948461A (en
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions

Abstract

A method for forming a semiconductor structure includes: forming a planar layer having a first opening on the target layer; forming a first side wall on the side wall of the first opening; forming a sacrificial layer filling the first opening; removing the first side wall to form a gap exposing the side wall of the sacrificial layer; forming a second opening penetrating through a portion of the planarization layer between adjacent sacrificial layers along the second direction; the second opening and the first side wall form a groove, and a gap is formed between the second opening and the gap on the second side wall; forming a second side wall which is positioned on the side wall of the groove and is filled in the gap, wherein the second side wall positioned on the side wall of the groove encloses a first groove; forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall; removing the sacrificial layer to form a third groove; and patterning the target layer below the first groove, the second groove and the third groove to form a target pattern. The embodiment of the invention is beneficial to improving the graphic precision of the target graphic.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid growth of the semiconductor integrated circuit (Integrated circuit, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in integrated circuits that are smaller, more precise, and more complex.
As integrated circuits develop, the geometry (i.e., the minimum device size that can be created using process steps) generally decreases as the functional density (i.e., the number of interconnect structures per chip) increases, which correspondingly increases the difficulty and complexity of integrated circuit fabrication.
Currently, with the continued scaling of technology nodes, how to increase the matching degree between the patterns formed on the wafer and the target patterns becomes a challenge.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which improves the precision, the flexibility of layout design and the degree of freedom of a target pattern.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a flat layer on the target layer, wherein first openings penetrating through the flat layer, extending along a first direction and distributed at intervals along a second direction are formed in the flat layer, and the second direction is perpendicular to the first direction; forming a first side wall on the side wall of the first opening; forming a sacrificial layer filling the first opening on the side wall of the first side wall, wherein the side wall opposite to the adjacent sacrificial layer along the second direction is a first side wall and a second side wall respectively; removing the first side wall to form a gap exposing the side wall of the sacrificial layer; forming a second opening penetrating through a portion of the planarization layer between adjacent sacrificial layers along the second direction; the second opening and the first side wall form a groove, and a gap is formed between the second opening and the gap on the second side wall; forming a second side wall which is positioned on the side wall of the groove and is filled in the gap, wherein the second side wall positioned on the side wall of the groove encloses a first groove; forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall; removing the sacrificial layer to form a third groove; the third groove, the second groove and the first groove are isolated by a second side wall; and patterning the target layer below the first groove, the second groove and the third groove by taking the second side wall and the flat layer as masks to form a target pattern.
Optionally, the step of forming the planarization layer and the first opening includes: forming a planar material layer on the target layer; patterning the flat material layer to form a plurality of first openings penetrating the flat material layer, wherein the remaining flat material layer is used as the flat layer.
Optionally, the step of forming the planarization layer and the first opening includes: forming a plurality of discrete placeholders on the target layer; forming the flat layer covering the side wall of the space occupying layer on the target layer; and removing the occupying layer to form the first opening.
Optionally, the process of patterning the planar material layer includes an anisotropic dry etching process.
Optionally, the process of forming the first side wall includes an atomic layer deposition process.
Optionally, the step of forming the sacrificial layer includes: filling a sacrificial material layer in the first opening, wherein the sacrificial material layer also covers the flat layer; and removing the sacrificial material layer higher than the top of the flat layer to form a sacrificial layer filled in the first opening.
Optionally, the process of forming the sacrificial material layer includes one or more of a spin-on process, an atomic layer deposition process, and a chemical vapor deposition process.
Optionally, the process of removing the sacrificial material layer above the top of the planar layer includes a dry etching process or a chemical mechanical polishing process.
Optionally, in the step of forming the sacrificial layer, a material of the sacrificial layer includes one or more of silicon oxide, metal oxide, polysilicon, and amorphous silicon.
Optionally, the process of removing the first side wall includes one or two processes of dry etching and wet etching.
Optionally, after the second opening is formed, removing the first side wall; alternatively, the second opening is formed after the first sidewall is removed.
Optionally, the process of forming the second side wall includes an atomic layer deposition process.
Optionally, the material of the first side wall includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride and titanium oxide.
Optionally, the material of the second side wall is the same as the material of the first side wall.
Optionally, the thickness of the second side wall located on the side wall of the groove is greater than or equal to 0.5 times the thickness of the first side wall along the direction parallel to the substrate.
Optionally, the material of the planarization layer includes one or more of polysilicon, amorphous silicon, silicon oxide, silicon nitride, and amorphous carbon.
Optionally, the process of removing the sacrificial layer includes one or both of wet etching and dry etching.
Optionally, the target layer comprises a dielectric layer; patterning the dielectric layers below the first groove, the second groove and the third groove by taking the second side wall and the flat layer as masks, and forming a plurality of interconnection grooves in the dielectric layers; the method for forming the semiconductor structure further comprises the following steps: and forming an interconnection line in the interconnection groove.
Optionally, the target layer further includes a layer of hard mask material on the dielectric layer.
Optionally, the material of the hard mask material layer includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide and silicon oxycarbonitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, the sacrificial layer occupies space for forming the third groove so as to define the graph and the position of the third groove; after forming the groove, forming a second side wall positioned on the side wall of the groove, and surrounding the second side wall positioned on the side wall of the groove into a first groove, wherein correspondingly, the pattern and the position of the first groove are defined through the groove and the second side wall; forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall; therefore, the patterns and positions of the third groove and the first groove are correspondingly defined through the sacrificial layer, the groove and the second side wall, the second groove is formed in different steps, difficulty in forming the first groove, the second groove and the third groove is reduced, process windows are increased (for example, optical proximity effect is improved), the degree of freedom and flexibility of pattern design of the first groove, the second groove and the third groove are improved, pattern precision of the first groove, the second groove and the third groove is guaranteed, the first groove, the second groove and the third groove are distributed at intervals along the second direction, adjacent grooves are isolated by the second side wall, minimum design intervals (Designed minimum space) are formed between the adjacent grooves, after the target layers below the first groove, the second groove and the third groove are patterned by taking the second side wall and the flat layer as masks, pattern quality and pattern precision of the target patterns are improved, and minimum design intervals between the adjacent target patterns are easily met.
In addition, a flat layer is formed on the target layer, a first opening is formed in the flat layer, a first side wall is formed on the side wall of the first opening, and then a sacrificial layer for filling the first opening is formed on the side wall of the first side wall; therefore, in the embodiment of the present invention, the pattern and the position of the sacrificial layer are defined through the first opening and the first sidewall, that is, the pattern and the position of the third groove are defined through the first opening and the first sidewall, and compared with the scheme that the pattern and the position of the third groove are defined in one etching step or in a single film structure, the pattern and the position of the third groove are defined through the first opening and the first sidewall, when the first opening is formed, the critical dimension of the first opening is larger than the critical dimension of the third groove, which is favorable for reducing the difficulty of forming the first opening and increasing the process window of the photolithography process for forming the first opening, for example: the requirement on the precision of the photoetching process for forming the first opening is reduced, the pattern quality and the pattern precision of the first opening are correspondingly improved, and then the pattern quality of the sacrificial layer is also easy to be higher by adjusting the thickness of the first side wall, so that the pattern precision and the pattern quality of the target pattern are improved.
Drawings
Fig. 1 to 21 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
From the background, how to improve the matching degree between the pattern formed on the wafer and the target pattern is a challenge. Specifically, in the current back-end process, the difficulty of the patterning process of the metal interconnection line is high, and the process window is small.
For example: when the pattern of the interconnection pattern is complex, the number of photomasks (masks) required by the photolithography process is large, which not only results in excessively high process cost, but also results in complex patterns of photomasks, and the optical proximity correction process of the photomasks also has higher difficulty, so that the pattern precision and the pattern quality of the formed interconnection line are poor, and even the problem that the interconnection line is short-circuited (Bridge) at the position where the interconnection line is not required to be connected is easily caused.
One approach utilizes Dummy interconnect lines (Dummy lines) to increase the window of the lithographic process and reduce mask pattern complexity. In operation of the device, the dummy interconnect lines are in a floating state, that is, the interconnect lines are not electrically connected to external circuitry or other interconnect structures. However, these floating dummy interconnect lines tend to increase parasitic capacitance of the back-end interconnect, resulting in poor performance of the formed semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a flat layer on the target layer, wherein first openings penetrating through the flat layer, extending along a first direction and distributed at intervals along a second direction are formed in the flat layer, and the second direction is perpendicular to the first direction; forming a first side wall on the side wall of the first opening; forming a sacrificial layer filling the first opening on the side wall of the first side wall, wherein the side wall opposite to the adjacent sacrificial layer along the second direction is a first side wall and a second side wall respectively; removing the first side wall to form a gap exposing the side wall of the sacrificial layer; forming a second opening penetrating through a portion of the planarization layer between adjacent sacrificial layers along the second direction; the second opening and the first side wall form a groove, and a gap is formed between the second opening and the gap on the second side wall; forming a second side wall which is positioned on the side wall of the groove and is filled in the gap, wherein the second side wall positioned on the side wall of the groove encloses a first groove; forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall; removing the sacrificial layer to form a third groove; the third groove, the second groove and the first groove are isolated by a second side wall; and patterning the target layer below the first groove, the second groove and the third groove by taking the second side wall and the flat layer as masks to form a target pattern.
In the method for forming a semiconductor structure provided by the embodiment of the invention, the sacrificial layer occupies space for forming the third groove so as to define the graph and the position of the third groove; after forming the groove, forming a second side wall positioned on the side wall of the groove, and surrounding the second side wall positioned on the side wall of the groove into a first groove, wherein correspondingly, the pattern and the position of the first groove are defined through the groove and the second side wall; forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall; therefore, the patterns and positions of the third groove and the first groove are correspondingly defined through the sacrificial layer, the groove and the second side wall, the second groove is formed in different steps, difficulty in forming the first groove, the second groove and the third groove is reduced, process windows are increased (for example, optical proximity effect is improved), the degree of freedom and flexibility of pattern design of the first groove, the second groove and the third groove are improved, pattern precision of the first groove, the second groove and the third groove is guaranteed, the first groove, the second groove and the third groove are distributed at intervals along the second direction, adjacent grooves are isolated by the second side wall, minimum design intervals (Designed minimum space) are formed between the adjacent grooves, after the target layers below the first groove, the second groove and the third groove are patterned by taking the second side wall and the flat layer as masks, pattern quality and pattern precision of the target patterns are improved, and minimum design intervals between the adjacent target patterns are easily met.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 21 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a substrate including a target layer 110 for forming a target pattern is provided.
The substrate is used for providing a platform for the subsequent process. The target layer 110 is a film layer to be patterned to form a target pattern. The target pattern may be a gate structure, an interconnect trench in a back-end-of-line process, a fin in a fin field effect transistor (FinFET), a channel stack or a Hard Mask (HM) layer in a full-wrap Gate (GAA) transistor, and the like.
In this embodiment, the target layer 110 includes a dielectric layer 111. The dielectric layer 111 is patterned subsequently, a plurality of interconnect trenches are formed in the dielectric layer 111, and then interconnect lines are formed in the interconnect trenches, the dielectric layer 111 being used to electrically isolate adjacent interconnect lines. Accordingly, in this embodiment, the target pattern is an interconnection groove.
Thus, the dielectric layer 111 is an inter-metal dielectric (Inter Metal Dielectric, IMD) layer.
Accordingly, in this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate, and functional structures such as a resistor structure or a conductive structure may be formed in the substrate. In this embodiment, the base includes a substrate 100 and a target layer 110 on the substrate 100.
The material of the dielectric layer 111 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or the like. In this embodiment, the material of the dielectric layer 111 is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end metal interconnection structures, and further reduce the back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.
In this embodiment, the target layer 110 is a stacked structure, and the target layer 110 includes a dielectric layer 111 and a hard mask material layer 112 disposed on the dielectric layer 111.
In the subsequent step of patterning the target layer 110, the hard mask material layer 112 is patterned to form a hard mask layer, and then the dielectric layer 111 is patterned by using the hard mask layer as a mask, so that the process stability of the patterned dielectric layer 111 is improved, and the accuracy of pattern transfer is correspondingly improved.
The material of the hard mask material layer 112 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the hard mask material layer 112 is titanium nitride.
In a specific process, a stress buffer layer can also be disposed between the hard mask material layer 112 and the dielectric layer 111 according to actual process requirements, so as to improve adhesion between the hard mask material layer 112 and the dielectric layer 111 and reduce stress generated between the film layers. In addition, an etching stop layer can be disposed between the hard mask material layer 112 and the stress buffer layer and on the hard mask material layer 112 to define a stop position of a subsequent etching process, which is beneficial to improving the effect of the subsequent patterning process. The description of the stress buffer layer and the etch stop layer is omitted here.
Referring to fig. 1 to 3 in combination, a planarization layer 120 is formed on the target layer 110, and first openings 10 extending through the planarization layer 120 and extending in a first direction (as shown in an x direction in fig. 2) and spaced apart in a second direction (as shown in a y direction in fig. 2) perpendicular to the first direction are formed in the planarization layer 120.
The flat layer 120 of the sidewall of the first opening 10 provides a supporting function for the subsequent formation of the first sidewall.
The planarization layer 120 is used as an etch mask for subsequent patterning of the target layer 110.
In addition, in the embodiment of the present invention, the planarization layer 120 is formed first, then, the first sidewall is formed on the sidewall of the first opening 10, the sacrificial layer filling the first opening 10 is formed on the first sidewall, the trench is formed in the planarization layer 120, and the second recess is formed in the planarization layer 120, so that the subsequent step of forming the planarization layer on the target layer 110 is omitted.
In the embodiment of the invention, a flat layer 120 is formed on the target layer 110, a first opening 10 is formed in the flat layer 120, a first side wall is formed on the side wall of the first opening 10, and then a sacrificial layer for filling the first opening 10 is formed on the side wall of the first side wall; therefore, in the embodiment of the present invention, the first opening 10 and the first side wall define the pattern and the position of the sacrificial layer, and compared with the scheme that the pattern and the position of the sacrificial layer are defined in one etching step or in a single film structure, the pattern and the position of the sacrificial layer are defined by the first opening 10 and the first side wall, when the first opening 10 is formed, the critical dimension of the first opening 10 is larger than the critical dimension of the sacrificial layer, which is beneficial to reducing the difficulty of forming the first opening 10 and increasing the process window of the photolithography process for forming the first opening 10, for example: the requirement on the precision of the photoetching process for forming the first opening 10 is reduced, the friendliness of the photoetching process is improved, the pattern quality and the pattern precision of the first opening 10 are correspondingly improved, and then the sacrificial layer is easy to have higher pattern quality by adjusting the thickness of the first side wall.
The planarization layer 120 is made of a material having etching selectivity to the material of the target layer 110, so as to ensure the effect of the planarization layer 120 serving as an etching mask for patterning the target layer 110. The material of the planarization layer 120 includes one or more of polysilicon, amorphous silicon, silicon oxide, silicon nitride, and amorphous carbon. In this embodiment, the planarization layer 120 has a single-layer structure, and the material of the planarization layer 120 is amorphous silicon.
In the present embodiment, two first openings 10 are formed in the planarization layer 120 as an example. In other embodiments, the first openings in the planar layer can be other numbers, and the pattern and location of the first openings can be determined according to actual design requirements.
As an example, the step of forming the planarization layer 120 and the first opening 10 includes: as shown in fig. 1, a flat material layer 115 is formed on the target layer 110; as shown in fig. 2 and 3, fig. 2 is a top view, fig. 3 is a cross-sectional view of fig. 2 at the AA position, the planarization material layer 115 is patterned, and a plurality of first openings 10 penetrating the planarization material layer 115 are formed, and the remaining planarization material layer 115 is used as the planarization layer 120.
In this embodiment, the flat material layer 115 is formed by a deposition process (e.g., a chemical vapor deposition process).
In this embodiment, the step of patterning the flat material layer 115 includes: forming a photoresist layer (not shown) on the flat material layer 115, the photoresist layer having a pattern opening formed therein; the planar material layer 115 under the pattern openings is patterned using the photoresist layer as a mask.
In this embodiment, the photoresist layer is used to define the pattern and the position of the first opening 10, and the forming process of the photoresist layer includes exposure, development, and other photolithography processes. As can be seen from the foregoing, the critical dimension of the first opening 10 is larger, which is advantageous for the difficulty of the process of forming the photoresist layer and increasing the process window of the photolithography process of forming the photoresist layer, thereby being advantageous for improving the pattern quality and pattern precision of the pattern opening, and correspondingly being advantageous for improving the pattern quality and pattern precision of the first opening 10, and the pattern of the photoresist layer is opposite to the subsequent pattern of the first sidewall and the sacrificial layer (Reverse tone), thereby being advantageous for further increasing the process window of forming the photoresist layer.
In this embodiment, the process of patterning the flat material layer 115 includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, has high controllability of etching profile, and is beneficial to improving the accuracy of pattern transmission, and further beneficial to improving the pattern quality of the first opening 10.
In this embodiment, after the first opening 10 is formed, the forming method further includes: and removing the photoresist layer. The photoresist layer removing process includes an ashing process and a wet photoresist removing process.
In other embodiments, the step of forming the planarization layer and the first opening includes: forming a plurality of discrete placeholders on the target layer; forming the flat layer covering the side wall of the space occupying layer on the target layer; and removing the occupying layer to form the first opening. Accordingly, the shape and position of the first opening are defined by the placeholder layer.
Referring to fig. 4 and 5, fig. 4 is a top view, and fig. 5 is a cross-sectional view of fig. 4 at the AA position, and a first sidewall 130 is formed at a sidewall of the first opening 10.
The first sidewall 130 is used to occupy a part of the space of the first opening 10, so that after the sacrificial layer filled in the first opening 10 is formed subsequently, the critical dimension of the sacrificial layer is smaller than that of the first opening 10, and therefore, the pattern and the position of the sacrificial layer are defined through the first opening 10 and the first sidewall 130.
In addition, a sacrificial layer filling the first opening 10 is formed on the side wall of the first side wall 130, and the opposite side walls of the adjacent sacrificial layer along the second direction are a first side wall and a second side wall respectively; forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall; removing the sacrificial layer to form a third groove; accordingly, a space between the second recess and the third recess corresponding to the sacrificial layer having the second sidewall is defined by the first sidewall 130. Therefore, by forming the first side wall 130, the embodiment of the invention can easily adjust the thickness of the first side wall 130, so that the minimum design interval between the third groove and the second groove is satisfied.
The first sidewall 130 is made of a material having etching selectivity with the materials of the planarization layer 120, the target layer 110 and the subsequent sacrificial layer, so as to reduce the influence of the subsequent process of removing the first sidewall 130 on the planarization layer 120, the target layer 110 and the sacrificial layer. The material of the first sidewall 130 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride and titanium oxide.
In this embodiment, the material of the first sidewall 130 is silicon nitride.
In this embodiment, the step of forming the first sidewall 130 includes: forming a first sidewall film (not shown) conformally covering the bottom and sidewalls of the first opening 10 and the top surface of the planarization layer 120; and removing the first sidewall film at the bottom of the first opening 10 and the top surface of the flat layer 120, and reserving the first sidewall film at the sidewall of the first opening 10 as the first sidewall 130.
Specifically, the first sidewall film is formed using an atomic layer deposition (Atomic Layer Deposition, ALD) process. The first side wall film formed by adopting the atomic layer deposition process has good thickness uniformity, can have good step coverage capability, and meanwhile, the atomic layer deposition process is a self-limiting reaction process based on the atomic layer deposition process, and the deposited film can reach the thickness of a single-layer atom.
Accordingly, since the first sidewall film conformally covers the bottom and the sidewall of the first opening 10 and the top surface of the flat layer 120, the anisotropic maskless etching process can be used to remove the first sidewall film located at the bottom of the first opening 10 and the top surface of the flat layer 120, so that a photomask is not required in the step of forming the first sidewall 130, which is beneficial to saving cost. Specifically, the anisotropic dry etching process is adopted to perform the anisotropic maskless etching process, so that the damage to other film structures is small while the side wall films at the bottom of the first opening 10 and the top surface of the flat layer 120 are removed, and the lateral etching of the first side wall film at the side wall of the first opening 10 is small.
Referring to fig. 6 and 7, fig. 6 is a top view, fig. 7 is a cross-sectional view of fig. 6 at the AA position, a sacrificial layer 140 filling the first opening 10 is formed on the sidewall of the first sidewall 130, and the opposite sidewalls of adjacent sacrificial layers 140 along the second direction are the first sidewall 11 and the second sidewall 12, respectively.
The sacrificial layer 140 is used to occupy a spatial position for forming the third recess, and thus the sacrificial layer 140 defines the pattern and position of the subsequent third recess.
In the embodiment of the invention, a flat layer 120 with a first opening 10 is formed on the target layer 110, then a first side wall 130 is formed on the side wall of the first opening 10, and then a sacrificial layer 140 filling the first opening 10 is formed on the side wall of the first side wall 130; therefore, in the embodiment of the present invention, the pattern and the position of the sacrificial layer 140 are defined through the first opening 10 and the first sidewall 130, that is, the pattern and the position of the third groove are defined through the first opening 10 and the first sidewall 130, and compared with the scheme that the pattern and the position of the third groove are defined through the first opening 10 and the first sidewall 130 in one etching step or by a single film structure, the critical dimension of the first opening 10 is larger than the critical dimension of the third groove when the first opening 10 is formed, which is beneficial to reducing the difficulty of forming the first opening 10 and increasing the process window of the photolithography process for forming the first opening 10, for example: the requirement on the precision of the photolithography process for forming the first opening 10 is reduced, which is correspondingly beneficial to improving the pattern quality and the pattern precision of the first opening 10, and then the thickness of the first side wall 130 is adjusted, so that the sacrificial layer 140 is easy to have smaller critical dimension and higher pattern quality, and further the pattern precision and the pattern quality of the target pattern are improved.
Along the second direction, the opposite side walls of the adjacent sacrificial layers 140 are a first side wall 11 and a second side wall 12, and the first side wall 11 and the second side wall 12 are spaced apart from each other.
The sacrificial layer 140 is removed later, so that the sacrificial layer 140 is made of a material easy to remove, so that the difficulty in removing the sacrificial layer 140 later is reduced; in addition, the sacrificial layer 140 is further made of a material having etching selectivity to the material of the first sidewall 130, the planarization layer 120 and the subsequent second sidewall. In this embodiment, in the step of forming the sacrificial layer 140, the material of the sacrificial layer 140 includes one or more of silicon oxide, metal oxide, polysilicon, and amorphous silicon.
As an example, the material of the sacrificial layer 140 is silicon oxide.
In this embodiment, the step of forming the sacrificial layer 140 includes: filling the first opening 10 with a sacrificial material layer (not shown), which also covers the planarization layer 120; the sacrificial material layer higher than the top of the planarization layer 120 is removed to form the sacrificial layer 140 filled in the first opening 10.
The process of forming the sacrificial material layer includes one or more of a spin-on process, an atomic layer deposition process, and a chemical vapor deposition process. In this embodiment, a spin coating process is used to form the sacrificial material layer. The spin coating process is simple to operate, low in process cost, easy to form a film layer with higher surface flatness, and in addition, the spin coating process is beneficial to improving the filling capability of the sacrificial material layer in the first opening 10.
In this embodiment, a planarization process is used to remove the sacrificial material layer above the top of the planarization layer 120. Specifically, the process of removing the sacrificial material layer higher than the planarization layer 120 includes a dry etching process or a chemical mechanical polishing process.
Referring to fig. 8 and 9, fig. 8 is a top view, and fig. 9 is a cross-sectional view of fig. 8 at the AA position, wherein the first sidewall 130 is removed to form a gap 20 exposing the sidewall of the sacrificial layer 140.
Removing the first side wall 130 to expose the side wall of the sacrificial layer 140, particularly the first side wall 11, so that after forming a second opening penetrating through a portion of the planarization layer 120 between adjacent sacrificial layers 140 along the second direction, the second opening can form a trench with the first side wall 11; after forming the second side wall located on the side wall of the groove, the second side wall located on the side wall of the groove encloses a first groove, correspondingly, after the sacrificial layer 140 is removed later to form a third groove, the third groove is isolated from the first groove by the second side wall, and the interval between the third groove and the first groove is the thickness of the second side wall.
The process of removing the first sidewall 130 includes one or both of dry etching and wet etching. In this embodiment, the first side wall 130 is removed by a wet etching process, which is easy to implement a higher etching selectivity, and is favorable for removing the first side wall 130 cleanly, and is simple to operate. Specifically, the material of the first sidewall 130 is silicon nitride, and the etching solution of the wet etching process is a hot phosphoric acid solution.
Referring to fig. 10 and 11, fig. 10 is a top view, fig. 11 is a cross-sectional view of fig. 10 at the AA position, forming a second opening 30 through a portion of the planarization layer 120 between adjacent sacrificial layers 140 along the second direction; the second opening 30 and the first sidewall 11 form a trench 40, and a space is provided between the second opening 30 and the gap 20 on the second sidewall 12.
The second opening 30 is configured to enclose a trench 40 with the first sidewall 11 after the first sidewall 130 is removed. The side wall of the trench 40 is used for providing support for the subsequent formation of the second side wall, the trench 40 and the subsequent second side wall located on the side wall of the trench 40 together define the pattern and the position of the subsequent first groove, compared with the pattern and the position of the first groove defined in a single etching step or by using a single film layer, the embodiment of the invention is beneficial to reducing the difficulty of forming the first groove, correspondingly improving the pattern precision of the first groove, and the critical dimension of the first groove is easy to adjust by adjusting the thickness of the second side wall, so that the critical dimension of the first groove meets the design requirement.
The second opening 30 is spaced from the gap 20 on the second sidewall 12, that is, the trench 40 is spaced from the gap 20 on the second sidewall 12, so that a portion of the flat layer 120 remains between the trench 40 and the gap 20 on the second sidewall 12, so as to facilitate the subsequent formation of a second recess penetrating through the flat layer 120 between the first recess and the second sidewall of the second sidewall 12.
In this embodiment, the second opening 30 is formed after the first sidewall 130 is removed, and as an example, the second opening 30 communicates with the gap 20 located in the first sidewall 11 to form the trench 40.
In other embodiments, the first sidewall can also be removed after the second opening is formed.
In this embodiment, the second opening 30 is formed by etching a portion of the planarization layer 120 between adjacent sacrificial layers 140 along the second direction using an anisotropic dry etching process. The anisotropic dry etching process is advantageous for improving the accuracy of pattern transfer.
Referring to fig. 12 and 13, fig. 12 is a top view, and fig. 13 is a cross-sectional view of fig. 12 at the AA position, forming a second sidewall 150 on the sidewall of the trench 40 and filling the gap 20, and the second sidewall 150 on the sidewall of the trench 40 encloses the first groove 101.
The first groove 101 is used to define the pattern and position of the target pattern.
The second sidewall 150 is used to jointly serve as a mask for patterning the target layer 110 with the planarization layer 120.
In this embodiment, the pattern and the position of the first groove 101 are defined by the trench 40 and the second sidewall 150. After the sacrificial layer 140 is removed to form the third groove, the third groove is isolated from the first groove 101 by the second sidewall 150, and after the second groove penetrating through the first groove 101 and the flat layer 120 between the second sidewall 150 of the second sidewall 12 is formed, the second groove is also isolated from the first groove 101 by the second sidewall 150, which is beneficial to realizing the minimum design interval between the adjacent grooves.
In this embodiment, the thickness of the second sidewall 150 located on the sidewall of the trench 30 is greater than or equal to 0.5 times the thickness of the first sidewall 130 along the direction parallel to the substrate. The width of the first gap 20 is defined by the thickness of the first sidewall 130 along the direction parallel to the substrate, and the thickness of the second sidewall 150 located on the sidewall of the trench 30 is greater than or equal to 0.5 times the thickness of the first sidewall 130, so as to ensure that the second sidewall 150 can fill the gap 20 located between the sidewall of the sacrificial layer 140 and the planarization layer 120.
In this embodiment, the thickness of the second sidewall 150 is the same as the thickness of the first sidewall 130 along the direction parallel to the substrate, and accordingly, after the second groove and the third groove are formed subsequently, the intervals between two adjacent grooves are the same along the second direction, and after the target layer 110 under the first groove 101, the second groove and the third groove is patterned to form the target pattern, the intervals between the target patterns are the same along the second direction, so that the uniformity of the intervals between the target patterns is improved.
In a specific implementation, the thickness of the second side wall 150 can also be different from the thickness of the first side wall 130, so that the interval between two adjacent grooves is different by adjusting the thicknesses of the second side wall 150 and the first side wall 130 according to actual requirements, and the design flexibility and the degree of freedom of the interval between the target patterns are improved.
In this embodiment, the second side wall 150 is made of a material having etching selectivity to the sacrificial layer 140 and the target layer 110, so as to improve the etching selectivity ratio of the sacrificial layer 140 to the second side wall 150 in the subsequent process of removing the sacrificial layer 140, and improve the effect of the patterning process of subsequently patterning the planarization layer 120 under the first groove 101, the second groove and the third groove. The material of the second sidewall 150 includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon.
In this embodiment, the material of the second side wall 150 is the same as that of the first side wall 130, so that the types of materials introduced in the semiconductor manufacturing process are reduced, which is beneficial to improving the process compatibility and reducing the process risk.
In this embodiment, the step of forming the second sidewall 150 includes: conformally covering a second sidewall film (not shown) on the sacrificial layer 140, the planarization layer 120 and the target layer 110, wherein the second sidewall film fills the gap 20; and removing the second sidewall films on the top surfaces of the sacrificial layer 140 and the flat layer 120 and the bottom of the trench 40 to form the second sidewall 150.
In this embodiment, the process of forming the second sidewall film includes an atomic layer deposition process.
In this embodiment, an anisotropic dry etching process is used to remove the second sidewall films on the top surfaces of the sacrificial layer 140 and the planarization layer 120, and on the bottom of the trench 40.
Referring to fig. 14 and 15, fig. 14 is a top view, and fig. 15 is a cross-sectional view of fig. 14 at the AA position, forming a second recess 102 through the planar layer 120 between the first recess 101 and the second sidewall 150 of the second sidewall 12.
The second recess 102 is used to define the pattern and location of the subsequent target pattern.
In this embodiment, in the step of forming the second groove 102, since the material of the planar layer 120 and the material of the second sidewall 150 have a higher etching selectivity, even if the mask layer used to form the second groove 102 exposes a portion of the second sidewall 150, the probability of the second sidewall 150 being erroneously etched is low, so that the etching process of the second groove 102 can implement Self-alignment (Self-aligned) according to the position of the second sidewall 150, which is beneficial to reducing the difficulty of forming the second groove 102, increasing the process window for forming the second groove 102, and further beneficial to improving the pattern precision and the pattern quality of the second groove 102, and correspondingly, the pattern precision and the pattern quality of the target pattern formed subsequently are also higher.
In this embodiment, an etching process (e.g., anisotropic dry etching) is used to etch the flat layer 120 between the first recess 101 and the second sidewall 150 of the second sidewall 12, so as to form the second recess 102.
Referring to fig. 16 and 17, fig. 16 is a top view, fig. 17 is a cross-sectional view of fig. 16 at the AA position, and the sacrificial layer 140 is removed to form a third recess 103; the third groove 103, the second groove 102 and the first groove 101 are isolated by a second side wall 150.
In the method for forming a semiconductor structure provided in the embodiment of the present invention, the sacrificial layer 140 occupies a space for forming the third groove 103, so as to define a pattern and a position of the third groove 103; after forming the groove 40, forming a second side wall 150 positioned on the side wall of the groove 40, wherein the second side wall 150 positioned on the side wall of the groove 40 encloses a first groove 101, and correspondingly, the pattern and the position of the first groove 101 are defined through the groove 40 and the second side wall 150; forming a second groove 102, penetrating through the first groove 101 and the flat layer 120 between the second side walls 150 of the second side walls 12; therefore, the patterns and positions of the third groove 103 and the first groove 101 are correspondingly defined through the sacrificial layer 140 and the grooves 40 and the second side walls 150, and the second groove 102 is formed in different steps, so that the difficulty in forming the first groove 101, the second groove 102 and the third groove 103 is reduced, the process window is increased (for example, the optical proximity effect is improved), the degree of freedom and the flexibility of pattern design of the first groove 101, the second groove 102 and the third groove 103 are improved, the pattern precision of the first groove 101, the second groove 102 and the third groove 103 is ensured, the first groove 101, the second groove 102 and the third groove 103 are distributed at intervals along the second direction, the adjacent grooves are separated by the second side walls 150, the minimum designed interval (Designed minimum space) is realized between the adjacent grooves, after the target layer 110 below the first groove 101, the second groove 102 and the third groove 103 is patterned by taking the second side walls 150 and the flat layer 120 as masks, the quality of the target pattern is easily formed, the target pattern is improved, and the minimum designed pattern is easily satisfied, and the minimum designed target pattern is realized.
The process of removing the sacrificial layer 140 includes one or both of wet etching and dry etching. As an example, the sacrificial layer 140 is removed using a wet etching process. In this embodiment, the material of the sacrificial layer 140 is silicon oxide, and thus, the etching solution of the wet etching process includes a hydrofluoric acid solution (DHF).
Referring to fig. 18 and 19, fig. 18 is a top view, fig. 19 is a cross-sectional view of fig. 18 at the AA position, and the second sidewall 150 and the planarization layer 120 are used as masks to pattern the target layer 110 under the first groove 101, the second groove 102 and the third groove 103, thereby forming a target pattern.
As can be seen from the foregoing, the degree of freedom and flexibility of the pattern design of the first groove 101, the second groove 102 and the third groove 103 are high, so that the pattern precision of the first groove 101, the second groove 102 and the third groove 103 is guaranteed, and it is beneficial to achieve the minimum design interval between adjacent grooves, accordingly, after the target layer 110 under the first groove 101, the second groove 102 and the third groove 103 is patterned, the pattern quality and the pattern precision of the target pattern are improved, and the minimum design interval is easily achieved between adjacent target patterns along the second direction. Furthermore, the present invention advantageously enables adjacent target patterns to achieve smaller distances at head-to-head locations.
In this embodiment, the target layer 110 includes a dielectric layer 111, so the dielectric layer 111 under the first recess 101, the second recess 102 and the third recess 103 is patterned with the second sidewall 150 and the planarization layer 120 as masks, and a plurality of interconnection trenches 40 are formed in the dielectric layer 111.
Accordingly, in the present embodiment, the target pattern is the interconnection groove 40.
The interconnect trenches 40 are used to provide space for forming interconnect lines in a back-end-of-line process.
Specifically, in this embodiment, the second side wall 150 and the flat layer 120 are used as masks, and the hard mask material layer 112 under the first groove 101, the second groove 102 and the third groove 103 is patterned to form the hard mask layer 160; the dielectric layer 111 is patterned using the hard mask layer 160 as a mask to form the interconnect trench 40.
Referring to fig. 20 and 21 in combination, fig. 20 is a top view, fig. 21 is a cross-sectional view of fig. 20 at an AA position, and in this embodiment, the method for forming a semiconductor structure further includes: an interconnect line 170 is formed in the interconnect trench 40.
The interconnection groove 40 formed in the embodiment can achieve a smaller distance at the head-to-head position, and accordingly, the interconnection line 170 can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the connection capability of the interconnection line 170 at the head-to-head position, and is beneficial to improving the degree of freedom and flexibility of layout design of the interconnection line 170; moreover, the spacing between adjacent interconnect trenches 40 in the second direction is easy to satisfy the design minimum spacing, and the pattern accuracy of the interconnect trenches 40 is high, which is correspondingly beneficial to enabling the spacing between the interconnect lines 170 in the second direction to satisfy the design minimum spacing, and improving the pattern accuracy of the interconnect lines 170, thereby improving the performance of the semiconductor structure.
Interconnect lines 170 are used to make electrical connection of the semiconductor structure to external circuitry or other interconnect structures.
In this embodiment, the interconnect 170 is made of copper. In other embodiments, the interconnect material can also be a conductive material such as cobalt, tungsten, aluminum, etc.
In this embodiment, in the step of interconnecting the lines 170, the planarization layer 120, the second sidewalls 150, and the hard mask layer 160 are also removed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a target layer for forming a target pattern;
forming a flat layer on the target layer, wherein first openings penetrating through the flat layer and extending along a first direction and being distributed at intervals along a second direction are formed in the flat layer, and the second direction is perpendicular to the first direction;
forming a first side wall on the side wall of the first opening;
forming a sacrificial layer filling the first opening on the side wall of the first side wall, wherein the side wall opposite to the adjacent sacrificial layer along the second direction is a first side wall and a second side wall respectively;
Removing the first side wall to form a gap exposing the side wall of the sacrificial layer;
forming a second opening penetrating through a portion of the planarization layer between adjacent sacrificial layers along the second direction; the second opening and the first side wall form a groove, and a gap is formed between the second opening and the gap on the second side wall;
forming a second side wall which is positioned on the side wall of the groove and is filled in the gap, wherein the second side wall positioned on the side wall of the groove encloses a first groove;
forming a second groove, penetrating through the first groove and a flat layer positioned between the second side wall of the second side wall;
removing the sacrificial layer to form a third groove; the third groove, the second groove and the first groove are isolated by a second side wall;
and patterning the target layer below the first groove, the second groove and the third groove by taking the second side wall and the flat layer as masks to form a target pattern.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the planarization layer and the first opening comprises: forming a planar material layer on the target layer; patterning the flat material layer to form a plurality of first openings penetrating the flat material layer, wherein the remaining flat material layer is used as the flat layer.
3. The method of forming a semiconductor structure of claim 1, wherein the step of forming the planarization layer and the first opening comprises: forming a plurality of discrete placeholders on the target layer; forming the flat layer covering the side wall of the space occupying layer on the target layer; and removing the occupying layer to form the first opening.
4. The method of forming a semiconductor structure of claim 2, wherein patterning the layer of planar material comprises an anisotropic dry etching process.
5. The method of forming a semiconductor structure of claim 1, wherein forming said first sidewall comprises an atomic layer deposition process.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the sacrificial layer comprises: filling a sacrificial material layer in the first opening, wherein the sacrificial material layer also covers the flat layer;
and removing the sacrificial material layer higher than the top of the flat layer to form a sacrificial layer filled in the first opening.
7. The method of forming a semiconductor structure of claim 6, wherein the process of forming the layer of sacrificial material comprises one or more of a spin-on process, an atomic layer deposition process, and a chemical vapor deposition process.
8. The method of claim 6, wherein removing the sacrificial material layer above the top of the planarization layer comprises a dry etching process or a chemical mechanical polishing process.
9. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the sacrificial layer, a material of the sacrificial layer comprises one or more of silicon oxide, metal oxide, polysilicon, and amorphous silicon.
10. The method of forming a semiconductor structure of claim 1, wherein the process of removing the first sidewall includes one or both of a dry etch and a wet etch.
11. The method of forming a semiconductor structure of claim 1, wherein after forming the second opening, removing the first sidewall; alternatively, the second opening is formed after the first sidewall is removed.
12. The method of forming a semiconductor structure of claim 1, wherein forming said second sidewall comprises an atomic layer deposition process.
13. The method of forming a semiconductor structure of claim 1, wherein the material of the first sidewall comprises one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide.
14. The method of claim 1, wherein the material of the second sidewall is the same as the material of the first sidewall.
15. The method of claim 1, wherein a thickness of the second sidewall of the trench sidewall is greater than or equal to 0.5 times a thickness of the first sidewall in a direction parallel to the substrate.
16. The method of forming a semiconductor structure of claim 1, wherein the material of the planarization layer comprises one or more of polysilicon, amorphous silicon, silicon oxide, silicon nitride, and amorphous carbon.
17. The method of forming a semiconductor structure of claim 1, wherein the process of removing the sacrificial layer comprises one or both of wet etching or dry etching.
18. The method of forming a semiconductor structure of claim 1, wherein the target layer comprises a dielectric layer;
patterning the dielectric layers below the first groove, the second groove and the third groove by taking the second side wall and the flat layer as masks, and forming a plurality of interconnection grooves in the dielectric layers;
the method for forming the semiconductor structure further comprises the following steps: and forming an interconnection line in the interconnection groove.
19. The method of forming a semiconductor structure of claim 18, wherein the target layer further comprises a layer of hard mask material on the dielectric layer.
20. The method of forming a semiconductor structure of claim 19, wherein the material of the hard mask material layer comprises one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739210A (en) * 2018-07-18 2020-01-31 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
CN111180513A (en) * 2018-11-12 2020-05-19 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same
US10714343B1 (en) * 2019-02-02 2020-07-14 Semiconductor Manufacturing (Shanghai) International Corporation Semiconductor structure and method for forming same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7879728B2 (en) * 2008-01-23 2011-02-01 International Business Machines Corporation Sub-lithographic printing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739210A (en) * 2018-07-18 2020-01-31 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
CN111180513A (en) * 2018-11-12 2020-05-19 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same
US10714343B1 (en) * 2019-02-02 2020-07-14 Semiconductor Manufacturing (Shanghai) International Corporation Semiconductor structure and method for forming same

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