CN113948463B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113948463B
CN113948463B CN202010692389.6A CN202010692389A CN113948463B CN 113948463 B CN113948463 B CN 113948463B CN 202010692389 A CN202010692389 A CN 202010692389A CN 113948463 B CN113948463 B CN 113948463B
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layer
side wall
groove
sidewall
forming
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CN113948463A (en
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a core layer on the target layer; forming a first side wall on the side wall of the core layer; forming a sacrificial layer on the target layer between the adjacent first side walls along the second direction, wherein the sacrificial layer covers the first side wall side walls positioned on the first side walls and is spaced from the first side walls positioned on the second side walls; forming a filling layer on the target layer; removing the sacrificial layer to form an opening; removing at least the first side wall positioned on the first side wall to form a groove; forming a side wall structure layer which is positioned on the side wall of the groove and is filled between the side wall of the core layer and the filling layer, and enclosing the side wall structure layer positioned on the side wall of the groove into a first groove; forming a second groove, and penetrating through the first groove and a filling layer positioned between the side wall structure layers of the second side wall; removing the core layer to form a third groove; and etching the target layer below the first groove, the second groove and the third groove to form a target pattern. The embodiment of the invention is beneficial to improving the graphic precision of the target graphic.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid growth of the semiconductor integrated circuit (Integrated circuit, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in integrated circuits that are smaller, more precise, and more complex.
As integrated circuits develop, the geometry (i.e., the minimum device size that can be created using process steps) generally decreases as the functional density (i.e., the number of interconnect structures per chip) increases, which correspondingly increases the difficulty and complexity of integrated circuit fabrication.
Currently, with the continued scaling of technology nodes, how to increase the matching degree between the patterns formed on the wafer and the target patterns becomes a challenge.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the precision, the flexibility of layout design and the degree of freedom of a target pattern.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming core layers extending along a first direction and arranged at intervals along a second direction on the target layer, wherein the second direction is perpendicular to the first direction, and the opposite side walls of the adjacent core layers along the second direction are respectively a first side wall and a second side wall; forming a first side wall on the side wall of the core layer; forming a sacrificial layer on the target layer between the adjacent first side walls along the second direction, wherein the sacrificial layer covers the first side wall on the first side wall and is spaced from the first side wall on the second side wall; forming a filling layer on the core layer, the first side wall and the target layer exposed by the sacrificial layer; removing the sacrificial layer and forming an opening in the filling layer; removing the first side wall on the first side wall or removing all the first side wall; the opening and the first side wall enclose a groove; forming a side wall structure layer which is positioned on the side wall of the groove and is filled between the side wall of the core layer and the filling layer, wherein the side wall structure layer positioned on the side wall of the groove encloses a first groove; forming a second groove, and penetrating through a filling layer between the side wall of the groove and the side wall structure layer on the second side wall; removing the core layer to form a third groove; the third groove, the second groove and the first groove are isolated by a side wall structure layer; and patterning the target layer below the first groove, the second groove and the third groove by taking the side wall structure layer and the filling layer as masks to form a target pattern.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate including a target layer for forming a target pattern; the core layer is separated from the target layer, extends along a first direction and is arranged along a second direction, the second direction is perpendicular to the first direction, and the opposite side walls of the adjacent core layer along the second direction are a first side wall and a second side wall respectively; the filling layer is positioned on the target layer exposed by the core layer, a groove penetrating through part of the filling layer is formed between the adjacent core layers along the second direction, and the groove exposes the first side wall and is spaced from the second side wall; the side wall structure layer is positioned on the side wall of the groove and the side wall of the core layer, the side wall structure layer positioned on the side wall of the groove encloses a first groove, and the side wall structure layer and the filling layer are used as masks of the graphical target layer; the second groove penetrates through the filling layer between the first groove and the side wall structure layer positioned on the second side wall along the second direction, and the second groove is isolated from the first groove and the core layer by the side wall structure layer; wherein the core layer is used for occupying space for forming a third groove.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, the core layer occupies space for forming the third groove; the sacrificial layer occupies space for forming an opening, then the first side wall on the first side wall is removed or all the first side wall is removed, the opening exposes the first side wall to form a groove, after forming a side wall structure layer which is positioned on the side wall of the groove and is filled between the side wall of the core layer and the filling layer, the side wall structure layer positioned on the side wall of the groove encloses a first groove, correspondingly, the pattern and the position of the first groove are defined through the sacrificial layer and the side wall structure layer, and the first groove and the third groove are isolated by the side wall structure layer; forming a second groove, penetrating through a filling layer between the side wall of the groove and the side wall structure layer positioned on the second side wall, and correspondingly, isolating the second groove from the first groove or the third groove by the side wall structure layer; therefore, the patterns and positions of the third groove and the first groove are correspondingly defined through the core layer, the sacrificial layer and the side wall structure layer, the second groove is formed in different steps, difficulty in forming the first groove, the second groove and the third groove is reduced, process windows (for example, optical proximity effect is improved), degree of freedom and flexibility of pattern design of the first groove, the second groove and the third groove are improved, pattern precision of the first groove, the second groove and the third groove is guaranteed, the first groove, the second groove and the third groove are distributed at intervals along the second direction, adjacent grooves are isolated by the side wall structure layer, minimum design intervals (Designed minimum space) between adjacent grooves are facilitated, accordingly, after the target layers below the first groove, the second groove and the third groove are formed through patterning by taking the side wall structure layer and the filling layer as masks, pattern quality and pattern precision of the target patterns are improved, and the minimum design intervals between adjacent target patterns along the second direction are easily met.
In addition, a core layer is formed firstly, and then a first side wall is formed on the side wall of the core layer, wherein the first side wall is an Outer side wall (Outer spacer); after the core layer is removed To form the third grooves, the distance between the adjacent third grooves along the first direction is defined by the core layer, and compared with the process of forming the grooves first and then forming the inner side walls on the side walls of the grooves, in the embodiment of the invention, the distance between the adjacent third grooves along the first direction is not the sum of the distance between the adjacent core layers and twice the thickness of the first side walls, which is beneficial To realizing smaller distance between the adjacent third grooves along the first direction, and correspondingly, after the target layers below the first grooves, the second grooves and the third grooves are patterned To form the target patterns, the adjacent target patterns can realize smaller distance at the position of Head To Head (Head To Head), which is beneficial To improving the flexibility and the freedom degree of the layout design of the target patterns, and the embodiment of the invention is beneficial To saving the process cost.
Drawings
Fig. 1 to 24 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 25 to 27 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
From the background, how to improve the matching degree between the pattern formed on the wafer and the target pattern is a challenge. Specifically, in the current back-end process, the difficulty of the patterning process of the metal interconnection line is high, and the process window is small.
For example: when the pattern of the interconnection pattern is complex, the number of photomasks (masks) required by the photolithography process is large, which not only results in excessively high process cost, but also results in complex patterns of photomasks, and the optical proximity correction process of the photomasks also has higher difficulty, so that the pattern precision and the pattern quality of the formed interconnection line are poor, and even the problem that the interconnection line is short-circuited (Bridge) at the position where the interconnection line is not required to be connected is easily caused.
One approach utilizes Dummy interconnect lines (Dummy lines) to increase the window of the lithographic process and reduce mask pattern complexity. In operation of the device, the dummy interconnect lines are in a floating state, that is, the interconnect lines are not electrically connected to external circuitry or other interconnect structures. However, these floating dummy interconnect lines tend to increase parasitic capacitance of the back-end interconnect, resulting in poor performance of the formed semiconductor structure.
In order to solve the technical problems, in the method for forming a semiconductor structure provided by the embodiment of the invention, the patterns and positions of the third groove and the first groove are respectively defined correspondingly by the core layer, the sacrificial layer and the side wall structure layer, and the second groove is formed in different steps, so that the difficulty in forming the first groove, the second groove and the third groove is reduced, the process window is increased, the degree of freedom and the flexibility of pattern design of the first groove, the second groove and the third groove are improved, the pattern precision of the first groove, the second groove and the third groove is ensured, the first groove, the second groove and the third groove are distributed at intervals along the second direction, the adjacent grooves are isolated by the side wall structure layer, the minimum designed interval between the adjacent grooves is facilitated, and correspondingly, after the target layers below the first groove, the second groove and the third groove are patterned by taking the side wall structure layer and the filling layer as masks, the quality and the pattern precision of the target patterns are improved, and the minimum designed along the second direction can be satisfied.
In addition, a core layer is formed firstly, and then a first side wall is formed on the side wall of the core layer, wherein the first side wall is an outer side wall; after the core layer is removed to form the third grooves, the distance between the adjacent third grooves along the first direction is defined by the core layer, and compared with the process of forming the grooves first and then forming the inner side walls on the side walls of the grooves, in the embodiment of the invention, the distance between the adjacent third grooves along the first direction is not the sum of the distance between the adjacent core layers and twice the thickness of the first side walls, so that smaller distances between the adjacent third grooves along the first direction are facilitated, and correspondingly, after the target layers below the first grooves, the second grooves and the third grooves are patterned to form the target patterns, smaller distances between the adjacent target patterns can be realized at the positions of the head to head, so that the flexibility and the freedom degree of layout design of the target patterns are facilitated to be improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 24 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a substrate (not shown) including a target layer 110 for forming a target pattern is provided.
The substrate is used for providing a platform for the subsequent process. The target layer 110 is a film layer to be patterned to form a target pattern. The target pattern may be a gate structure, an interconnect trench in a back-end-of-line process, a fin in a fin field effect transistor (FinFET), a channel stack or a Hard Mask (HM) layer in a full-wrap Gate (GAA) transistor, and the like.
In this embodiment, the target layer 110 includes a dielectric layer 111. The dielectric layer 111 is patterned subsequently, a plurality of interconnect trenches are formed in the dielectric layer 111, and then interconnect lines are formed in the interconnect trenches, the dielectric layer 111 being used to electrically isolate adjacent interconnect lines. Accordingly, in this embodiment, the target pattern is an interconnection groove.
Thus, the dielectric layer 111 is an inter-metal dielectric (Inter Metal Dielectric, IMD) layer.
Accordingly, in this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate, and functional structures such as a resistor structure or a conductive structure may be formed in the substrate. In this embodiment, the base includes a substrate 100 and a target layer 110 on the substrate 100.
The material of the dielectric layer 111 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or the like. In this embodiment, the material of the dielectric layer 111 is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end metal interconnection structures, and further reduce the back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.
In this embodiment, the target layer 110 is a stacked structure, and the target layer 110 further includes a hard mask material layer 112 on the dielectric layer 111. In the subsequent step of patterning the target layer 110, the hard mask material layer 112 is patterned to form a hard mask layer, and then the dielectric layer 111 is patterned by using the hard mask layer as a mask, so that the process stability of the patterned dielectric layer 111 is improved, and the accuracy of pattern transfer is correspondingly improved.
The material of the hard mask material layer 112 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the hard mask material layer 112 is titanium nitride.
In a specific process, a stress buffer layer can also be disposed between the hard mask material layer 112 and the dielectric layer 111 according to actual process requirements, so as to improve adhesion between the hard mask material layer 112 and the dielectric layer 111 and reduce stress generated between the film layers. In addition, an etching stop layer can be disposed between the hard mask material layer 112 and the stress buffer layer and on the hard mask material layer 112 to define a stop position of a subsequent etching process, which is beneficial to improving the effect of the subsequent patterning process. The description of the stress buffer layer and the etch stop layer is omitted here.
Referring to fig. 2 and 3, fig. 2 is a top view, fig. 3 is a cross-sectional view of fig. 2 at an AA position, and on the target layer 110, core (mandril) layers 120 extending in a first direction (as shown in an X direction in fig. 2) and arranged at intervals in a second direction (as shown in a Y direction in fig. 2) are formed, the second direction being perpendicular to the first direction, and sidewalls opposite to the core layers 120 in the second direction are a first sidewall 11 and a second sidewall 12, respectively.
The core layer 120 is used to occupy a spatial location for forming a third groove, thereby defining the pattern and location of a subsequent third groove. Compared with the method of directly forming the third groove through the etching process, the method of forming the core layer 120 first and then removing the core layer 120 to form the third groove is beneficial to reducing the forming difficulty of the third groove and enlarging the process window for forming the third groove, so that the pattern precision of the third groove is ensured, and correspondingly, after the target layer 110 below the third groove is etched subsequently to form the target pattern, the pattern precision of the target pattern is improved. Furthermore, core layer 120 also provides support for the subsequent formation of the first sidewall.
In this embodiment, the core layer 120 is made of a material that is easy to remove, so as to reduce the difficulty in the subsequent process of removing the core layer 120. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, silicon nitride, and amorphous carbon.
As an example, the core layer 120 is a single-layer structure, and the material of the core layer 120 is amorphous silicon.
In the present embodiment, two core layers 120 are formed on the target layer 110 as an example. In other embodiments, the core layer can also be other numbers.
The opposite side walls of the adjacent core layers 120 along the second direction are a first side wall 11 and a second side wall 12, respectively, and the first side wall 11 and the second side wall 12 are spaced apart from each other.
Referring to fig. 4 and 5, fig. 4 is a top view, and fig. 5 is a cross-sectional view of fig. 4 at an AA position, a first sidewall 130 is formed on the sidewall of the core layer 120.
The subsequent steps further comprise: forming a sacrificial layer on the target layer 110 between adjacent first side walls 130 along the second direction, wherein the sacrificial layer covers the side walls of the first side walls 130 on the first side walls 11; then removing the sacrificial layer to form an opening; removing the first side wall 130 on the first side wall 11 or removing all the first side walls 130, so that the opening and the first side wall 11 form a groove; forming a side wall structure layer which is positioned on the side wall of the groove and is filled between the side wall of the core layer 120 and the filling layer, wherein the side wall structure layer positioned on the side wall of the groove encloses a first groove; a second recess is formed through the filling layer between the sidewall of the trench 30 and the sidewall structure layer of the second sidewall 12.
The core layer 120 is subsequently removed to form a third recess. Accordingly, the interval between the third recess corresponding to the core layer 120 having the second sidewall 12 and the second recess is defined by the first sidewall 130, so that by forming the first sidewall 130, it is easy to adjust the thickness of the first sidewall 130, so that the minimum designed interval between the first recess and the second recess is satisfied.
In addition, in this embodiment, the core layer 120 is formed first, and then the first side wall 130 is formed on the side wall of the core layer 120, so that the pattern and the position of the core layer 120 are used To define the pattern and the position of the subsequent third groove, the distance between the adjacent core layers 120 along the first direction is used To define the distance between the third grooves, the first side wall 130 is an Outer side wall (Outer Spacer), the distance between the adjacent third grooves along the first direction is not the sum of the distance between the adjacent core layers 120 and twice the thickness of the first side wall 130, which is beneficial To realizing smaller distance between the adjacent third grooves along the first direction, and correspondingly, after the target layer 110 under the first groove, the second groove and the third groove is patterned To form the target pattern, the adjacent target pattern can realize smaller distance at the position of the Head To Head (Head To Head, h), which is beneficial To improving the layout design flexibility and the htdegree of the target pattern.
In addition, compared with the scheme of reducing the distance of the third groove at the head-to-head position by using the cutting (Cut) process, one photomask (Mask) is needed for the cutting process, and one photomask is omitted correspondingly, so that the embodiment of the invention is beneficial to saving the process cost.
In this embodiment, the head-to-head position refers to: adjacent ones of the film layers are opposite in the extending direction along the film layers or the grooves, or adjacent ones of the grooves are opposite.
The subsequent processes of forming the sacrificial layer and the filling layer include etching processes, and for this purpose, the material of the first sidewall 130 is selected as follows: the first sidewall 130 has a high etching selectivity with respect to the materials of the core layer 120, the sacrificial layer, and the filler layer. The material of the first sidewall 130 includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride and titanium oxide.
In this embodiment, the material of the first sidewall 130 is silicon nitride.
In this embodiment, the step of forming the first sidewall 130 includes: conformally covering a first sidewall film (not shown) over the core layer 120 and target layer 110; and removing the first sidewall films on the top surface of the target layer 110 and the top surface of the core layer 120, and reserving the first sidewall film on the sidewall of the core layer 120 as the first sidewall 130.
Specifically, the first sidewall film is formed using an atomic layer deposition (Atomic Layer Deposition, ALD) process. The first side wall film formed by adopting the atomic layer deposition process has good thickness uniformity and can have good step coverage capability.
Accordingly, since the first sidewall film conformally covers the top surface of the target layer 110, the top surface of the core layer 120, and the sidewalls, in this embodiment, the first sidewall film on the top surfaces of the target layer 110 and the core layer 120 can be removed by using an anisotropic maskless etching process, so that a photomask is not required in the step of forming the first sidewall 130, which is beneficial to reducing the process cost. Specifically, the anisotropic dry etching process is adopted to perform the anisotropic maskless etching process, which is beneficial to ensuring that the side wall films on the top surfaces of the target layer 110 and the core layer 120 are completely removed, and simultaneously, the damage to other film structures is smaller, and is beneficial to reducing the transverse etching of the side wall films on the side wall of the core layer 120.
Referring to fig. 6 and 7, fig. 6 is a top view, fig. 7 is a cross-sectional view of fig. 6 at the AA position, and a sacrificial layer 140 is formed on the target layer 110 between adjacent first sidewalls 130 along the second direction, wherein the sacrificial layer 140 covers the sidewalls of the first sidewalls 130 on the first sidewalls 11 and is spaced apart from the first sidewalls 130 on the second sidewalls 12.
The sacrificial layer 140 is used to occupy a spatial location for forming the opening. And forming a filling layer on the target layer 110 exposed by the core layer 120, the first side wall 130 and the sacrificial layer 140, and removing the first side wall 130 on the first side wall 11 or removing all the first side walls 130, so that after the opening 10 and the first side wall 11 form a groove, the formed groove is used for providing support for the subsequently formed side wall structure layer, thereby enabling the side wall structure layer in the groove to form a first groove.
Therefore, in the embodiment of the present invention, the pattern and the position of the first groove are defined by the sacrificial layer 140 and the sidewall structure layer, and the first groove and the third groove are isolated by the sidewall structure layer.
Compared with the shape and position of the first groove defined directly by the etching process or a single film layer, the embodiment of the invention defines the pattern and position of the first groove by the sacrificial layer 140 and the sidewall structure layer, and in the step of forming the sacrificial layer 140, the critical dimension of the sacrificial layer 140 is larger than the critical dimension (for example, the dimension along the first direction and the second direction) of the subsequent first groove, which is beneficial to reducing the process difficulty of forming the sacrificial layer 140, for example: the difficulty of the photoetching process for forming the sacrificial layer 140 is reduced, the tolerance of the photoetching process for forming the sacrificial layer 140 is improved, and further, the pattern quality and the pattern precision of the sacrificial layer 140 are higher, and correspondingly, the pattern quality and the pattern precision of the subsequently formed first groove are also higher.
In this embodiment, the sacrificial layer 140 covers the sidewall of the first sidewall 130 on the first sidewall 11 and is spaced apart from the first sidewall 130 on the second sidewall 12, so that, along the second direction, there is a remaining space between the sacrificial layer 140 and the first sidewall 130 on the second sidewall 12 for filling the subsequent filling layer.
The material of the sacrificial layer 140 is different from the material of the core layer 120. The material of the sacrificial layer 140 and the core layer 120 has an etching selectivity, so that the core layer 120 can remain in the subsequent step of removing the sacrificial layer 140. The material of the sacrificial layer 140 includes one or more of an organic planarization material, silicon oxide, and amorphous carbon. Among them, organic planarization materials include BARC (Bottom Anti-reflective coating), SOC (spin-on carbon), and the like. In this embodiment, the material of the sacrificial layer 140 is spin-on carbon. The spin-on carbon has good filling performance, and the spin-on carbon material is easy to etch, which is beneficial to reducing the difficulty of forming the sacrificial layer 140.
In this embodiment, in the step of forming the sacrificial layer 140, the top surface of the sacrificial layer 140 is higher than the top surface of the core layer 120. The process of forming the sacrificial layer 140 includes the steps of forming a planarization layer covering the first sidewall 130 and the core layer 120 and patterning the planarization layer, and by making the top surface of the sacrificial layer 140 higher than the top surface of the core layer 120, the process of removing the planarization layer higher than the top surface of the core layer 120 to make the top surface of the sacrificial layer 140 flush with the top surface of the core layer 120 is omitted, and the process of removing the planarization layer higher than the top surface of the core layer 120 is more difficult, thereby being beneficial to reducing the process difficulty of forming the sacrificial layer 140.
In this embodiment, the sacrificial layer 140 also covers the top surface of the first sidewall 130 on the first sidewall 11.
Accordingly, in the present embodiment, the step of forming the sacrificial layer 140 includes: forming a planarization layer (not shown) on the target layer 110 to cover the core layer 120 and the first sidewall 130; the planarization layer is patterned, and a portion of the planarization layer covering the sidewalls of the first sidewall 130 on the first sidewall 11 remains on the portion of the target layer 110 between the adjacent first sidewalls 130 along the second direction as the sacrificial layer 140.
In this embodiment, a spin coating process is used to form the planarization layer. The spin coating process is simple to operate and low in process cost.
In this embodiment, an anisotropic dry etching process is used to pattern the planarization layer.
In other embodiments, the top surface of the sacrificial layer can also be flush with the top surface of the core layer. Accordingly, the step of forming the sacrificial layer includes: forming a planarization layer on the target layer to cover the core layer and the first sidewall; patterning the flat layer, reserving a part of the flat layer which is positioned between the adjacent first side walls along the second direction and covers the first side wall on the first side wall; and removing the flat layer higher than the top surface of the core layer to form the sacrificial layer.
Alternatively, the step of forming the sacrificial layer includes: forming a planarization layer on the target layer to cover the core layer and the first sidewall; removing the flat layer above the top surface of the core layer; and after removing the flat layer higher than the top surface of the core layer, patterning the flat layer, and reserving a part of the flat layer which is positioned between the adjacent first side walls along the second direction and covers the first side wall positioned on the first side wall as a sacrificial layer.
Referring to fig. 8 to 10, a filling layer 160 is formed on the core layer 120, the first sidewall 130, and the target layer 110 where the sacrificial layer 140 is exposed.
The filling layer 160 is used to mask the subsequent sidewall structure layer as a mask for the subsequent patterned target layer 110.
The filling layer 160 is made of a material having etching selectivity to the materials of the core layer 120, the sacrificial layer 140 and the first sidewall 130. The material of the filling layer 160 includes spin-on silicon oxide, metal oxide (e.g., titanium oxide), polysilicon, and amorphous silicon. In this embodiment, the material of the filling layer 160 is spin-on silicon oxide.
In this embodiment, the step of forming the filling layer 160 includes:
as shown in fig. 8, a filler material layer 150 covering the core layer 120 and the sacrificial layer 140 is formed on the target layer 110.
The process of forming the filler material layer 150 includes one or more of an atomic layer deposition process, a chemical vapor deposition process, and a spin-on process. As an example, the filler material layer 150 is formed using a spin-coating process. The spin coating process is simple to operate and low in process cost, and is beneficial to improving the flatness of the top surface of the filling material layer 150.
As shown in fig. 9 and 10, fig. 9 is a top view, fig. 10 is a cross-sectional view of fig. 9 at the AA position, the filler material layer 150 is removed above the top surface of the core layer 120, and the remaining filler material layer 150 is used as the filler layer 160.
In this embodiment, a dry etching process is used, for example: an anisotropic dry etching process removes the filler material layer 150 above the top surface of the core layer 120.
Referring to fig. 11 to 12, fig. 11 is a top view, fig. 12 is a cross-sectional view of fig. 11 at the AA position, the sacrificial layer 140 is removed, and an opening 10 is formed in the filling layer 160.
The method for forming the semiconductor structure further comprises the following steps: the first side wall 130 on the first side wall 11 is removed or all of the first side wall 130 is removed. The opening 10 is configured to form a trench with the first sidewall 11 after removing the first sidewall 130 on the first sidewall 11 or removing all the first sidewall 130.
In this embodiment, the sacrificial layer 140 further covers the top surface of the first sidewall 130 on the first sidewall 11. Therefore, the sacrificial layer 140 is removed first, exposing the first sidewall 130 on the first sidewall 11, and then removing the first sidewall 130 on the first sidewall 11 or removing all the first sidewall 130.
The process of removing the sacrificial layer 140 includes one or both of wet etching and dry etching.
In this embodiment, the sacrificial layer 140 is removed by a dry etching process. Specifically, the material of the sacrificial layer 140 is spin-coated carbon, and the sacrificial layer 140 is removed by an ashing process. As an example, the sacrificial layer 140 is removed by using oxygen plasma, and the process of removing the sacrificial layer 140 is simple, has low difficulty, and has little influence on other film layers. In other embodiments, other suitable processes can be selected to remove the sacrificial layer, depending on the material of the actual sacrificial layer.
In other embodiments, when the sacrificial layer exposes the top surface of the first sidewall, the sequence of removing the sacrificial layer, removing the first sidewall on the first sidewall or removing all the first sidewall can be adjusted according to the actual process requirement.
Referring to fig. 13 to 14, fig. 13 is a top view, and fig. 14 is a cross-sectional view of fig. 13 at the AA position, removing the first sidewall 130 on the first sidewall 11 or removing all the first sidewall 130.
After the first side wall 130 on the first side wall 11 is removed or all the first side walls 130 are removed, the opening 10 and the first side wall 11 enclose a trench 30.
The sidewalls of trench 30 are used to provide support for the formation of the sidewall structure layer. Accordingly, the trench 30 and the sidewall structure layer located on the sidewall of the trench 30 are used to define the pattern and the position of the first recess.
By removing at least the first sidewall 130 located on the first sidewall 11, the first sidewall 11 of the core layer 120 is exposed, so that after a sidewall structure layer is formed on the sidewall of the trench 30, the sidewall structure layer located on the sidewall of the trench 30 encloses a first groove, the interval between the first groove and the first sidewall 11 is the thickness of the sidewall structure layer, and correspondingly, the interval between the third groove and the first groove can be the thickness of the sidewall structure layer, thereby being beneficial to enabling the minimum interval between the third groove and the first groove to be met.
In this embodiment, all of the first side walls 130 are removed, so as to form the first gaps 20 exposing the side walls of the core layer 120. The first gap 20 in the first side wall 11 communicates with the opening 10 and forms a trench 30 with the opening 10.
The process of removing all of the first sidewall 130 includes one or both of dry etching and wet etching. In this embodiment, the first side wall 130 is removed by a wet etching process, which is easy to achieve a higher etching selectivity, and is favorable for removing the first side wall 130 cleanly, and simple to operate. Specifically, the material of the first sidewall 130 is silicon nitride, and the etching solution of the wet etching process is a hot phosphoric acid solution.
Referring to fig. 15 and 16, fig. 15 is a top view, and fig. 16 is a cross-sectional view of fig. 15 at the AA position, forming a sidewall structure layer 170 on the sidewall of the trench 30, and filling the sidewall structure layer 170 between the sidewall of the core layer 120 and the filling layer 160, where the sidewall structure layer 170 on the sidewall of the trench 30 encloses the first groove 101.
The first groove 101 is used to define the pattern and position of the target pattern.
The sidewall structure layer 170 is used to mask the fill layer 160 to be used as a mask for patterning the target layer 110.
In this embodiment, the sacrificial layer 140 is configured to occupy space for forming the opening 10, and then remove the first sidewall 130 on the first sidewall 11 or remove all of the first sidewall 130, so that the opening 10 exposes the first sidewall 11 to form the trench 30, and after forming the sidewall structure layer 170, the sidewall structure layer 170 on the sidewall of the trench 30 encloses the first groove 101, and accordingly, the pattern and the position of the first groove 101 are defined by the sacrificial layer 140 and the sidewall structure layer 170.
In addition, the first groove 101 is isolated from the subsequent third groove by the side wall structure layer 170, and the first groove 101 is also isolated from the subsequent second groove by the side wall structure layer 170, so that the minimum design interval between the adjacent grooves is realized.
In this embodiment, since all the first sidewalls 130 are removed, a second sidewall is formed on the sidewalls of the trench 30 and fills the first gap 20, and the second sidewall is used as the sidewall structure layer 170. Accordingly, the sidewall structure layer 170 is a single layer structure.
In this embodiment, the thickness of the second sidewall located on the sidewall of the trench 30 is greater than or equal to 0.5 times the thickness of the first sidewall 130 along the direction parallel to the substrate. The thickness of the second sidewall is greater than or equal to 0.5 times the thickness of the first sidewall 130, thereby ensuring that the second sidewall can fill the first gap 20 between the core layer 120 and the filler layer 160.
In this embodiment, the thickness of the second sidewall is the same as the thickness of the first sidewall 130 along the direction parallel to the substrate, and accordingly, after the second groove and the third groove are formed subsequently, the intervals between two adjacent grooves are the same along the second direction, and after the target layer 110 under the first groove 101, the second groove and the third groove is patterned to form the target pattern, the intervals between the target patterns are the same along the second direction, so that the uniformity of the intervals between the target patterns is improved.
In a specific implementation, the thickness of the second side wall can also be different from the thickness of the first side wall 130, so that the interval between two adjacent grooves is different by adjusting the thicknesses of the second side wall and the first side wall 130 according to actual requirements, and the design flexibility and the degree of freedom of the interval between the target patterns are improved.
In this embodiment, the second side wall is made of a material having etching selectivity to the core layer 120, the target layer 110 and the sacrificial layer 140, and the material of the second side wall includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon.
The material of the second sidewall is the same as or different from the material of the first sidewall 130.
In this embodiment, the step of forming the second sidewall includes: forming a second sidewall film (not shown) on the top surfaces of the filling layer 160 and the core layer 120, the sidewalls and bottom of the trench 30, and the first gap 20; and removing the second sidewall films on the top surfaces of the filling layer 160 and the core layer 120 and the bottom of the trench 30 to form a second sidewall.
In this embodiment, the process of forming the second sidewall film includes an atomic layer deposition process.
In this embodiment, an anisotropic dry etching process is used to remove the second sidewall films on the top surfaces of the filling layer 160 and the core layer 120 and the bottom of the trench 30.
Referring to fig. 17 and 18, fig. 17 is a top view, fig. 18 is a cross-sectional view of fig. 17 at the AA position, forming a second recess 102, extending through the filling layer 160 between the first recess 101 and the sidewall structure layer 170 of the second sidewall 12. Specifically, the second recess 102 extends through the fill layer 160 between the sidewall of the trench 30 and the sidewall structure layer 170 of the second sidewall 12.
The second recess 102 is used to define the pattern and location of the subsequent target pattern.
In this embodiment, in the step of forming the second groove 102, since the material of the filling layer 160 and the material of the sidewall structure layer 170 have a higher etching selectivity ratio, even if the mask layer used to form the second groove 102 exposes a portion of the sidewall structure layer 170, the probability of the sidewall structure layer 170 being erroneously etched is low, so that the etching process of the second groove 102 can implement self-alignment according to the position of the sidewall structure layer 170, correspondingly increases the process window for forming the second groove 102, and enables the second groove 102 and the first groove 101, and the second groove 102 and the core layer 120 to be separated by the sidewall structure layer 170, which is correspondingly beneficial to implementing the minimum design interval between adjacent grooves.
In this embodiment, an etching process (e.g., dry etching) is used to etch the filling layer 160 between the first recess 101 and the sidewall structure layer 170 of the second sidewall 12, so as to form the second recess 102.
In this embodiment, since the filling layer 160 and the sidewall structure layer 170 have a higher etching selectivity, in the step of etching the filling layer 160 between the first groove 101 and the sidewall structure layer 170 located on the second sidewall 12, the etching rate of the sidewall structure layer 170 is low, so that the sidewall structure layer 170 located on the sidewall of the trench 30 and the sidewall structure layer 170 located on the second sidewall 12 can play a role in defining the etching stop position in the second direction, which is beneficial to reducing the difficulty of forming the second groove 102, increasing the process window for forming the second groove 102, and further improving the pattern precision and the pattern quality of the second groove 102. Accordingly, the pattern precision and pattern quality of the target pattern formed later are also high.
Referring to fig. 19 and 20, fig. 19 is a top view, fig. 20 is a cross-sectional view of fig. 19 at AA, and the core layer 120 is removed to form a third recess 103; the third groove 103, the second groove 102 and the first groove 101 are isolated by a side wall structure layer 170.
The embodiment of the invention defines the pattern and the position of the third groove 103 and the first groove 101 through the core layer 120, the sacrificial layer 140 and the side wall structure layer 170, and forms the second groove 102 in different steps, which is beneficial to reducing the difficulty of forming the first groove 101, the second groove 102 and the third groove 103, increasing the process window (for example, improving the optical proximity effect), improving the degree of freedom and flexibility of the pattern design of the first groove 101, the second groove 102 and the third groove 103, ensuring the pattern precision of the first groove 101, the second groove 102 and the third groove 103, arranging the first groove 101, the second groove 102 and the third groove 103 at intervals along the second direction (as shown in the Y direction in fig. 19), separating the adjacent grooves by the side wall structure layer 170, and realizing the minimum design interval between the adjacent grooves, and correspondingly, forming the target pattern under the first groove 101, the second groove 102 and the third groove 103 by using the side wall structure layer 170 and the filling layer 160 as masks, and improving the target pattern precision along the minimum design interval between the target pattern and the second pattern.
In addition, in the embodiment of the present invention, the core layer 120 is formed first, and then the first side wall 130 is formed on the side wall of the core layer 120, where the first side wall 130 is an Outer side wall (Outer space), and the distance between the third grooves 103 adjacent along the first direction is defined by the core layer 120, so that it is beneficial to implementing a smaller distance between the third grooves 103 adjacent along the first direction, and correspondingly, after the target layer 110 under the first groove 101, the second groove 102 and the third groove 103 is patterned to form the target pattern, the adjacent target pattern can implement a smaller distance at the head-to-head position, which is beneficial to improving the flexibility and the degree of freedom of layout design of the target pattern, and in addition, the embodiment of the present invention is beneficial to saving the process cost.
The process of removing the core layer 120 includes one or both of wet etching and dry etching.
As an example, the core layer 120 is removed using a wet etching process. In this embodiment, the etching solution of the wet etching process includes TMAH solution (tetramethylammonium hydroxide solution), SC1 solution or SC2 solution. Wherein the SC1 solution refers to NH 4 OH and H 2 O 2 Is a mixture of (3)Solution, SC2 solution refers to HCl and H 2 O 2 Is a mixed solution of (a) and (b).
Referring to fig. 21 and 22, fig. 21 is a top view, fig. 22 is a cross-sectional view of fig. 21 at the AA position, and the first recess 101, the second recess 102 and the target layer 110 under the third recess 103 are patterned with the sidewall structure layer 170 and the filling layer 160 as masks, so as to form a target pattern.
As can be seen from the foregoing, the degree of freedom and flexibility of the pattern design of the first groove 101, the second groove 102 and the third groove 103 are high, so that the pattern precision of the first groove 101, the second groove 102 and the third groove 103 is guaranteed, and it is beneficial to achieve the minimum design interval between adjacent grooves, accordingly, after the target layer 110 under the first groove 101, the second groove 102 and the third groove 103 is patterned, the pattern quality and the pattern precision of the target pattern are improved, and the minimum design interval is easily achieved between adjacent target patterns along the second direction. Furthermore, the present invention advantageously enables adjacent target patterns to achieve smaller distances at head-to-head locations.
In this embodiment, the target layer 110 includes a dielectric layer 111, so the interconnect trench 40 is formed by patterning the target layer 110 under the first recess 101, the second recess 102, and the third recess 103 using the sidewall structure layer 170 and the filling layer 160 as masks. Accordingly, the target pattern is an interconnect trench 40.
The interconnect trenches 40 are used to provide space for forming interconnect lines in a back-end-of-line process.
Specifically, in this embodiment, the sidewall structure layer 170 and the filling layer 160 are used as masks, and the hard mask material layer 112 under the first groove 101, the second groove 102 and the third groove 103 is patterned to form a hard mask layer 175; the dielectric layer 111 is patterned using the hard mask layer 175 as a mask to form the interconnect trench 40.
Referring to fig. 23 and 24 in combination, fig. 23 is a top view, fig. 24 is a cross-sectional view of fig. 23 at an AA position, and in this embodiment, the method for forming a semiconductor structure further includes: an interconnection line 180 is formed in the interconnection groove 40.
The interconnection groove 40 formed in the embodiment can achieve a smaller distance at the head-to-head position, and accordingly, the interconnection line 180 can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the connection capability of the interconnection line 180 at the head-to-head position and improving the degree of freedom and flexibility of layout design of the interconnection line 180; moreover, the spacing between adjacent interconnect trenches 40 in the second direction is easy to satisfy the design minimum spacing, and the pattern accuracy of the interconnect trenches 40 is high, which is correspondingly advantageous to make the spacing between the interconnect lines 180 in the second direction satisfy the design minimum spacing, and to improve the pattern accuracy of the interconnect lines 180, thereby improving the performance of the semiconductor structure.
Interconnect 180 is used to make electrical connection of the semiconductor structure to external circuitry or other interconnect structures.
In this embodiment, the material of the interconnect 180 is copper. In other embodiments, the interconnect material can also be a conductive material such as cobalt, tungsten, aluminum, etc.
In this embodiment, in the step of interconnecting the wires 180, the filling layer 160, the sidewall structure layer 170 and the hard mask layer 175 are also removed.
Fig. 25 to 27 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention. The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that:
referring to fig. 25, the first sidewall 130a on the first sidewall 11a is removed, forming a second gap (not shown) exposing the first sidewall 11 a; the second gap communicates with the opening (not shown) and forms the groove 30a with the opening.
In this embodiment, after the sacrificial layer is removed, the first sidewall 130a on the first sidewall 11a is removed. In the step of removing the first sidewall 130a located on the first sidewall 11a, the first sidewall 130a exposed by the opening sidewall is removed, which is beneficial to reducing the difficulty of the process of removing the first sidewall 130a located on the first sidewall 11 a.
Accordingly, in the present embodiment, the process of removing the first sidewall 130a exposed by the opening sidewall includes an isotropic dry etching process. The isotropic dry etching process has the characteristic of isotropic etching, so that the first sidewall 130a exposed by the sidewall of the opening can be removed, the etching amount of the first sidewall 130a between the filling layer 160a and the first core layer 120a is small, and in addition, the process controllability and the etching precision of the dry etching process are high, so that damage to other film layers is reduced.
Referring to fig. 26, a sidewall structure layer 170a is formed on the sidewall of the trench 30a and filled between the sidewall of the core layer 120a and the filling layer 160a, and the sidewall structure layer 170a on the sidewall of the trench 30a encloses the first groove 101a.
In this embodiment, a second sidewall 165a is formed on the sidewall of the trench 30a, and the second sidewall 165a and the first sidewall 130a form the sidewall structure layer 170a.
Therefore, in this embodiment, the second sidewall 165a encloses the first groove 101a.
Referring to fig. 27, a second recess 102a is formed through the fill layer 160a between the sidewalls of the trench 30a and the sidewall structure layer 170a of the second sidewall 12 a.
In this embodiment, after the second groove 102a is formed, the second groove 102a is isolated from the first groove 101a by the second sidewall 165a, the second groove 102a is isolated from the core layer 120a by the first sidewall 130a, and correspondingly, after the core layer 120a is removed to form the third groove, the second groove 102a is isolated from the third groove by the first sidewall 130 a.
The subsequent steps are the same as those of the previous embodiment, and the present embodiment is not described herein. For a specific description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and no further description is given here.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 17 and 18, fig. 17 is a top view and fig. 18 is a cross-sectional view of fig. 17 at AA showing a schematic structural view of an embodiment of a semiconductor structure according to the present invention.
The semiconductor structure includes: a substrate including a target layer 110 for forming a target pattern; a core layer 120, which is separated from the target layer 110, extends along a first direction (as shown in an X direction in fig. 17) and is arranged along a second direction (as shown in a Y direction in fig. 17), wherein the second direction is perpendicular to the first direction, and opposite side walls of adjacent core layers 120 along the second direction are a first side wall 11 and a second side wall 12, respectively; the filling layer 160 is located on the target layer 110 exposed by the core layer 120, and a groove (not labeled) penetrating through a part of the filling layer 160 is formed between adjacent core layers 120 along the second direction, wherein the groove exposes the first sidewall 11 and is spaced from the second sidewall 12; the sidewall structure layer 170 is located on the sidewall of the trench and the sidewall of the core layer 120, the sidewall structure layer 170 located on the sidewall of the trench encloses the first groove 101, and the sidewall structure layer 170 and the filling layer 160 are used as masks of the patterned target layer 110; the second groove 102 penetrates through the filling layer 160 between the first groove 101 and the side wall structure layer 170 of the second side wall 12 along the second direction, and the second groove 102 is isolated from the first groove 101 and the core layer 120 by the side wall structure layer 170; wherein the core layer 120 is used to occupy space for forming the third recess.
The core layer 120 occupies space for forming a third groove, and the core layer 120 correspondingly defines the pattern and the position of the third groove; the pattern and the position of the first groove 101 are defined through the groove and the side wall structure layer 170, and the first groove 101 and the third groove are isolated by the side wall structure layer 170; the second groove 102 penetrates through the filling layer 160 between the first groove 101 and the side wall structure layer 170 of the second side wall 12, and correspondingly, the second groove 102 is isolated from the first groove 101 or the third groove by the side wall structure layer 170; therefore, the patterns and positions of the third groove and the first groove 101 are correspondingly defined through the core layer 120 and the grooves and the side wall structure layers 170, which are beneficial to reducing the forming difficulty of the first groove 101, the second groove 102 and the third groove and increasing the process window (for example, improving the optical proximity effect), so that the degree of freedom and flexibility of the pattern design of the first groove 101, the second groove 102 and the third groove are improved, the pattern precision of the first groove 101, the second groove 102 and the third groove is ensured, the first groove 101, the second groove 102 and the third groove are distributed at intervals along the second direction, the adjacent grooves are isolated by the side wall structure layers 170, and the minimum design interval between the adjacent grooves is beneficial to being realized.
Accordingly, the sidewall structure layer 170 and the filling layer 160 are used as masks to pattern the target layer 110 under the first groove 101, the second groove 102 and the third groove, after forming the target pattern, the pattern quality and the pattern precision of the target pattern are improved, and the adjacent target patterns along the second direction are easy to realize to meet the minimum design interval.
In addition, in the embodiment of the present invention, the sidewall structure layer 170 is located on the Outer sidewall of the core layer 120, and the sidewall structure layer 170 located on the Outer sidewall of the core layer 120 is an Outer sidewall (Outer spacer); after the core layer 120 is removed To form the third grooves, the distance between the third grooves adjacent in the first direction is defined by the core layer 120, which is advantageous To achieve a smaller distance between the third grooves adjacent in the first direction, and accordingly, after the first grooves 101, the second grooves 102 and the target layer 110 under the third grooves are patterned To form the target pattern, the adjacent target patterns can achieve a smaller distance at the Head-To-Head (Head To Head) position, which is advantageous To improve the flexibility and the degree of freedom of layout design of the target pattern.
The target layer 110 is a film layer to be patterned to form a target pattern. The target pattern may be a pattern of a gate structure, an interconnect trench in a back-end-of-line process, a fin in a fin field effect transistor (FinFET), a channel stack or a Hard Mask (HM) layer in a fully-surrounding Gate (GAA) transistor, etc.
In this embodiment, the target layer 110 includes a dielectric layer 111. The dielectric layer 111 is patterned subsequently, a plurality of interconnect trenches are formed in the dielectric layer 111, and then interconnect lines are formed in the interconnect trenches, the dielectric layer 111 being used to electrically isolate adjacent interconnect lines. Thus, the dielectric layer 111 is an IMD layer. Accordingly, in this embodiment, the target pattern is an interconnection groove.
Accordingly, in this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate, and functional structures such as a resistor structure or a conductive structure may be formed in the substrate. In this embodiment, the base includes a substrate 100 and a target layer 110 on the substrate 100.
In this embodiment, the material of the dielectric layer 111 is an ultra-low k dielectric material.
In this embodiment, the target layer 110 is a stacked structure, and the target layer 110 further includes a hard mask material layer 112 on the dielectric layer 111. In the subsequent step of patterning the target layer 110, the hard mask material layer 112 is patterned to form a hard mask layer, and then the dielectric layer 111 is patterned by using the hard mask layer as a mask, so that the process stability of the patterned dielectric layer 111 is improved, and the accuracy of pattern transfer is correspondingly improved.
As an example, the material of the hard mask material layer 112 is titanium nitride.
The core layer 120 is used to occupy a spatial location for forming a third groove, thereby defining the pattern and location of a subsequent third groove. Compared with the method of directly forming the third groove through the etching process, the method of forming the core layer 120 first and then removing the core layer 120 to form the third groove is beneficial to reducing the forming difficulty of the third groove and enlarging the process window for forming the third groove, so that the pattern precision of the third groove is ensured, and correspondingly, after the target layer 110 below the third groove is etched subsequently to form the target pattern, the pattern precision of the target pattern is improved.
In this embodiment, the core layer 120 is made of a material that is easy to remove, so as to reduce the difficulty in the subsequent process of removing the core layer 120. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, silicon nitride, and amorphous carbon.
As an example, the core layer 120 is a single-layer structure, and the material of the core layer 120 is amorphous silicon.
The filler layer 160 is used to mask the sidewall structure layer 170 as a mask for patterning the target layer 110.
The filling layer 160 is made of a material having etching selectivity with the materials of the core layer 120 and the sidewall structure layer 170. The material of the filling layer 160 includes spin-on silicon oxide, metal oxide (e.g., titanium oxide), polysilicon, and amorphous silicon. In this embodiment, the material of the filling layer 160 is spin-on silicon oxide.
The sidewalls of the trench are used to provide support for the formation of the sidewall structure layer 170. Accordingly, the trench and the sidewall structure layer 170 located at the trench sidewall are used to define the pattern and location of the first recess 101.
The first groove 101 is used to define the pattern and position of the target pattern.
The sidewall structure layer 170 is used to act as a mask for patterning the target layer 110 in conjunction with the filler layer 160.
In addition, the first groove 101 is isolated from the subsequent third groove by the side wall structure layer 170, and the first groove 101 is also isolated from the second groove 102 by the side wall structure layer 170, so that the minimum design interval between the adjacent grooves is realized.
In this embodiment, the sidewall structure layer 170 is a single layer structure, the sidewall structure layer 170 is a second sidewall, and the first groove 101 is correspondingly surrounded by the second sidewall located on the sidewall of the trench.
In this embodiment, the second side wall is made of a material having etching selectivity to the core layer 120 and the target layer 110, and the material of the second side wall includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide and amorphous silicon.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Fig. 27 is a schematic view of another embodiment of a semiconductor structure of the present invention. The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: the sidewall structure layer 170a includes a first sidewall 130a located between the sidewall of the core layer 120a and the filler layer 160a, and a second sidewall 165a located on the sidewall of the trench (not labeled); the first groove 101 is surrounded by the second side wall 165 a.
The material of the first sidewall 130a includes one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide. The second side wall 165a may be the same or different from the first side wall 130a.
In the second direction, the second recess 102a extends through the first recess 101a and the filler layer 160a between the first side wall 130a of the second side wall 12 a. In the second direction, the second sidewall 165a is exposed from one sidewall of the second groove 102a, and the first sidewall 130a located on the second sidewall 12a is exposed from the other sidewall.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a target layer for forming a target pattern;
forming core layers extending along a first direction and arranged at intervals along a second direction on the target layer, wherein the second direction is perpendicular to the first direction, and the opposite side walls of the adjacent core layers along the second direction are respectively a first side wall and a second side wall;
forming a first side wall on the side wall of the core layer;
forming a sacrificial layer on the target layer between the adjacent first side walls along the second direction, wherein the sacrificial layer covers the first side wall on the first side wall and is spaced from the first side wall on the second side wall;
forming a filling layer on the core layer, the first side wall and the target layer exposed by the sacrificial layer;
removing the sacrificial layer and forming an opening in the filling layer;
removing the first side wall on the first side wall or removing all the first side wall; the opening and the first side wall enclose a groove;
Forming a side wall structure layer which is positioned on the side wall of the groove and is filled between the side wall of the core layer and the filling layer, wherein the side wall structure layer positioned on the side wall of the groove encloses a first groove;
forming a second groove, and penetrating through a filling layer between the side wall of the groove and the side wall structure layer on the second side wall;
removing the core layer to form a third groove; the third groove, the second groove and the first groove are isolated by a side wall structure layer;
and patterning the target layer below the first groove, the second groove and the third groove by taking the side wall structure layer and the filling layer as masks to form a target pattern.
2. The method of claim 1, wherein removing all of said first sidewall forms a first gap exposing sidewalls of said core layer;
the first gap positioned on the first side wall is communicated with the opening and forms the groove with the opening;
and forming a second side wall which is positioned on the side wall of the groove and fills the first gap, wherein the second side wall is used as the side wall structure layer.
3. The method of forming a semiconductor structure of claim 1, wherein removing the first sidewall on the first sidewall forms a second gap exposing the first sidewall; the second gap is communicated with the opening and forms the groove with the opening;
And forming a second side wall on the side wall of the groove, wherein the second side wall and the first side wall form the side wall structure layer.
4. The method of forming a semiconductor structure of claim 3, wherein after removing the sacrificial layer, removing a first sidewall on the first sidewall;
and in the step of removing the first side wall on the first side wall, removing the first side wall exposed by the side wall of the opening.
5. The method of forming a semiconductor structure as claimed in claim 2 or 3, wherein the thickness of the second sidewall located on the sidewall of the trench is greater than or equal to 0.5 times the thickness of the first sidewall in a direction parallel to the substrate.
6. The method of forming a semiconductor structure as claimed in claim 2 or 3, wherein the thickness of the second sidewall located on the sidewall of the trench is the same as the thickness of the first sidewall along a direction parallel to the substrate.
7. The method of forming a semiconductor structure of claim 1, wherein a material of the sacrificial layer and a material of the core layer are different.
8. The method of forming a semiconductor structure of claim 1, wherein the material of the sacrificial layer comprises one or more of BARC, SOC, silicon oxide, and amorphous carbon.
9. The method of forming a semiconductor structure of claim 1, wherein the material of the first sidewall comprises one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide.
10. The method of forming a semiconductor structure of claim 1, wherein the process of removing the sacrificial layer comprises one or both of wet etching or dry etching.
11. The method of forming a semiconductor structure of claim 1, wherein the process of removing all of the first sidewall comprises one or both of a dry etch and a wet etch.
12. The method of forming a semiconductor structure of claim 4, wherein removing the exposed first sidewall of the opening sidewall comprises an isotropic dry etching process.
13. The method of forming a semiconductor structure of claim 1, wherein the target layer comprises a dielectric layer;
using the side wall structure layer and the filling layer as masks, patterning the dielectric layers below the first groove, the second groove and the third groove, and forming a plurality of interconnection grooves in the dielectric layers;
The method for forming the semiconductor structure further comprises the following steps: and forming an interconnection line in the interconnection groove.
14. A semiconductor structure, comprising:
a substrate including a target layer for forming a target pattern;
the core layer is separated from the target layer, extends along a first direction and is arranged along a second direction, the second direction is perpendicular to the first direction, and the opposite side walls of the adjacent core layer along the second direction are a first side wall and a second side wall respectively;
the filling layer is positioned on the target layer exposed by the core layer, a groove penetrating through part of the filling layer is formed between the adjacent core layers along the second direction, and the groove exposes the first side wall and is spaced from the second side wall;
the side wall structure layer is positioned on the side wall of the groove and the side wall of the core layer, the side wall structure layer positioned on the side wall of the groove encloses a first groove, and the side wall structure layer and the filling layer are used as masks of the graphical target layer;
the second groove penetrates through the filling layer between the first groove and the side wall structure layer positioned on the second side wall along the second direction, and the second groove is isolated from the first groove and the core layer by the side wall structure layer; wherein the core layer is used for occupying space for forming a third groove.
15. The semiconductor structure of claim 14, wherein the sidewall structure layer comprises a first sidewall between the core layer sidewall and a fill layer, and a second sidewall at the trench sidewall; the first groove is surrounded by the second side wall; the second groove penetrates through the first groove and the filling layer positioned between the first side walls of the second side walls along the second direction;
or the side wall structure layer is of a single-layer structure.
16. The semiconductor structure of claim 14, wherein the material of the fill layer comprises spin-on silicon oxide, metal oxide, polysilicon, and amorphous silicon.
17. The semiconductor structure of claim 14, wherein the target layer comprises a dielectric layer; the target pattern is an interconnection groove.
18. The semiconductor structure of claim 14, wherein the material of the core layer comprises one or more of polysilicon, amorphous silicon, silicon oxide, silicon nitride, and amorphous carbon.
19. The semiconductor structure of claim 14 wherein a material of said sidewall structure layer comprises one or more of silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium nitride, and titanium oxide.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104253027A (en) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 Duplex pattern and forming method thereof
CN107731666A (en) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 The method of Dual graphing
CN111370299A (en) * 2018-12-26 2020-07-03 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
US10714343B1 (en) * 2019-02-02 2020-07-14 Semiconductor Manufacturing (Shanghai) International Corporation Semiconductor structure and method for forming same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9406682B2 (en) * 2014-09-12 2016-08-02 International Business Machines Corporation Method and structure for preventing epi merging in embedded dynamic random access memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104253027A (en) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 Duplex pattern and forming method thereof
CN107731666A (en) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 The method of Dual graphing
CN111370299A (en) * 2018-12-26 2020-07-03 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
US10714343B1 (en) * 2019-02-02 2020-07-14 Semiconductor Manufacturing (Shanghai) International Corporation Semiconductor structure and method for forming same

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