CN114551333A - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a core layer on a substrate; carrying out ion doping on the core layer of the sacrificial region, wherein the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, the core layer doped with ions is used as the sacrificial layer, and the core layer not doped with ions is used as the anti-etching layer; forming a trench through the core layer between adjacent sacrificial regions; forming side walls on the side walls of the groove, wherein the side walls positioned on the side walls of the groove enclose a first groove; removing the sacrificial layer by adopting an etching process to form a second groove penetrating through the anti-etching layer, wherein the etching rate of the etching process to the sacrificial layer is greater than that of the anti-etching layer; and etching the target layers at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern. The embodiment of the invention is beneficial to improving the pattern precision of the target pattern and the matching degree of the target pattern and the design pattern.

Description

Method for forming semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the Integrated Circuit is developed towards smaller size, higher Circuit precision and higher Circuit complexity.

In the development of integrated circuits, as the functional density (i.e., the number of interconnect structures per chip) generally increases, the geometric size (i.e., the minimum component size that can be produced by the process steps) also decreases, which increases the difficulty and complexity of integrated circuit fabrication.

At present, with the shrinking of technology nodes, it is a challenge to improve the matching between the target pattern and the design pattern formed on the wafer.

Disclosure of Invention

The embodiment of the invention provides a method for forming a semiconductor structure, which is beneficial to improving the pattern precision of a target pattern and the matching degree of the target pattern and a design pattern.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a core layer on the substrate, the core layer including an etch-resistant region for forming an etch-resistant layer and a sacrificial region for forming a sacrificial layer; performing ion doping on the core layer of the sacrificial region, wherein the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, the core layer doped with ions in the sacrificial region is used as the sacrificial layer, and the core layer not doped with ions in the anti-etching region is used as the anti-etching layer; forming a groove penetrating through the core layer between the adjacent sacrificial regions, wherein the side wall of the groove exposes the core layer in the sacrificial regions; forming a side wall on the side wall of the groove, wherein the side wall positioned on the side wall of the groove is encircled to form a first groove; after ion doping and the first groove are formed, removing the sacrificial layer by adopting an etching process, and forming a second groove penetrating through the anti-etching layer in the anti-etching layer; wherein, the etching speed of the etching process to the sacrificial layer is greater than that to the anti-etching layer; and etching the target layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern.

Optionally, after the core layer is formed and before the trench is formed, ion doping is performed on the core layer of the sacrificial region; or after the groove is formed and before the side wall is formed, carrying out ion doping on the core layer of the sacrificial region; or after the side walls are formed and before the second grooves are formed, ion doping is performed on the core layer of the sacrificial region.

Optionally, the ions for ion doping the core layer of the sacrificial region include boron ions, phosphorus ions, arsenic ions, or argon ions.

Optionally, in the step of ion doping the core layer of the sacrificial region, the ion doping concentration in the core layer of the sacrificial region is 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter.

Optionally, an ion implantation process is used to perform ion doping on the core layer of the sacrificial region.

Optionally, the parameters of the ion implantation process include: the implantation energy is 1KeV to 100KeV, and the implantation direction forms an angle of 0 DEG to 5 DEG with the normal of the substrate surface.

Optionally, a wet etching process is used to remove the sacrificial layer.

Optionally, the etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid, nitric acid, and acetic acid.

Optionally, in a mixed solution of hydrofluoric acid, nitric acid and acetic acid adopted in the wet etching process, a molecular ratio between the nitric acid and the hydrofluoric acid is at least 2, and a molar percentage of the nitric acid is at least 14%.

Optionally, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molar percentage of the hydrofluoric acid is 0.2% to 6%, the molar percentage of the nitric acid is 14% to 28%, and the molar percentage of the acetic acid is 66% to 86%.

Optionally, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid adopted in the wet etching process, the volume ratio of the hydrofluoric acid to the acetic acid is 1:8 to 1:100, and the volume ratio of the hydrofluoric acid to the nitric acid is 1:3 to 1: 50.

Optionally, in the step of forming the core layer, a material of the core layer includes amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride or silicon oxycarbonitride.

Optionally, the step of ion doping the core layer of the sacrificial region includes: forming a shielding layer covering the etching resistant area, wherein the shielding layer exposes the sacrificial area; and performing the ion doping on the core layer by taking the shielding layer as a mask.

Optionally, the target layer is a dielectric layer; etching the dielectric layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form an interconnection groove; the method for forming the semiconductor structure further comprises the following steps: after forming the interconnection trench, forming a metal line in the interconnection trench.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming a semiconductor structure according to the embodiment of the present invention, the core layer of the sacrificial region is ion-doped, so that the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, and the sacrificial layer in the sacrificial region and the anti-etching layer in the anti-etching region are formed by ion-doping the core layer, which is not only beneficial to simplifying the process, but also beneficial to reducing the difficulty of removing the sacrificial layer and improving the process controllability of removing the sacrificial layer by using an etching process in the step of removing the sacrificial layer, wherein the etching rate of the etching process on the sacrificial layer is greater than the etching rate on the anti-etching layer, the pattern precision of the second groove is also improved, and the anti-etching layer can be retained in the step of removing the sacrificial layer, correspondingly, the effect of the anti-etching layer as a mask of the patterning target layer is guaranteed, and in the step of etching the target layers at the bottoms of the first groove and the second groove to form the target pattern, the high pattern transfer precision and the good patterning effect are favorably obtained, so that the pattern precision of the target pattern is improved, and the matching degree of the target pattern and the design pattern is improved.

Drawings

Fig. 1 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background art, it is a challenge to improve the matching between the target pattern and the design pattern formed on the wafer.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a core layer on the substrate, the core layer including an etch-resistant region for forming an etch-resistant layer and a sacrificial region for forming a sacrificial layer; performing ion doping on the core layer of the sacrificial region, wherein the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, the core layer doped with ions in the sacrificial region is used as the sacrificial layer, and the core layer not doped with ions in the anti-etching region is used as the anti-etching layer; forming a groove penetrating through the core layer between the adjacent sacrificial regions, wherein the side wall of the groove exposes the core layer in the sacrificial regions; forming a side wall on the side wall of the groove, wherein the side wall positioned on the side wall of the groove is encircled to form a first groove; after ion doping and the first groove are formed, removing the sacrificial layer by adopting an etching process, and forming a second groove penetrating through the anti-etching layer in the anti-etching layer; wherein, the etching speed of the etching process to the sacrificial layer is greater than that to the anti-etching layer; and etching the target layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern.

In the method for forming a semiconductor structure according to the embodiment of the present invention, the core layer of the sacrificial region is ion-doped, so that the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, and the sacrificial layer in the sacrificial region and the anti-etching layer in the anti-etching region are formed by ion-doping the core layer, which is not only beneficial to simplifying the process, but also beneficial to reducing the difficulty of removing the sacrificial layer and improving the process controllability of removing the sacrificial layer by using an etching process in the step of removing the sacrificial layer, wherein the etching rate of the etching process on the sacrificial layer is greater than the etching rate on the anti-etching layer, the pattern precision of the second groove is also improved, and the anti-etching layer can be retained in the step of removing the sacrificial layer, the anti-etching layer is correspondingly guaranteed to serve as a mask of the patterning target layer, and in the step of etching the target layer at the bottoms of the first groove and the second groove to form the target pattern, the high pattern transfer precision and the good patterning effect are favorably obtained, so that the pattern precision of the target pattern is improved, and the matching degree of the target pattern and the designed pattern is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 1 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 1, a substrate (not labeled) is provided, including a target layer 100 for forming a target pattern.

The substrate is used for providing a platform for subsequent process.

The target layer 100 is a film layer to be patterned to form a target pattern.

The target pattern may be a gate structure, an interconnection trench in a back-end process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, or the like.

In this embodiment, the target layer 100 is a dielectric layer. And patterning the dielectric layer, forming a plurality of interconnection grooves in the dielectric layer, and forming metal lines in the interconnection grooves, wherein the dielectric layer is used for realizing electric isolation between adjacent metal lines. Accordingly, the target pattern is an interconnect slot. The Dielectric layer is an Inter Metal Dielectric (IMD) layer. The dielectric layer is made of low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride.

In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate, and a functional structure such as a resistor structure or a conductive structure may be formed in the substrate.

In this embodiment, the substrate further includes a hard mask material layer 110 on the target layer 100, and an etch stop layer 120 on the hard mask material layer 110.

The hard mask material layer 110 is used for forming a hard mask layer after a subsequent patterning process. Specifically, after the first groove and the second groove are formed subsequently, the patterns of the first groove and the second groove can be firstly transferred to the hard mask material layer 110 to form a hard mask layer, and then the target layer 100 is etched by using the hard mask layer as a mask, so that even if the subsequent anti-etching layer and the side wall are consumed in the process of the patterning process, the target layer 100 can be continuously etched by using the hard mask layer as the mask, and the improvement of the stability and the process effect of the patterning process is facilitated.

In this embodiment, the hard mask material layer 110 is made of silicon nitride. In other embodiments, the material of the hard mask material layer may also be silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride.

The subsequent process includes a plurality of etching steps, and the etching stop layer 120 is used for defining an etching stop position in the subsequent etching process, so that the loss of the target layer 100 is reduced, the depth consistency of the etching process is improved, and the effect of the subsequent patterning process is improved.

In this embodiment, the material of the etch stop layer 120 is silicon oxide. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride, aluminum nitride, or the like.

Referring to fig. 2 and 3, fig. 2 is a top view, and fig. 3 is a cross-sectional view of fig. 2 taken along a yy cut line, a core layer (Mandrel)130 is formed on the substrate, the core layer 130 including an etch-resistant region a for forming an etch-resistant layer and a sacrificial region B for forming a sacrificial layer.

Subsequently, ion doping is performed on the core layer 130 to form the anti-etching layer and the sacrificial layer.

Specifically, in this embodiment, the core layer 130 of the sacrificial region B is used to form a sacrificial layer through subsequent ion doping, and the remaining core layer 130 of the etch-resistant region a, which is not doped with ions, is used as an etch-resistant layer.

Therefore, the regions of the etching-resistant region a and the sacrificial region B are divided according to the formation positions and patterns of the subsequent etching-resistant layer and the sacrificial layer.

In this embodiment, a part of the core layer 130 is used as the sacrificial region B, and the rest of the core layer is used as the etching-resistant region a.

In this embodiment, the number of the sacrificial regions B is plural, and the sacrificial regions B are arranged at intervals along a transverse direction (as shown in an X direction in fig. 2) and along a longitudinal direction (as shown in a Y direction in fig. 2), and the transverse direction is perpendicular to the longitudinal direction. As an example, two of the sacrificial regions B are illustrated.

The material of the core layer 130 includes amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the material of the core layer 130 is amorphous silicon.

In this embodiment, the core layer 130 is formed by a deposition process (e.g., a chemical vapor deposition process).

Referring to fig. 4 to 9, the core layer 130 of the sacrificial region B is ion-doped, and the core layer 130 of the sacrificial region B and the core layer 130 of the anti-etching region a are adapted to have different etching rates, the core layer 130 doped with ions in the sacrificial region B is used as the sacrificial layer 160, and the core layer 130 not doped with ions in the anti-etching region a is used as the anti-etching layer 150.

The subsequent steps further comprise: forming a trench penetrating the core layer 130 between the adjacent sacrificial regions B; forming a side wall on the side wall of the groove, wherein the side wall positioned on the side wall of the groove is encircled to form a first groove; and removing the sacrificial layer to form a second groove.

In this embodiment, the core layer 130 of the sacrificial region B is ion-doped, which is suitable for making the etching rates of the core layer 130 of the sacrificial region B and the core layer 130 of the anti-etching region a different, so that the sacrificial layer 160 and the anti-etching layer 150 are formed by ion-doping the core layer 130, which is not only beneficial to simplify the process, but also beneficial to making the etching rates of the sacrificial layer 160 and the anti-etching layer 150 different by ion-doping, in the subsequent step of removing the sacrificial layer 160 by using an etching process, the etching rate of the etching process on the sacrificial layer 160 is greater than the etching rate on the anti-etching layer 150, which is beneficial to reducing the difficulty of removing the sacrificial layer 160 and improving the process controllability of removing the sacrificial layer 160, the pattern precision of the second groove is also improved, and the anti-etching layer 150 can be retained in the step of removing the sacrificial layer 160, accordingly, the function of the anti-etching layer 150 as a mask for patterning the target layer 100 is ensured, and in the step of etching the target layer 100 at the bottom of the first and second grooves to form the target pattern, higher pattern transfer accuracy and better patterning effect are obtained, so that the pattern accuracy of the target pattern is improved, and the matching degree of the target pattern and the design pattern is improved.

In this embodiment, the difference between the etching rates of the core layer 130 in the sacrificial region B and the core layer 130 in the anti-etching region a means that the etching rates of the core layer 130 in the sacrificial region B and the core layer 130 in the anti-etching region a are different under the same etching process condition.

In this embodiment, the core layer 130 of the sacrificial region B and the core layer 130 of the anti-etching region a have different etching rates, so that a specific etching process is easily selected in the subsequent step, so that the etching process has a higher etching selectivity ratio between the sacrificial layer 160 and the anti-etching layer 150, thereby correspondingly reducing the difficulty of subsequently removing the sacrificial layer 160 and increasing the process window for forming the second groove.

As an example, the core layer 130 of the sacrificial region B is ion-doped after the core layer 130 is formed and before the trench is formed.

In other embodiments, the core layer of the sacrificial region may be ion-doped after the trench is formed and before the side wall is formed; or after the side wall is formed and before the second groove is formed, ion doping is performed on the core layer of the sacrificial region.

In this embodiment, the doping depth of the ion doping is the entire thickness of the core layer 130.

In this embodiment, the ions for ion doping the core layer 130 of the sacrificial region B include boron ions, phosphorus ions, arsenic ions, or argon ions. As an example, the ions that ion-dope the core layer 130 of the sacrificial region B are boron ions.

When the ions are doped in the core layer 130, the inventor finds that, when the ion doping concentration in the core layer 130 is greater than a doping concentration value, and a specific etching process is selected, the etching rate of the etching process on the material of the core layer 130 doped with the ions is far greater than the etching rate on the material of the core layer 130 not doped with the ions, and the etching rate of the etching process on the material of the core layer 130 not doped with the ions is even close to stop, so that the etching process has a higher etching selection ratio on the sacrificial layer 160 and the anti-etching layer 150, and further ensures that the process difficulty for subsequently removing the sacrificial layer 160 is low and the process window is large, and the anti-etching layer 150 can be retained in the step of removing the sacrificial layer 160.

Specifically, in this embodiment, the material of the core layer 130 is amorphous silicon, and boron ions are doped in the amorphous silicon, so that the etching rate of the amorphous silicon material can be changed, and thus the etching rates of the sacrificial layer 160 and the etch-resistant layer 150 are different.

Therefore, in the step of doping the ions into the core layer 130 of the sacrificial region B, the doping concentration of the ions in the core layer 130 of the sacrificial region B is not too small, otherwise, the difference between the etching rates of the ion-doped core layer 130 and the ion-undoped core layer 130 is not obvious, and the increase effect on the process window for subsequently removing the sacrificial layer 160 is easily reduced. For this reason, in the embodiment, in the step of ion doping the core layer 130 of the sacrificial region B, the ion doping concentration in the core layer 130 of the sacrificial region B is 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter.

As an example, the sacrificial layer 160 is doped with boron ions, and the doping concentration of the boron ions in the sacrificial layer 160 is 1.0E19 atoms per cubic centimeter.

In this embodiment, the number of the sacrificial regions B is plural, and therefore, the number of the sacrificial layers 160 is also plural. A plurality of the sacrificial layers 160 extend in the transverse direction and are arranged at intervals in the longitudinal direction.

In this embodiment, the step of ion doping the core layer 130 of the sacrificial region B includes:

as shown in fig. 4 and 5, fig. 4 is a top view, and fig. 5 is a cross-sectional view taken along yy cut line of fig. 4, a shielding layer 140 covering the etch-resistant region a is formed, and the shielding layer 140 exposes the sacrificial region B.

The shielding layer 140 is used to shield the core material layer 130 in the second area.

In this embodiment, the material of the shielding layer 140 is Spin-on carbon (SOC). In other embodiments, the material of the shielding layer may also be other organic materials, such as: BARC (Bottom Anti-reflective coating) materials, ODL (Organic Dielectric layer) materials, and the like.

As an example, the step of forming the blocking layer 140 includes: forming an initial barrier layer (not shown) on the core layer 130; forming a patterned layer (not shown) on the initial shielding layer; and patterning the initial shielding layer by using the patterning layer as a mask to form the shielding layer 140.

In this embodiment, the process of forming the initial shielding layer includes a Spin-On (Spin-On) process.

In this embodiment, the material of the patterned layer includes a photoresist, and the forming process of the patterned layer includes a photolithography process including photoresist coating, exposure, development, and the like.

In this embodiment, the process of patterning the initial shielding layer includes an anisotropic dry etching process. The anisotropic dry etching process is beneficial to improving the precision of pattern transfer.

As shown in fig. 6 and 7, fig. 6 is a top view, and fig. 7 is a cross-sectional view taken along yy cut line of fig. 6, and the ion doping is performed on the core layer 130 using the shielding layer 140 as a mask.

In this embodiment, the shielding layer 140 exposes the sacrificial region B, and thus the core layer 130 of the sacrificial region B is ion-doped.

In this embodiment, an ion implantation process is adopted to perform ion doping on the core layer 130 of the sacrificial region B. The ion implantation process is simple and easy to operate, the doping depth can meet the process requirement easily by adjusting the implantation direction and energy, and the ion doping concentration can meet the process requirement easily by adjusting the implantation dosage.

In this embodiment, the parameters of the ion implantation process include: the implantation energy is 1KeV to 100KeV, and the implantation direction forms an angle of 0 DEG to 5 DEG with the normal of the substrate surface.

The implantation energy of the ion implantation process is not too small or too large. If the implantation energy of the ion implantation process is too small, the ion implantation depth is easily insufficient, and the difference between the etched rates of the ion-doped core layer 130 and the ion-undoped core layer 130 is easily insignificant; if the implantation energy of the ion implantation process is too large, too large implantation damage is easily caused, and side effects are easily generated. For this reason, in the present embodiment, the implantation energy of the ion implantation process is 1KeV to 100 KeV.

The angle between the ion implantation direction and the normal of the substrate surface should not be too large, otherwise the risk of implanting ions into the core layer 130 of the etching-resistant region a is easily increased. For this reason, in this embodiment, the angle between the implantation direction of the ion implantation process and the normal of the substrate surface is 0 ° to 5 °.

As shown in fig. 8 and 9, fig. 8 is a top view, and fig. 9 is a cross-sectional view taken along yy cut line of fig. 8, where the shielding layer 140 is removed.

The blocking layer 140 is removed to expose the top surfaces of the anti-etching layer 150 and the sacrificial layer 160, so as to facilitate the subsequent process.

Specifically, the blocking layer 140 may be removed by one or both of an ashing process and a wet stripping process.

Referring to fig. 10 to 15, a trench 180 penetrating the core layer 130 between the adjacent sacrificial regions B is formed, and the core layer 130 in the sacrificial region B is exposed by sidewalls of the trench 180.

The side wall of the trench 180 is used for providing a supporting function for a subsequent formed side wall, and the trench 180 and the subsequent side wall jointly define the shape and the position of the first groove. Specifically, a sidewall is formed on the sidewall of the trench 180, and a first groove is defined by the sidewall located on the sidewall of the trench 180.

In this embodiment, before forming the trench 180, the core layer 130 of the sacrificial region B is ion-doped to form the sacrificial layers 160 and the anti-etching layers 150, so that the trench 180 penetrates through the anti-etching layers 150 between the adjacent sacrificial layers 160, and the side wall of the trench 180 exposes the sacrificial layers 160.

As an example, in an actual process, the trench 180 may also penetrate the core layer 130 (i.e., the sacrificial layer 160) of the sacrificial region B along a longitudinal direction for a partial width.

In this embodiment, the number of the grooves 180 is also plural, and the plural grooves 180 extend in the transverse direction and are arranged at intervals with the core layer 130 of the sacrificial region B in the longitudinal direction.

In this embodiment, the sacrificial region B located at the edge position in the longitudinal direction serves as an edge sacrificial region, and the trench 180 is also located in the core layer 130 at a side of the edge sacrificial region away from the adjacent sacrificial region B.

In this embodiment, the step of forming the trench 180 includes:

as shown in fig. 10 and 11, fig. 10 is a top view, and fig. 11 is a cross-sectional view taken along yy cut line of fig. 10, a mask layer 170 is formed on the etch-resistant layer 150 and the sacrificial layer 160, and a pattern opening 175 exposing a portion of the etch-resistant layer 150 between adjacent sacrificial layers 160 is formed in the mask layer 170.

The mask layer 170 is used as a mask for etching the etch-resistant layer 150 to form a trench.

Specifically, the mask layer 170 is formed on the etch stop layer 120.

In this embodiment, the mask layer 170 is made of spin-on carbon. For the material and the formation steps of the mask layer 170, reference may be made to the corresponding description of the blocking layer, which is not repeated herein.

In this embodiment, the mask layer 170 further exposes a portion of the width of the sacrificial layer 160 and a portion of the etch-resistant layer 150 adjacent to the sacrificial layer 160.

Referring to fig. 12 and 13, fig. 12 is a top view, and fig. 13 is a cross-sectional view taken along yy cut line of fig. 12, wherein the mask layer 170 is used as a mask to remove the etch-resistant layer 150 at the bottom of the pattern opening 175, thereby forming a trench 180.

In this embodiment, an anisotropic dry etching process (e.g., a plasma etching process) is used to remove the anti-etching layer 150 at the bottom of the pattern opening 175. The plasma etching process has better profile controllability and high etching precision, is favorable for improving the graphic precision and the profile appearance quality of the groove 180, and is also favorable for improving the etching efficiency.

In this embodiment, the pattern opening 175 further exposes a portion of the width of the sacrificial layer 160 and a portion of the anti-etching layer 150 adjacent to the sacrificial layer 160, so that during the process of removing the anti-etching layer 150 at the bottom of the pattern opening 175, a portion of the sacrificial layer 160 and a portion of the anti-etching layer 150 adjacent to the sacrificial layer 160 are also removed.

Accordingly, the trench 180 is also formed in the etch resist layer 150 adjacent to the sacrificial layer 160. Specifically, in this embodiment, the number of the grooves 180 is multiple, and the grooves 180 are arranged at intervals along the longitudinal direction.

As shown in fig. 14 and 15, fig. 14 is a top view, and fig. 15 is a cross-sectional view of fig. 14 taken along the yy cut line, and the mask layer 170 is removed.

The mask layer 170 is removed to facilitate the subsequent process. Specifically, the process for removing the mask layer 170 includes one or both of an ashing process and a wet stripping process.

Referring to fig. 16 in combination, as an example, the method for forming the semiconductor structure further includes: after the core layer 130 is formed, before the side wall is formed, a cutting groove 200 penetrating the core layer 130 of the sacrificial region B in the longitudinal direction is formed, and the cutting groove 200 transversely divides the core layer 130 of the sacrificial region B.

The cutting groove 200 transversely divides the core layer 130 of the sacrificial region B, so that after ion doping is performed to form the anti-etching layer 150 and the sacrificial layer 160, the cutting groove 200 transversely divides the sacrificial layer 160, and then in the step of forming the side wall, the side wall can also be filled in the cutting groove 200, the side wall in the cutting groove 200 is used as a dividing layer for transversely dividing the sacrificial layer 160, and further after the sacrificial layer 160 is subsequently removed to form a second groove, the dividing layer transversely divides the second groove, which is beneficial to realizing a smaller distance between adjacent second grooves.

As an example, the cutting groove 200 is formed after the trench 180 is formed and ion doping is performed, and before a sidewall is formed. Accordingly, the cutting grooves 200 penetrate the sacrificial layer 160 in the longitudinal direction, and the sacrificial layer 160 is divided in the transverse direction by the cutting grooves 200.

In other embodiments, the cutting groove may be formed after the core layer is formed and before the ion doping is performed; or, after ion doping and before forming the groove, forming the cutting groove.

Referring to fig. 17 to 18, fig. 17 is a top view, and fig. 18 is a cross-sectional view taken along yy cut line of fig. 17, wherein a sidewall 190 is formed on a sidewall of the trench 180, and the sidewall 190 located on the sidewall of the trench 180 encloses a first groove 210.

The sidewall spacers 190 are used as a partial mask for the subsequent etching of the target layer 100. In this embodiment, the sidewall 190 and the trench 180 jointly define the pattern defining the first groove 210, and in the process of forming the trench 180, the size of the trench 180 is relatively large, and the requirement on the size precision of the trench 180 is low, which is beneficial to reducing the difficulty of forming the trench 180 and increasing the process window.

The subsequent steps further comprise: the sacrificial layer 160 is removed to form a second groove. In this embodiment, before forming the second groove, the side wall 190 is formed, so that the isolation between the first groove 210 and the second groove can be realized subsequently, and the distance between the adjacent first groove 210 and the second groove satisfies the designed minimum interval; accordingly, after the target layer 100 at the bottom of the first groove 210 and the second groove is subsequently etched, it is beneficial to enable the distance between the target patterns formed in the target layer 100 to meet the minimum design interval.

In this embodiment, the side walls 190 are further filled in the cutting grooves 200, the side walls 190 in the cutting grooves 200 are used as dividing layers for dividing the sacrificial layer 160, and after the sacrificial layer 160 is correspondingly removed subsequently to form second grooves, the dividing layers are used for dividing the second grooves, which is beneficial to realizing smaller distance between the second grooves.

The material of the sidewall spacers 190 may be titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the sidewall spacers 190 are made of titanium oxide. The titanium oxide material has a higher etching selectivity than amorphous silicon or silicon nitride, the sidewall 190 can be retained in the subsequent step of removing the sacrificial layer 160, and the sidewall 190 can be used as a mask of the etching target layer 100.

In this embodiment, the step of forming the sidewall spacers 190 includes: forming a side wall material layer (not shown) on the sidewalls and the bottom of the trench 180, and the top surfaces of the etch resistant layer 150 and the sacrificial layer 160; and removing the sidewall spacer material layer located at the bottom of the trench 180 and on the top surfaces of the etch-resistant layer 150 and the sacrificial layer 160, wherein the remaining sidewall spacer material layer located on the sidewall of the trench 180 is used as the sidewall spacer 190.

In this embodiment, the sidewall material layer is formed by an atomic layer deposition process. The atomic layer deposition process has strong step coverage capability, is favorable for improving the coverage capability of the side wall material layer on the side wall of the groove 180, and is favorable for improving the thickness uniformity of the side wall material layer and accurately controlling the thickness of the side wall 190 by selecting the atomic layer deposition process.

In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to remove the spacer material layer located at the bottom of the trench 180 and the top surfaces of the anti-etching layer 150 and the sacrificial layer 160. The anisotropic dry etching process has anisotropic etching characteristics, so that the sidewall material layer on the bottom of the trench 180, the top surfaces of the etch resistant layer 150 and the sacrificial layer 160 can be removed without a mask, and the sidewall material layer on the sidewall of the trench 180 can be retained.

As an example, the thickness of the sidewall 190 is 50 to 300 angstroms, and the thickness of the sidewall 190 is smaller, so that a smaller interval is realized between the adjacent first groove 210 and the second groove 220. Wherein, the thickness of the sidewall wall 190 refers to: the side wall 190 has a dimension perpendicular to the side wall of the trench 180.

Referring to fig. 19 and 20, fig. 19 is a top view, and fig. 20 is a cross-sectional view taken along yy cut line of fig. 19, after ion doping and forming the first recess 210, an etching process is performed to remove the sacrificial layer 160 and form a second recess 220 penetrating the anti-etching layer 150 in the anti-etching layer 150; wherein, the etching process has a higher etching rate for the sacrificial layer 160 than for the anti-etching layer 150.

The second groove 220 and the first groove 210 together define a pattern of a target pattern. After the second recess 220 and the first recess 210 are formed, the sidewall spacers 190 and the remaining etch-resistant layer 150 are used as a mask for patterning the target layer 100.

In this embodiment, the number of the second grooves 220 is plural. The second grooves 220 extend along a transverse direction (as shown in the X direction in fig. 19), a plurality of the second grooves 220 are longitudinally spaced from the first grooves 210 (as shown in the Y direction in fig. 19), and the second grooves 220 are separated from the first grooves 210 by the side wall 190, which is beneficial to ensure that the designed minimum spacing between the second grooves 220 and the first grooves 210 is satisfied.

In this embodiment, the core layer 130 of the sacrificial region B is ion-doped, which is suitable for making the etching rates of the core layer 130 of the sacrificial region B (i.e. the sacrificial layer 160) and the core layer 130 of the anti-etching region a (i.e. the anti-etching layer 150) different, which is not only beneficial to simplify the process, but also makes the etching rates of the sacrificial layer 160 and the anti-etching layer 150 different by means of ion-doping, accordingly, in the step of removing the sacrificial layer 160 by using the etching process, the etching rate of the etching process on the sacrificial layer 160 is greater than the etching rate on the anti-etching layer 150, which is beneficial to reducing the difficulty of removing the sacrificial layer 160 and improving the process controllability of removing the sacrificial layer 160, the pattern precision of the second groove 220 is also improved, and the anti-etching layer 150 can be retained in the step of removing the sacrificial layer 160, correspondingly, the anti-etching layer 150 is ensured to serve as a mask for patterning the target layer 100, and in the step of etching the target layer 100 at the bottoms of the first groove 210 and the second groove 220 to form a target pattern, higher pattern transfer precision and better patterning effect are facilitated, so that the pattern precision of the target pattern is improved, and the matching degree of the target pattern and a designed pattern is improved.

In addition, in this embodiment, after the trench 180 is formed, the sidewall 190 is formed on the sidewall of the trench 180, so that the sidewall 190 on the sidewall of the trench 180 surrounds the first groove 210, and then the sacrificial layer 160 is removed to form the second groove 220, in this embodiment, the first groove 210 and the second groove 2200 are formed in different steps, which is beneficial to reducing the difficulty of forming the first groove 210 and the second groove 220 and increasing the process window (for example, improving the optical proximity effect), so that the pattern accuracy of the first groove 210 and the second groove 220 is ensured, and correspondingly, after the target layer 100 at the bottom of the first groove 210 and the second groove 220 is subsequently etched to form the target pattern, the pattern accuracy of the target pattern is also improved.

In this embodiment, after the sacrificial layer 160 is removed To form the second groove 220, the second groove 220 is divided by the dividing layer along the transverse direction, which is beneficial To realize a smaller distance between the second grooves 220 adjacent To each other along the transverse direction, that is, a smaller line end distance is realized at a Head-To-Head (HTH) position of the second groove 220, so that the design freedom of a target pattern is improved.

In this embodiment, the sacrificial layer 160 is removed by a wet etching process. Specifically, in this embodiment, the sacrificial layer 160 is doped with ions, the wet etching process has different etching rates for the ion-doped core layer 130 and the ion-undoped core layer 130, and the wet etching process has a larger etching selectivity for the anti-etching layer 150 and the sacrificial layer 160, so that the anti-etching layer 150 can be retained during the process of removing the sacrificial layer 160.

In this embodiment, the etching solution used in the wet etching process includes a mixed solution of Hydrofluoric acid (Hydrofluoric acid), Nitric acid (Nitric acid), and Acetic acid (Acetic acid), that is, an HNA solution. Compared with the etching rate of the amorphous silicon which is not doped with ions, the HNA solution has a higher etching rate to the amorphous silicon which is doped with ions, and the HNA solution is selected, so that the etching selection ratio of a wet etching process to the amorphous silicon which is doped with ions and the amorphous silicon which is not doped with ions is favorably improved, namely the etching selection ratio of the sacrificial layer 160 to the anti-etching layer 150 is favorably improved, the process difficulty of removing the sacrificial layer 160 is obviously reduced, the probability of damaging the anti-etching layer 150 is reduced, the pattern precision and the pattern quality of the second groove 220 are obviously improved, and the pattern integrity of the first groove 210 is favorably improved.

As an example, in a mixed solution of hydrofluoric acid, nitric acid and acetic acid adopted by the wet etching process, the volume ratio of the hydrofluoric acid to the acetic acid is 1:8 to 1:100, and the volume ratio of the hydrofluoric acid to the nitric acid is 1:3 to 1: 50. By setting the volume ratio of hydrofluoric acid, nitric acid and acetic acid within the above range, it is ensured that the HNA solution can significantly improve the etching selectivity to the sacrificial layer 160 and the anti-etching layer 150, even when the etching rate to the anti-etching layer 150 is nearly stopped.

As an example, in the HNA solution adopted in the wet etching process, the volume ratio of hydrofluoric acid to nitric acid to acetic acid is 1: 3: 8.

as an example, in a mixed solution of hydrofluoric acid, nitric acid and acetic acid, the molecular ratio between the nitric acid and the hydrofluoric acid is at least 2, and the molar percentage of the nitric acid is at least 14%.

As an example, in a mixed solution of hydrofluoric acid, nitric acid and acetic acid, the molar percentage of the hydrofluoric acid is 0.2% to 6%, the molar percentage of the nitric acid is 14% to 28%, and the molar percentage of the acetic acid is 66% to 86%.

By setting the molecular ratio between the nitric acid and the hydrofluoric acid and the molar percentages of the hydrofluoric acid, the nitric acid and the acetic acid within the above ranges, the improvement effect of the HNA solution on the etching selectivity of the sacrificial layer 160 and the anti-etching layer 150 is more remarkable, even the etching rate of the anti-etching layer 150 is nearly stopped, and meanwhile, the etching rate of the wet etching process on the sacrificial layer 160 is slower, so that the etching rate of the wet etching process is controllable, the process controllability of the wet etching process is improved, and the process difficulty of removing the sacrificial layer 160 is further reduced.

Referring to fig. 21 and 22, fig. 21 is a top view, and fig. 22 is a cross-sectional view taken along the yy cut line of fig. 21, wherein the target layer 100 at the bottom of the first recess 210 and the second recess 220 is etched using the etch-resistant layer 150 and the sidewall spacers 190 as masks, so as to form a target pattern 300.

As can be seen from the above description, the pattern precision and the pattern quality of the first groove 210 and the second groove 220 are high, and the function of the anti-etching layer 150 as a mask for etching the target layer 100 can be ensured, which is beneficial to improving the process effect of patterning the target layer 100, and further improving the pattern precision and the pattern quality of the target pattern 300.

In this embodiment, the target layer 100 is a dielectric layer, and therefore, the dielectric layer at the bottoms of the first groove 210 and the second groove 220 is etched by using the anti-etching layer 150 and the sidewall spacers 190 as masks, so as to form an interconnection trench. Accordingly, in this embodiment, the target pattern 300 is an interconnection groove.

The interconnection groove is used for providing a space position for forming the metal wire.

In this embodiment, the hard mask material layer 110 and the etch stop layer 120 are further formed on the target layer 100, and the etch stop layer 120 is exposed at the bottoms of the first recess 210 and the second recess 220.

Therefore, with the anti-etching layer 150 and the sidewall spacers 190 as masks, the etching stop layer 120 and the hard mask material layer 110 at the bottoms of the first groove 210 and the second groove 220 are sequentially etched, and the remaining hard mask material layer 110 is used as a hard mask layer 230; the target layer 100 is patterned by using the hard mask layer 230 as a mask.

The hard mask layer 230 is formed by transferring the patterns of the first and second recesses 210 and 220 into the hard mask material layer 110, which is beneficial to improving the process stability and process effect of the patterning target layer 100.

In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to sequentially etch the etch stop layer 120, the hard mask material layer 110, and the target layer 100 at the bottoms of the first recess 210 and the second recess 220. The dry etching process has the characteristic of anisotropic etching, has good controllability of an etching profile, and is beneficial to improving the precision of pattern transfer, so that the target pattern 300 formed in the target layer 100 meets the process requirement, and the dry etching process is also beneficial to realizing a larger etching selection ratio, thereby improving the process effect of patterning the target layer 100.

In this embodiment, during the process of patterning the target layer 100, the etch stop layer 150 and the sidewall spacers 190 are also consumed by a portion of the thickness.

Referring to fig. 23 and 24 in combination, fig. 23 is a top view, and fig. 24 is a cross-sectional view taken along a yy cut line of fig. 23, in this embodiment, the method for forming a semiconductor structure further includes: after the formation of the interconnection trenches, metal lines 310 are formed in the interconnection trenches.

Metal lines 310 are used to make electrical connections to the semiconductor structure to external circuitry or other interconnect structures.

As can be seen from the foregoing description, the interconnection grooves have high pattern precision and high pattern quality, and the distance between adjacent interconnection grooves easily satisfies the designed minimum interval, which is accordingly beneficial to make the longitudinal distance of the metal line 310 satisfy the designed minimum interval, and at the same time, the interconnection grooves can also realize a smaller distance at the head-to-head position, which is also beneficial to improving the pattern precision and the design freedom of the metal line 310, and further beneficial to improving the electrical connection performance of the metal line 310.

In this embodiment, the metal line 310 is made of copper. In other embodiments, the material of the line can also be a conductive material such as cobalt, tungsten, aluminum, and the like.

In this embodiment, during the process of forming the metal line 310, the remaining anti-etching layer 150, the sidewall spacers 190, the etch stop layer 120, and the hard mask layer 230 are also removed, so as to expose the top surface of the dielectric layer, thereby preparing for the subsequent process.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a target layer for forming a target pattern;

forming a core layer on the substrate, the core layer including an etch-resistant region for forming an etch-resistant layer and a sacrificial region for forming a sacrificial layer;

performing ion doping on the core layer of the sacrificial region, wherein the etching rates of the core layer of the sacrificial region and the core layer of the anti-etching region are different, the core layer doped with ions in the sacrificial region is used as the sacrificial layer, and the core layer not doped with ions in the anti-etching region is used as the anti-etching layer;

forming a groove penetrating through the core layer between the adjacent sacrificial regions, wherein the side wall of the groove exposes the core layer in the sacrificial regions;

forming a side wall on the side wall of the groove, wherein the side wall positioned on the side wall of the groove is encircled to form a first groove;

after ion doping and the first groove are formed, removing the sacrificial layer by adopting an etching process, and forming a second groove penetrating through the anti-etching layer in the anti-etching layer; wherein, the etching speed of the etching process to the sacrificial layer is greater than that to the anti-etching layer;

and etching the target layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form a target pattern.

2. The method of claim 1, wherein after forming the core layer and before forming the trench, ion doping the core layer of the sacrificial region;

or after the groove is formed and before the side wall is formed, carrying out ion doping on the core layer of the sacrificial region;

or after the side walls are formed and before the second grooves are formed, ion doping is performed on the core layer of the sacrificial region.

3. The method of claim 1, wherein the ions that ion-dope the core layer of the sacrificial region comprise boron ions, phosphorous ions, arsenic ions, or argon ions.

4. The method of claim 1, wherein in the step of ion doping the core layer of the sacrificial region, the ion doping concentration in the core layer of the sacrificial region is from 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter.

5. The method of claim 1, wherein the core layer of the sacrificial region is ion doped using an ion implantation process.

6. The method of forming a semiconductor structure of claim 5, wherein the parameters of the ion implantation process comprise: the implantation energy is 1KeV to 100KeV, and the implantation direction forms an angle of 0 DEG to 5 DEG with the normal of the substrate surface.

7. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer is removed using a wet etch process.

8. The method of claim 7, wherein the wet etching process uses an etching solution comprising a mixture of hydrofluoric acid, nitric acid, and acetic acid.

9. The method according to claim 8, wherein the wet etching process uses a mixed solution of hydrofluoric acid, nitric acid and acetic acid, wherein a molecular ratio between the nitric acid and the hydrofluoric acid is at least 2, and a molar percentage of the nitric acid is at least 14%.

10. The method for forming a semiconductor structure according to claim 9, wherein a mixed solution of hydrofluoric acid, nitric acid and acetic acid is used in the wet etching process, the molar percentage of hydrofluoric acid is 0.2% to 6%, the molar percentage of nitric acid is 14% to 28%, and the molar percentage of acetic acid is 66% to 86%.

11. The method for forming a semiconductor structure according to claim 8, wherein in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the volume ratio of hydrofluoric acid to acetic acid is 1:8 to 1:100, and the volume ratio of hydrofluoric acid to nitric acid is 1:3 to 1: 50.

12. The method of claim 1, wherein in the step of forming the core layer, the material of the core layer comprises amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.

13. The method of claim 1, wherein ion doping the core layer of the sacrificial region comprises: forming a shielding layer covering the etching resistant area, wherein the shielding layer exposes the sacrificial area; and performing the ion doping on the core layer by taking the shielding layer as a mask.

14. The method of forming a semiconductor structure of claim 1, wherein the target layer is a dielectric layer;

etching the dielectric layer at the bottoms of the first groove and the second groove by taking the anti-etching layer and the side wall as masks to form an interconnection groove;

the method for forming the semiconductor structure further comprises the following steps: after forming the interconnection trench, forming a metal line in the interconnection trench.

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