CN112053946B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN112053946B CN112053946B CN201910492662.8A CN201910492662A CN112053946B CN 112053946 B CN112053946 B CN 112053946B CN 201910492662 A CN201910492662 A CN 201910492662A CN 112053946 B CN112053946 B CN 112053946B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
A semiconductor device and a method of forming the same, including: providing a substrate; sequentially forming a first material layer and a second material layer on the surface of a substrate; forming a first mask layer on the surface of the second material layer, wherein a first groove is formed between adjacent first mask layers, the first mask layer has a first size, and the first groove has a second size; forming a first hard doped layer having first ions within the first material layer at the bottom of the first trench; removing the first material layer to form a second groove; thinning the initial first doped layer to form a first doped layer, forming a second groove into an initial third groove, wherein the first doped layer has a third size, and the initial third groove has a fourth size; forming a first doping mask layer and a second doping mask layer in the second material layer, wherein the first doping mask layer is positioned at the bottom of the second groove, and the second doping mask layer is positioned at the bottom of the initial third groove; the first doped layer and the second material layer are removed to form a third trench. The method improves the performance of the semiconductor device.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
With the rapid development of semiconductor technology, the feature size of semiconductor devices is continuously reduced, so that the integrated circuit is more and more integrated, and the requirements on the semiconductor manufacturing process are also higher. Etching is an important process in semiconductor manufacturing, and is a process of transferring a pattern on a mask onto a material layer, and as the feature size is continuously reduced, the etching process encounters a bottleneck due to the existence of a wavelength limit in the photolithography process, so that etching of a trench with a smaller size cannot be provided.
In order to obtain smaller pitch sizes, multiple Patterning Lithography (MPL) has been developed. Two forms of MPL have been tried, one using repeated lithographic processes (photolithography-etch-lithography or LELE) techniques and the other based on self-aligned spacer processing. The self-aligned spacer process is advantageous when fabricating fins of FinFET structures.
The self-aligned spacer process is commonly referred to as a self-aligned dual process (SADP). In SADP, a set of mandrels is lithographically formed by patterning and etching a mandrel material. Sidewall spacers may then be formed on the sidewalls of the mandrels. The formation of sidewall spacers may be accomplished by depositing material over the mandrel material, removing the deposited material on the horizontal surfaces, and removing the mandrel material, leaving the sidewall spacers behind. The deposition of sidewall spacers may result in a spacer width that is much smaller than the spacer width achievable by photolithographic formation of mandrels. The sidewall spacers and mandrels may then be polished to expose the mandrels and the spacers that act as an etch mask to remove remaining mandrel material. The SADP process involves forming spacers as a film layer on the sidewalls of a pre-patterned mandrel, removing the spacer layer from the horizontal surface, and removing the initially patterned mandrel material leaving the spacers themselves. Since each mandrel has two sidewall spacers, the linear density is doubled. Thus, SADP is suitable for defining narrow fins at half the initial lithographic pitch.
However, due to the limitations of the photolithography process, the pitch of the fin formed by SADP is difficult to adjust.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which aims to improve the performance of the semiconductor device.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate; forming a first material layer on the surface of the substrate; forming a second material layer on the first material layer; forming a plurality of discrete first mask layers on the surface of the second material layer, wherein first grooves are formed between adjacent first mask layers, the first mask layers have a first size in a first direction parallel to the surface of the substrate, and the first grooves have a second size; doping first ions in a second material layer at the bottom of the first groove, and forming an initial first doped layer in the second material layer; after forming an initial first doped layer, removing the second material layers on two sides of the initial first doped layer to form a second groove and an initial third groove which are respectively positioned on two sides of the initial first doped layer, wherein the second groove and the initial second groove have a first size in a first direction parallel to the surface of the substrate; after forming a second groove and an initial third groove, thinning the side wall of the initial first doping layer exposed by the initial third groove to form a first doping layer, so that the initial third groove forms a third groove, the size of the first doping layer is a third size in a first direction parallel to the surface of the substrate, the third size is smaller than the second size, the size of the third groove is a fourth size, and the fourth size is larger than the first size; doping second ions in the first material layer at the bottom of the second groove, and forming a first doping mask layer in the first material layer; doping second ions in the first material layer at the bottom of the third groove, and forming a second doping mask layer in the first material layer; and after the first doping mask layer and the second doping mask layer are formed, removing the first doping layer and the first material layer to form a fifth groove.
Optionally, the forming method of the initial first doped layer includes: and carrying out first ion doping on the second material layer by taking the first mask layer as a mask, wherein the doped ions of the first ion doping are first ions, so that the second material layer at the bottom of the first groove is formed into an initial first doped layer.
Optionally, the first ion doping process includes: an ion implantation process or a solid state source doping process.
Optionally, the first ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
Optionally, the forming method of the first doped mask layer includes: and carrying out ion doping on the first material layer at the bottom of the second groove by taking the first doped layer as a mask, wherein the ion doped ions are second ions, so that the first material layer at the bottom of the second groove is formed into a first doped mask layer.
Optionally, the forming method of the second doped mask layer includes: and carrying out ion doping on the first material layer at the bottom of the third groove by taking the first doping layer as a mask, wherein the ion doped ions are second ions, so that the first material layer at the bottom of the third groove is formed into a second doping mask layer.
Optionally, the second doping mask layer is formed in the process of forming the first doping mask layer.
Optionally, the second ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
Optionally, the method further comprises: forming a first isolation layer on the surface of the first material layer, wherein the second material layer is positioned on the surface of the first isolation layer; the second and third grooves expose a first spacer surface; and after the first doping mask layer and the second doping mask layer are formed, removing the first doping layer, the first isolation layer and the second material layer to form a fifth groove.
Optionally, the method of forming the fifth groove includes: removing the first doped layer; removing the first isolation layer after removing the first doping layer; and removing the second material layer after removing the first isolation layer.
Optionally, the material of the first material layer includes: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
Optionally, the process of removing the first material layer includes: a dry etching process or a wet etching process.
Optionally, the material of the second material layer includes: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
Optionally, the method for thinning the sidewall of the initial first doped layer exposed by the initial third trench includes: forming a second mask layer on the surface of the first material layer, wherein the second mask layer is positioned on part of the surface of the initial first doping layer and part of the surface of the second material layer, and the initial third groove and part of the top surfaces of the first mask layer on two sides of the initial third groove are exposed; and taking the second mask layer as a mask, and etching to remove part of the first mask layer, so that the initial first doped layer forms a first doped layer.
Optionally, the substrate includes: the substrate, the initial first dabber layer that is located the substrate surface and the initial second dabber layer that is located initial first dabber layer surface.
Optionally, the substrate further comprises: the first protection layer is formed on the surface of the substrate, and the initial first mandrel layer is positioned on the surface of the first protection layer; forming a second protective layer on the surface of the initial first mandrel layer, wherein the initial second mandrel layer is positioned on the surface of the second protective layer; and forming a third protective layer on the surface of the initial second mandrel layer, wherein the first material layer is positioned on the surface of the third protective layer.
Optionally, the substrate includes: a plurality of first regions and second regions located between adjacent first regions; the first mask layer is positioned on the surface of the second material layer in the first area; the first doping mask layer and the second doping mask layer are positioned on the substrate surface of the first region, and the first doping mask layer and the second doping mask layer expose the substrate surface of the second region; the method for forming the semiconductor device further comprises the following steps: etching the initial first mandrel layer by taking the first doping mask layer and the second doping mask layer as masks to form a first mandrel layer, wherein a first opening is formed between adjacent first mandrel layers of the first region, the size of the first opening is a first size, and a second opening is formed between the first mandrel layers of the adjacent first region; forming a first side wall on the side wall of the first mandrel layer, wherein the first side wall fills the first opening, and the first side wall is also positioned on the side wall of the second opening; removing the first mandrel layer after forming the first side wall; after the first mandrel layer is removed, the first side wall is used as a mask, the initial second mandrel layer is etched, a second mandrel layer is formed on the first area substrate, the second mandrel layer is further positioned on the second area substrate, a third opening and a fourth opening are respectively formed on two sides of the second mandrel layer of the first area, and in a first direction parallel to the surface of the substrate, the size of the third opening is a first size, and the size of the fourth opening is a fourth size; forming a second side wall on the side wall of the second mandrel layer, wherein the second side wall is further positioned on the second area substrate, the second side wall covers the third opening and the side wall of the fourth opening, the second side wall has a fifth size, the first size is larger than twice of the fifth size, and the fourth size is larger than twice of the fifth size; removing the second mandrel layer after forming the second side wall; removing the second side wall of the second region after removing the second mandrel layer; and after removing the second side wall of the second region, etching the substrate by taking the second side wall of the first region as a mask, and forming a fin part in the substrate.
Optionally, the surface of the second material layer of each first region forms 3 separate first mask layers.
The invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor device provided by the technical scheme of the invention, the first mask layers have the same size in the first direction parallel to the surface of the substrate, and the first grooves have the same size, so that the method is easy to realize by adopting a photoetching process. An initial first doped layer and second and third trenches respectively located in the initial first doped layer are formed by reverse transfer of the first mask layer. And thinning the initial first doping layer side wall exposed by the initial third groove to form a first doping layer, so that the initial third groove is formed into a third groove, and the sizes of the second groove and the third groove are different. And forming a first doping mask layer, a second doping mask layer and a third groove through reverse transfer of the first doping layer, wherein the sizes of the second groove and the third groove are different, and the sizes of the first doping mask layer and the second doping mask layer are also different. And forming an imaging layer of a subsequent SADP process by taking the first doping mask layer and the second doping mask layer as masks, thereby realizing fin parts with different pitches. Thereby improving the performance of the semiconductor device.
Further, the distance between the two second side walls of the side wall of the third opening is the size of the third opening minus the thickness of the two second side walls; the third opening is formed by reversely transferring the first doped mask layer, and the size of the third opening is equal to the size of the first doped mask layer to be the first size. The distance between the two second side walls of the side wall of the fourth opening is the size of the fourth opening minus the thickness of the two second side walls; the fourth opening is formed by reversely transferring the second doping mask layer, and the size of the fourth opening is equal to the size of the second doping mask layer to be the fourth size. The distance between the second side walls on two sides of the second mandrel layer in the first region is the size of the second mandrel layer, the size of the second mandrel layer is formed by reversely transferring the third groove, the size of the second mandrel layer is equal to the size of the third groove, the third groove is formed by reversely transferring the first doped layer, and the size of the third groove is equal to the size of the first doped layer to be the third size. Therefore, the first size, the third size and the fourth size are reasonably designed, and fin parts with multiple pitches can be realized. Thereby improving the performance of the semiconductor device.
Drawings
Fig. 1 to 15 are schematic structural views of a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the prior art semiconductor device is poor.
As semiconductor devices develop, it is required to form fins with multiple pitches, i.e., the distance between adjacent fins has multiple dimensions. At the same time, the fin size of FinFET devices is further shrinking, and such small-sized fins have not been realized using photolithography techniques, but using SADP processes. However, it is difficult to form fins of multiple pitches even by the SADP process. Therefore, semiconductor devices having fins with multiple pitches are difficult to realize.
In an embodiment of the invention, a substrate is provided; sequentially forming a first material layer and a second material layer on the surface of a substrate; forming a first mask layer on the surface of the second material layer, wherein a first groove is formed between adjacent first mask layers, the first mask layer has a first size, and the first groove has a second size; forming a first hard doped layer having first ions within the first material layer at the bottom of the first trench; removing the first material layer to form a second groove; thinning the initial first doped layer to form a first doped layer, forming a second groove into an initial third groove, wherein the first doped layer has a third size, and the initial third groove has a fourth size; forming a first doping mask layer and a second doping mask layer in the second material layer, wherein the first doping mask layer is positioned at the bottom of the second groove, and the second doping mask layer is positioned at the bottom of the initial third groove; the first doped layer and the second material layer are removed to form a third trench. And forming a third groove through thinning the initial first doping layer, so that the second groove and the initial third groove are different in size, and forming a first doping mask layer and a second doping mask layer with different sizes through reverse transfer of the first doping layer. And then forming fin parts with different pitches through the first doping mask layers and the second doping mask layers with different sizes.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 15 are schematic structural views of a semiconductor device forming process.
Referring to fig. 1, a substrate is provided.
In this embodiment, the substrate includes a plurality of first regions I and second regions II located between adjacent first regions I.
In this embodiment, the substrate includes: a substrate 200, an initial first mandrel layer 202 located on a surface of the substrate 200, and an initial second mandrel layer 204 located on a surface of the initial first mandrel layer 202.
In this embodiment, the substrate further includes: a first protective layer 201 formed on the surface of the substrate 200, wherein an initial first mandrel layer 202 is located on the surface of the first protective layer 201; forming a second protective layer 203 on the surface of the initial first mandrel layer 202, wherein the initial second mandrel layer 204 is positioned on the surface of the second protective layer 203; a third protective layer 205 is formed on the surface of the initial second mandrel layer 204.
The substrate 200 is used to provide a layer of material for forming the fin.
The substrate 200 includes: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium. In this embodiment, the material of the substrate 200 is: silicon, the substrate 200 is formed using a selective epitaxial process.
The materials of the first protective layer 201, the second protective layer 203 and the third protective layer 205 include: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride or silicon oxycarbide.
The first protective layer 201, the second protective layer 203, and the third protective layer 205 are etching stop layers.
In this embodiment, the materials of the first protective layer 201, the second protective layer 203, and the third protective layer 205 are silicon oxide.
The materials of the initial first mandrel layer 202 include: amorphous silicon, amorphous carbon, polysilicon SiCO or SiCOH.
The materials of the initial second mandrel layer 204 include: amorphous silicon, amorphous carbon, polysilicon SiCO or SiCOH. A step of
In this embodiment, the material of the initial first mandrel layer 202 is polysilicon. The material of the initial second mandrel layer 204 is polysilicon.
With continued reference to fig. 1, a first material layer 210 is formed on the substrate surface; a second material layer 220 is formed on the first material layer 210.
In this embodiment, the first material layer 210 is located on the surface of the third protection layer 205.
In this embodiment, a first isolation layer 211 is further formed on the surface of the first material layer 210; the second material layer 220 is located on the surface of the first isolation layer 211.
The first material layer 210 provides a material layer for subsequent formation of an initial first doped layer.
The second material layer 220 provides a material layer for subsequently forming a first doped mask layer and a second doped mask layer.
The materials of the first material layer 210 include: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
The materials of the second material layer 220 include: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
In this embodiment, the material of the first material layer 210 is amorphous silicon. The material of the second material layer 220 is amorphous silicon.
The process of forming the first material layer 210 includes: a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the first material layer 210 is a chemical vapor deposition process. In other embodiments, the first material layer is formed using a physical vapor deposition process or an atomic layer deposition process.
The process of forming the second material layer 220 includes: a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the second material layer 220 is a chemical vapor deposition process. In other embodiments, the first material layer is formed using a physical vapor deposition process or an atomic layer deposition process.
Referring to fig. 2, a plurality of first mask layers 230 are formed on the surface of the second material layer 220, and first trenches 231 are formed between adjacent first mask layers 230 in the first region I, wherein the first mask layers 230 have a first dimension a and the first trenches 231 have a second dimension B along the first direction.
In this embodiment, 3 separate first mask layers 230 are formed on the surface of the second material layer 220 in each first region I.
The first mask layer 230 exposes the surface of the second material layer 220 in the second region II.
In this embodiment, a sixth trench 232 is formed between the first mask layers 230 adjacent to the first region I.
The sixth slot 232 has a seventh dimension C in a first direction parallel to the substrate surface.
In this embodiment, the material of the first mask layer 230 is a photoresist material. In other embodiments, the material of the first mask layer is a hard mask layer, and the material of the hard mask layer includes: amorphous carbon, silicon oxide, silicon nitride or titanium nitride.
The method for forming the first mask layer 230 includes: forming an initial first mask layer on the surface of the second material layer 220; the initial first mask layer is exposed and developed to form the first mask layer 230.
In a first direction parallel to the substrate surface, the dimensions of the first mask layer are the same, and the dimensions of the first grooves are the same, which is easily achieved by using a photolithography process.
Referring to fig. 3, first ions are doped in the second material layer 220 at the bottom of the first trench 231, and an initial first doped layer 241 is formed in the second material layer.
The initial first doped layer 241 has first ions therein.
The initial first doped layer 241 has a second dimension B.
The forming method of the initial first doping layer 241 includes: the first mask layer 230 is used as a mask to perform first ion doping on the second material layer 220, and the doped ions of the first ion doping are first ions, so that the second material layer 220 at the bottom of the first trench 231 is formed as an initial first doped layer 241.
The first ion doping process comprises the following steps: an ion implantation process or a solid state source doping process.
In this embodiment, the first ion doping process is an ion implantation process. In other embodiments, the first ion doping process is a solid state source doping process.
The first ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
In this embodiment, the first ion is a boron ion.
The initial first doped layer 241 is formed by doping the second material layer 220 with first ions, and the first ions enter into the ion gaps of the second material layer 220, so that the ion state of the initial first doped layer 241 is stable and is not easy to be etched.
The initial first doped layer 241 provides a material layer for the subsequent formation of the first doped layer.
In this embodiment, the method further includes: an initial second doped layer 242 is formed within the second material layer 220 of the second region II.
In this embodiment, the initial second doped layer 242 is formed during the formation of the initial first doped layer 241.
In this embodiment, after the initial first doped layer 241 is formed, the first mask layer 230 is removed. The process of removing the first mask layer 230 is an ashing process.
Referring to fig. 4, after the initial first doping layer 241 is formed, the second material layer 220 is removed, and the second and third trenches 221 and 222 are formed at both sides of the initial first doping layer 241, respectively.
The second slot 221 and the initial third slot 222 have a first dimension a.
The second grooves 221 and the initial third grooves 222 expose the surface of the first isolation layer 211.
The process of removing the second material layer 220 includes: a dry etching process or a wet etching process.
In the process of removing the second material layer 220, there is a first etch rate for the second material layer 220 and a second etch rate for the initial first doped layer 241, the first etch rate being greater than the second etch rate.
In a specific embodiment, the ratio of the first etching rate to the second etching rate is 5 to 10.
The first etch rate is greater than the second etch rate, which can ensure less consumption of the initial first doped layer 241 while removing the second material layer 220.
In this embodiment, the process of removing the second material layer 220 is a wet etching process; the parameters of the wet etching process include: HF and H 2 Hydrofluoric acid solution with O volume ratio of 1/2000-1/100.
The initial first doped layer, the second trench, and the initial third trench are formed by reverse transfer to the first mask layer. The initial first doped layer has a second dimension B equal to the first trench dimension; the second groove and the initial third groove have the same size as the first mask layer and are the first size A.
Referring to fig. 5, after forming the second trench 221 and the initial third trench 222, thinning the initial first doped layer 241 sidewall exposed by the initial third trench 222 to form a first doped layer 243, such that the initial third trench 222 is formed as a third trench 224, and the first doped layer 243 has a third dimension E in the first direction, the third dimension E being smaller than the second dimension B, and the third trench 224 has a fourth dimension D; the fourth dimension D is greater than the first dimension a.
The method for thinning the sidewall of the initial first doped layer 241 exposed by the initial third trench 222 includes: forming a second mask layer 250 on the surface of the first isolation layer 211, where the second mask layer 250 is located on the initial second doped layer 242, part of the surface of the initial first doped layer 241 and part of the surface of the second material layer, and exposes the initial third groove 222 and part of the top surface of the first mask layer 241 on two sides of the initial third groove 222; with the second mask layer 250 as a mask, a portion of the initial first doped layer 241 is etched away, so that the initial first doped layer 241 forms a first doped layer 243.
The process of etching away a portion of the initial first doped layer 241 includes: an anisotropic dry etching process. In this embodiment, the parameters of the dry etching process include: using gases as CF 4 、CH 2 F 2 、CH 3 F and O 2 ，CF 4 The flow rate of (C) is 50sccm to 500sccm, CH 2 F 2 The flow rate of (C) is 0 to 100sccm, CH 3 F has a flow rate of 0 to 100sccm, O 2 The flow rate of the chamber is 10sccm to 100sccm, the source radio frequency power is 50W to 500W, the bias radio frequency power is 100W to 1000W, and the chamber pressure is 100 millitorr to 200 millitorr.
In this embodiment, the material of the second mask layer 250 is photoresist.
The second groove 221 and the initial third groove 222 have the same size, and the third groove 224 has a size larger than the initial third groove 222, so that the second groove 221 has a size not identical to the third groove 224.
In this embodiment, after the first doped layer 243 is formed, the second mask layer 250 is removed. The process of removing the second mask layer 250 is an ashing process.
Referring to fig. 6, the second ions are doped in the first material layer 210 at the bottom of the second trench 221, the first doping mask layer 251 is formed in the first material layer 210, the second ions are doped in the first material layer 210 at the bottom of the third trench 224, and the second doping mask layer 252 is formed in the first material layer 210.
The first doping mask layer 251 and the second doping mask layer 252 each have second ions therein.
The method for forming the first doping mask layer 251 includes: the first material layer 210 at the bottom of the second trench 221 is ion doped with the first doped layer 243 as a mask, and the ion doped ions are second ions, so that the first material layer 210 at the bottom of the second trench 221 is formed as a first doped mask layer 251.
The forming method of the second doped mask layer 252 includes: the first material layer 210 at the bottom of the third trench 224 is ion doped with the first doped layer 243 as a mask, and the ion doped ions are second ions, so that the first material layer 210 at the bottom of the third trench 224 is formed as the second doped mask layer 252.
In this embodiment, the second doped mask layer 252 is formed during the process of forming the first doped mask layer 251. In other embodiments, after the first doped mask layer is formed, the second doped mask layer is formed or after the second doped mask layer is formed, the first doped mask layer is formed.
In this embodiment, the forming method of the first doping mask layer 251 and the second doping mask layer 252 includes: the first material layer 210 is doped with second ions by using the first doped layer 243 and the initial second doped layer 242 as masks, and the doped ions of the second ion doping are second ions, so that the first material layer 210 at the bottom of the second trench 221 is formed as a first doped mask layer 251, and the first material layer 210 at the bottom of the third trench 224 is formed as a second doped mask layer 252.
The second ion doping process comprises the following steps: an ion implantation process or a solid state source doping process.
In this embodiment, the second ion doping process is an ion implantation process. In other embodiments, the first ion doping process is a solid state source doping process.
The second ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
In this embodiment, the second ion is a boron ion.
The first doping mask layer 251 and the second doping mask layer 252 are formed by doping the first material layer 210 with second ions, and the second ions enter into the ion gaps of the first material layer 210, so that the ion states of the first doping mask layer 251 and the second doping mask layer 252 are stable and are not easy to be etched.
The dimension of the first doping mask layer 251 is a first dimension a along the first direction; the second doping mask layer 252 has a fourth dimension D, which is greater than the first dimension a.
Referring to fig. 7, after forming the first doping mask layer 251 and the second doping mask layer 252, the first doping layer 243 is removed.
In this embodiment, in the process of removing the first doped layer 243, the initial second doped layer 242 is also removed.
The second and third grooves 221 and 224 expose the first isolation layer 211.
The material of the first isolation layer 211 is silicon oxide, and the material of the first doped layer 243 is polysilicon doped with boron ions. The first isolation layer 211 and the first doped layer 243 are of different materials. Proper selection of the etching parameters can ensure that the influence on the first isolation layer 211 is reduced in the case of removing the first doped layer 243.
The process of removing the first doped layer 243 includes: a dry etching process or a wet etching process.
The process of etching away a portion of the first doped layer 243 includes: an anisotropic dry etching process. In this embodiment, the parameters of the dry etching process include: using gas as HBr and O 2 HBr flow rate of 50sccm to 500sccm, O 2 The flow rate of (2) is 0-100 sccm, source radio frequencyThe power is 50-500W, the bias radio frequency power is 0-50W, and the pressure of the chamber is 50-500 mTorr.
Referring to fig. 8, after removing the first doping layer 243, the first isolation layer 211 is removed; after the first isolation layer 211 is removed, the first material layer 210 is removed, and a fifth groove 253 is formed on the substrate surface of the first region I.
The bottom of the fifth groove 253 exposes the substrate surface of the first region I.
The fifth groove 253 has a third dimension E in the first direction.
The process of removing the first isolation layer 211 includes: a dry etching process or a wet etching process.
The process of removing the first material layer 210 includes: a dry etching process or a wet etching process.
In this embodiment, the process of removing the first material layer 210 is a wet etching process. The parameters of the wet process include: HF and H 2 Hydrofluoric acid solution with O volume ratio of 1/2000-1/100.
In the process of removing the first material layer 210, there is a first etch rate for the first material layer 210, and a second etch rate for the first doping mask layer 251 and the second doping mask layer 252, the first etch rate being greater than the second etch rate.
In a specific embodiment, the ratio of the first etch rate to the second etch rate is between 5 and 20.
The first etching rate is greater than the second etching rate, so that the consumption of the first doping mask layer 251 and the second doping mask layer 252 can be reduced while the first material layer 210 is removed.
In this embodiment, the substrate further includes a second region II, and the first doping mask layer 251 and the second doping mask layer 252 expose a substrate surface of the second region II.
In this embodiment, a seventh trench 254 is formed between the first doping mask layer 251 or the second doping mask layer 252 adjacent to the first region I.
The seventh slot 254 has a seventh dimension C in a first direction parallel to the substrate surface.
By the reverse transfer of the first doping layer 243, the first doping mask layer 251, the second doping mask layer 252, and the third trench 253 are formed, and the first doping mask layer 251 and the second doping mask layer 252 are different in size in the first direction.
The first doping mask layer 251 and the second doping mask layer 252 are used as masks to form patterned layers of the subsequent SADP process, so as to form fin portions with different pitches. Please refer to fig. 9 to 15.
Referring to fig. 9, the first mandrel layer 204 is etched with the first doped mask layer 251 and the second doped mask layer 252 as masks, so as to form a first mandrel layer 260, wherein a first opening 261 is formed between adjacent first mandrel layers 260 of the first region I, and a second opening 262 is formed between adjacent first mandrel layers 260 of the first region I.
The first opening 261 has a first dimension a and the second opening 262 has a seventh dimension C in a first direction parallel to the substrate surface.
The material of the initial first mandrel layer 204 is polysilicon, and the material of the first mandrel layer 260 is polysilicon.
The process of etching the initial first mandrel layer 204 includes: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the first mandrel layer 260 is formed by etching the third protection layer 205 and the initial first mandrel layer 204 using the first doped mask layer 251 and the second doped mask layer 252 as masks.
The first opening 261 and the second opening 262 expose the surface of the second protection layer 203. The second protective layer 203 is an etch stop layer when the initial first mandrel layer 204 is etched.
Referring to fig. 10, a first sidewall 270 is formed on a sidewall of the first mandrel layer 260, and the first opening 261 is filled with the first sidewall 270, and the first sidewall 270 is further located on a sidewall of the second opening 262.
The material of the first sidewall 270 includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride or silicon oxycarbide.
In this embodiment, the material of the first sidewall 270 is silicon nitride.
The method for forming the first side wall 270 includes: forming an initial first sidewall material layer within the first opening 261, within the second opening 262, and on the surface of the first mandrel layer 260; and etching back the initial first sidewall material layer until the surface of the first mandrel layer 260, the bottom surfaces of the first opening 261 and the second opening 262 are exposed, thereby forming the first sidewall 270.
Referring to fig. 11, after forming the first sidewall 270, the first mandrel layer 260 is removed.
In this embodiment, before removing the first mandrel layer 260, removing the third protection layer 205 on top of the first mandrel layer 260 is further included.
The process of removing the first mandrel layer 260 includes: a dry etching process or a wet etching process.
In this embodiment, the material of the first mandrel layer 260 is polysilicon, and the process of removing the first mandrel layer 260 is a wet etching process.
Referring to fig. 12, after the first mandrel layer 260 is removed, the initial second mandrel layer 202 is etched using the first sidewall 270 as a mask, and a second mandrel layer 280 is formed on the first region I substrate 200, and the second mandrel layer 280 is further located on the second region II substrate 200.
In this embodiment, the method further includes: etching the second protective layer 203 and the initial second mandrel layer 202 with the first sidewall 270 as a mask; the second mandrel layer 280 is formed.
The second mandrel layer 280 of the first region I has a third opening 281 and a fourth opening 282 on both sides thereof, respectively.
The third opening 281 has a size of a first size a in a first direction parallel to the substrate surface; the fourth opening 282 has a fourth dimension D.
A fifth opening 283 is formed between adjacent second mandrel layers 280 in the second region II.
The fifth opening 283 has a size of a seventh dimension C in a first direction parallel to the substrate surface.
The third opening 281, the fourth opening 282, and the fifth opening 283 expose the surface of the first protective layer 201.
Referring to fig. 13, a second sidewall 290 is formed on the sidewall of the second mandrel layer 280, and the second sidewall 290 is further located on the substrate 200 in the second region II.
In a first direction parallel to the substrate surface, the second sidewall 290 has a fifth dimension e, the first dimension a is greater than twice the fifth dimension e, and the fourth dimension D is greater than twice the fifth dimension e.
The second sidewall 290 covers the sidewalls of the third opening 281, the fourth opening 282 and the fifth opening 283.
The dimensions of the second sidewall 290 in the first region I in the first direction parallel to the substrate surface determine the width of the fin to be subsequently formed. The second side walls are located in the third opening 281 and the fourth opening 282, and then in the first direction parallel to the substrate surface, the size of the third opening 281 and the size of the fourth opening 282 determine the distance between the second side walls 290 located in the third opening 281 and the size of the fourth opening 282 determines the distance between the second side walls 290 located in the fourth opening 282.
The second side walls 290 of the side walls of the third opening 281 are separated by a first distance a, where the first distance a is the dimension of the third opening 281 minus the thickness of the two second side walls 290.
In this embodiment, the first distance a=the first dimension a-2×the fifth dimension e.
The distance between the two second side walls 290 of the side wall of the fourth opening 282 is a second distance b, and the second distance b is the size of the fourth opening 282 minus the thickness of the two second side walls 290.
In this embodiment, the second distance b=fourth dimension D-2×fifth dimension e.
The distance between the second sidewalls 290 on both sides of the second mandrel layer 280 in the first region I is a third distance c, and the third distance c is equal to the size of the second mandrel layer 280 in the first region I.
In this embodiment, the third distance c=a third dimension E.
The materials of the second sidewall 290 include: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride or silicon oxycarbide.
In this embodiment, the material of the second sidewall 290 is silicon nitride.
The method for forming the second sidewall 290 includes: forming an initial second sidewall material layer in the third opening 281, in the fourth opening 282, in the fifth opening 283 and on the surface of the second mandrel layer 280; and etching the initial second sidewall material layer until the bottom surfaces of the second mandrel layer 280, the third opening 281, the fourth opening 282 and the fifth opening 283 are exposed, thereby forming the second sidewall 290.
Referring to fig. 14, after forming the second sidewall 290, the second mandrel layer 280 is removed; after removing the second mandrel layer 280, the second sidewall 290 of the second region II is removed.
In this embodiment, before removing the second mandrel layer 280, removing the second protective layer 203 on top of the second mandrel layer 280 is further included.
The process of removing the second mandrel layer 280 includes: a dry etching process or a wet etching process.
The method for removing the second sidewall 290 of the second region II includes: forming a third mask layer on the substrate 200, where the third mask layer covers the surface of the second sidewall 290 of the first region I, and exposes the second sidewall 290 of the second region II; and removing the second side wall 290 of the second region II by taking the third mask layer as a mask.
The second side walls 290 have a fifth dimension e, and a first distance a, a second distance b and a third distance c are provided between adjacent second side walls 290 in the first region I.
Referring to fig. 15, after removing the second sidewall 290 of the second region II, the substrate 200 is etched with the second sidewall 290 of the first region I as a mask, and a fin 291 is formed in the substrate 200.
The fin 290 has a width of a fifth dimension e.
The pitch between fins 290 includes a first distance a, a second distance b, and a third distance c.
The first distance a=a first dimension a-2 is a fifth dimension e.
The second distance b=fourth dimension D-2×fifth dimension e.
The third distance c=a third dimension E.
Therefore, by adopting the method for forming a semiconductor device according to the present embodiment, fin portions with multiple pitches can be obtained by reasonably designing the values of the first dimension a, the third dimension E, and the fourth dimension D.
Correspondingly, the embodiment also provides a semiconductor device formed by adopting the method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a first material layer on the surface of the substrate;
forming a second material layer on the first material layer;
forming a plurality of discrete first mask layers on the surface of the second material layer, wherein first grooves are formed between adjacent first mask layers, the first mask layers have a first size in a first direction parallel to the surface of the substrate, and the first grooves have a second size;
Doping first ions in a second material layer at the bottom of the first groove, and forming an initial first doped layer in the second material layer;
after forming an initial first doped layer, removing the second material layers on two sides of the initial first doped layer to form a second groove and an initial third groove which are respectively positioned on two sides of the initial first doped layer, wherein the second groove and the initial third groove have a first size in a first direction parallel to the surface of the substrate;
after forming a second groove and an initial third groove, thinning the side wall of the initial first doping layer exposed by the initial third groove to form a first doping layer, so that the initial third groove forms a third groove, the size of the first doping layer is a third size in a first direction parallel to the surface of the substrate, the third size is smaller than the second size, the size of the third groove is a fourth size, and the fourth size is larger than the first size;
doping second ions in the first material layer at the bottom of the second groove, and forming a first doping mask layer in the first material layer;
doping second ions in the first material layer at the bottom of the third groove, and forming a second doping mask layer in the first material layer;
and after the first doping mask layer and the second doping mask layer are formed, removing the first doping layer and the first material layer to form a fifth groove.
2. The method of forming a semiconductor device according to claim 1, wherein the method of forming an initial first doped layer comprises: and carrying out first ion doping on the second material layer by taking the first mask layer as a mask, wherein the doped ions of the first ion doping are first ions, so that the second material layer at the bottom of the first groove is formed into an initial first doped layer.
3. The method of claim 2, wherein the first ion doping process comprises: an ion implantation process or a solid state source doping process.
4. The method of forming a semiconductor device according to claim 2, wherein the first ions comprise: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
5. The method of forming a semiconductor device of claim 1, wherein the method of forming a first doping mask layer comprises: and carrying out ion doping on the first material layer at the bottom of the second groove by taking the first doped layer as a mask, wherein the ion doped ions are second ions, so that the first material layer at the bottom of the second groove is formed into a first doped mask layer.
6. The method of forming a semiconductor device according to claim 1 or 5, wherein the method of forming the second doping mask layer comprises: and carrying out ion doping on the first material layer at the bottom of the third groove by taking the first doping layer as a mask, wherein the ion doped ions are second ions, so that the first material layer at the bottom of the third groove is formed into a second doping mask layer.
7. The method of claim 1, wherein the second doping mask layer is formed during the forming of the first doping mask layer.
8. The method of forming a semiconductor device according to claim 1, wherein the second ions comprise: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
9. The method for forming a semiconductor device according to claim 1, further comprising: forming a first isolation layer on the surface of the first material layer, wherein the second material layer is positioned on the surface of the first isolation layer; the second and third grooves expose a first spacer surface; and after the first doping mask layer and the second doping mask layer are formed, removing the first doping layer, the first isolation layer and the second material layer to form a fifth groove.
10. The method of forming a semiconductor device according to claim 9, wherein the method of forming a fifth trench comprises: removing the first doped layer; removing the first isolation layer after removing the first doping layer; and removing the second material layer after removing the first isolation layer.
11. The method of forming a semiconductor device according to claim 1, wherein a material of the first material layer comprises: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
12. The method of forming a semiconductor device of claim 11, wherein the process of removing the first material layer comprises: a dry etching process or a wet etching process.
13. The method of forming a semiconductor device according to claim 1, wherein a material of the second material layer includes: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
14. The method of forming a semiconductor device of claim 1, wherein the thinning of the initial first doped layer sidewall exposed by the initial third trench comprises: forming a second mask layer on the surface of the first material layer, wherein the second mask layer is positioned on part of the surface of the initial first doping layer and part of the surface of the second material layer, and the initial third groove and part of the top surfaces of the first mask layer on two sides of the initial third groove are exposed; and taking the second mask layer as a mask, and etching to remove part of the first mask layer, so that the initial first doped layer forms a first doped layer.
15. The method of forming a semiconductor device according to claim 1, wherein the substrate comprises: the substrate, the initial first dabber layer that is located the substrate surface and the initial second dabber layer that is located initial first dabber layer surface.
16. The method of forming a semiconductor device according to claim 15, wherein the substrate further comprises: the first protection layer is formed on the surface of the substrate, and the initial first mandrel layer is positioned on the surface of the first protection layer; forming a second protective layer on the surface of the initial first mandrel layer, wherein the initial second mandrel layer is positioned on the surface of the second protective layer; and forming a third protective layer on the surface of the initial second mandrel layer, wherein the first material layer is positioned on the surface of the third protective layer.
17. The method of forming a semiconductor device according to claim 15, wherein the substrate comprises: a plurality of first regions and second regions located between adjacent first regions; the first mask layer is positioned on the surface of the second material layer in the first area; the first doping mask layer and the second doping mask layer are positioned on the substrate surface of the first region, and the first doping mask layer and the second doping mask layer expose the substrate surface of the second region; the method for forming the semiconductor device further comprises the following steps: etching the initial first mandrel layer by taking the first doping mask layer and the second doping mask layer as masks to form a first mandrel layer, wherein a first opening is formed between adjacent first mandrel layers of the first region, the size of the first opening is a first size, and a second opening is formed between the first mandrel layers of the adjacent first region; forming a first side wall on the side wall of the first mandrel layer, wherein the first side wall fills the first opening, and the first side wall is also positioned on the side wall of the second opening; removing the first mandrel layer after forming the first side wall; after the first mandrel layer is removed, the first side wall is used as a mask, the initial second mandrel layer is etched, a second mandrel layer is formed on the first area substrate, the second mandrel layer is further positioned on the second area substrate, a third opening and a fourth opening are respectively formed on two sides of the second mandrel layer of the first area, and in a first direction parallel to the surface of the substrate, the size of the third opening is a first size, and the size of the fourth opening is a fourth size; forming a second side wall on the side wall of the second mandrel layer, wherein the second side wall is further positioned on the second area substrate, the second side wall covers the third opening and the side wall of the fourth opening, the second side wall has a fifth size, the first size is larger than twice of the fifth size, and the fourth size is larger than twice of the fifth size; removing the second mandrel layer after forming the second side wall; removing the second side wall of the second region after removing the second mandrel layer; and after removing the second side wall of the second region, etching the substrate by taking the second side wall of the first region as a mask, and forming a fin part in the substrate.
18. The method of forming a semiconductor device of claim 17, wherein the second material layer surface of each of the first regions forms 3 separate first mask layers.
19. A semiconductor device formed by the method of any one of claims 1 to 18.
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| US9209038B2 (en) * | 2014-05-02 | 2015-12-08 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits using self-aligned quadruple patterning |
| US9431265B2 (en) * | 2014-09-29 | 2016-08-30 | International Business Machines Corporation | Fin cut for tight fin pitch by two different sit hard mask materials on fin |
| US9934985B2 (en) * | 2015-11-30 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Critical dimension control for double patterning process |
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| US8975129B1 (en) * | 2013-11-13 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a FinFET device |
| CN104658971A (en) * | 2013-11-25 | 2015-05-27 | 台湾积体电路制造股份有限公司 | Method Of Making a FinFET Device |
| CN106486371A (en) * | 2015-08-28 | 2017-03-08 | 联华电子股份有限公司 | A kind of method making semiconductor element |
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