CN112053946A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN112053946A CN112053946A CN201910492662.8A CN201910492662A CN112053946A CN 112053946 A CN112053946 A CN 112053946A CN 201910492662 A CN201910492662 A CN 201910492662A CN 112053946 A CN112053946 A CN 112053946A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
A semiconductor device and a method of forming the same, comprising: providing a substrate; sequentially forming a first material layer and a second material layer on the surface of a substrate; forming first mask layers on the surfaces of the second material layers, wherein a first groove is formed between every two adjacent first mask layers, the first mask layers have a first size, and the first grooves have a second size; forming a first hard doped layer having first ions in the first material layer at the bottom of the first trench; removing the first material layer to form a second groove; thinning the initial first doping layer to form a first doping layer, and forming a second groove into an initial third groove, wherein the first doping layer has a third size, and the initial third groove has a fourth size; forming a first doped mask layer and a second doped mask layer in the second material layer, wherein the first doped mask layer is positioned at the bottom of the second groove, and the second doped mask layer is positioned at the bottom of the initial third groove; and removing the first doping layer and the second material layer to form a third groove. The method improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor technology, the feature size of semiconductor devices is continuously reduced, so that the integration level of integrated circuits is higher and higher, which also puts higher demands on the semiconductor manufacturing process. Etching is an important process in semiconductor manufacturing, and is a process of transferring a pattern on a mask onto a material layer, and as the feature size is continuously reduced, the etching process encounters a bottleneck due to the existence of a wavelength limit in the photoetching process, and etching of a trench with a smaller size cannot be provided.
To achieve smaller pitch dimensions, Multiple Patterning Lithography (MPL) has been developed. Two forms of MPL have been tried, one using repetitive photolithographic processing (photo-etch-photo or LELE) techniques, and the other based on self-aligned spacer processing. The self-aligned spacer process is advantageous when fabricating fins of FinFET structures.
The self-aligned spacer process is commonly referred to as a self-aligned dual process (SADP). In SADP, a set of mandrels is formed photolithographically by patterning and etching a mandrel material. Sidewall spacers may then be formed on the sidewalls of the mandrel. The formation of the sidewall spacers may be accomplished by depositing material over the mandrel material, removing the deposited material on horizontal surfaces, and removing the mandrel material, leaving the sidewall spacers. The deposition of the sidewall spacers may result in a spacer width that is much smaller than the spacer width available for photolithographic formation of the mandrel. The sidewall spacers and mandrels may then be polished to expose the mandrels and spacers that serve as an etch mask to remove the remaining mandrel material. The SADP process involves forming spacers as film layers on the sidewalls of a pre-patterned mandrel, removing the spacer layer from horizontal surfaces, and removing the initially patterned mandrel material while leaving the spacers themselves. Since there are two sidewall spacers per mandrel, the linear density is doubled. Thus, SADP is suitable for defining narrow fins at half the initial lithographic pitch.
However, the pitch of the fins formed by SADP is difficult to adjust due to the limitations of the photolithography process.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a substrate; forming a first material layer on the surface of the substrate; forming a second material layer on the first material layer; forming a plurality of discrete first mask layers on the surface of the second material layer, wherein a first groove is formed between every two adjacent first mask layers, and the first mask layers have a first size and a second size in a first direction parallel to the surface of the substrate; doping first ions in the second material layer at the bottom of the first groove, and forming an initial first doping layer in the second material layer; after an initial first doping layer is formed, removing the second material layer on two sides of the initial first doping layer, and forming a second groove and an initial third groove which are respectively positioned on two sides of the initial first doping layer, wherein the second groove and the initial second groove have a first size in a first direction parallel to the surface of the substrate; after a second groove and an initial third groove are formed, thinning the side wall of the initial first doping layer exposed by the initial third groove to form a first doping layer, so that the initial third groove is formed into a third groove, and in a first direction parallel to the surface of a substrate, the size of the first doping layer is a third size, the third size is smaller than a second size, the third groove is a fourth size, and the fourth size is larger than the first size; doping second ions in the first material layer at the bottom of the second groove, and forming a first doped mask layer in the first material layer; doping second ions in the first material layer at the bottom of the third groove, and forming a second doped mask layer in the first material layer; and after a first doped mask layer and a second doped mask layer are formed, removing the first doped layer and the first material layer to form a fifth groove.
Optionally, the method for forming the initial first doping layer includes: and carrying out first ion doping on the second material layer by taking the first mask layer as a mask, wherein the doping ions of the first ion doping are first ions, so that the second material layer at the bottom of the first groove is formed into an initial first doping layer.
Optionally, the first ion doping process includes: an ion implantation process or a solid source doping process.
Optionally, the first ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, or indium ions.
Optionally, the method for forming the first doped mask layer includes: and ion doping is carried out on the first material layer at the bottom of the second groove by taking the first doping layer as a mask, and the ion-doped doping ions are second ions, so that the first material layer at the bottom of the second groove is formed into a first doping mask layer.
Optionally, the forming method of the second doped mask layer includes: and carrying out ion doping on the first material layer at the bottom of the third groove by taking the first doping layer as a mask, wherein the ion-doped doping ions are second ions, so that the first material layer at the bottom of the third groove is formed into a second doping mask layer.
Optionally, the second doped mask layer is formed in the process of forming the first doped mask layer.
Optionally, the second ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, or indium ions.
Optionally, the method further includes: forming a first isolation layer on the surface of the first material layer, wherein the second material layer is positioned on the surface of the first isolation layer; the second groove and the third groove are exposed out of the surface of the first isolation layer; and after a first doped mask layer and a second doped mask layer are formed, removing the first doped layer, the first isolation layer and the second material layer to form a fifth groove.
Optionally, the method for forming the fifth groove includes: removing the first doped layer; removing the first isolation layer after removing the first doping layer; and removing the second material layer after removing the first isolating layer.
Optionally, the material of the first material layer includes: amorphous silicon, amorphous carbon, polycrystalline silicon, SiCO, or SiCOH.
Optionally, the process of removing the first material layer includes: a dry etching process or a wet etching process.
Optionally, the material of the second material layer includes: amorphous silicon, amorphous carbon, polycrystalline silicon, SiCO, or SiCOH.
Optionally, the method for performing thinning treatment on the sidewall of the initial first doping layer exposed by the initial third trench includes: forming a second mask layer on the surface of the first material layer, wherein the second mask layer is positioned on the surface of part of the initial first doped layer and the surface of part of the second material layer, and exposes the initial third groove and the top surface of part of the first mask layer at two sides of the initial third groove; and etching and removing part of the first mask layer by taking the second mask layer as a mask so as to form a first doping layer on the initial first doping layer.
Optionally, the substrate comprises: the multilayer chip comprises a substrate, an initial first mandrel layer positioned on the surface of the substrate, and an initial second mandrel layer positioned on the surface of the initial first mandrel layer.
Optionally, the substrate further comprises: the first protection layer is formed on the surface of the substrate, and the initial first mandrel layer is positioned on the surface of the first protection layer; forming a second protective layer on the surface of the initial first mandrel layer, wherein the initial second mandrel layer is positioned on the surface of the second protective layer; and forming a third protective layer on the surface of the initial second mandrel layer, wherein the first material layer is positioned on the surface of the third protective layer.
Optionally, the substrate comprises: a plurality of first regions and second regions located between adjacent first regions; the first mask layer is positioned on the surface of the second material layer in the first area; the first doped mask layer and the second doped mask layer are positioned on the surface of the substrate in the first area, and the first doped mask layer and the second doped mask layer are exposed out of the surface of the substrate in the second area; the method for forming the semiconductor device further comprises the following steps: etching the initial first mandrel layer by taking the first doped mask layer and the second doped mask layer as masks to form a first mandrel layer, wherein a first opening is formed between the adjacent first mandrel layers of the first region, the size of the first opening is a first size, and a second opening is formed between the first mandrel layers of the adjacent first regions; forming a first side wall on the side wall of the first mandrel, wherein the first side wall is filled in the first opening and is also positioned on the side wall of the second opening; after the first side wall is formed, removing the first mandrel layer; after the first mandrel layer is removed, etching the initial second mandrel layer by taking the first side wall as a mask, and forming a second mandrel layer on the first area substrate, wherein the second mandrel layer is also positioned on the second area substrate, and both sides of the second mandrel layer of the first area on the second area substrate are respectively provided with a third opening and a fourth opening, and in the first direction parallel to the surface of the substrate, the size of the third opening is the first size, and the size of the fourth opening is the fourth size; forming a second side wall on the side wall of the second mandrel layer, wherein the second side wall is also positioned on the second region substrate, the second side wall covers the third opening and the side wall of the fourth opening, the second side wall has a fifth size, the first size is larger than twice of the fifth size, and the fourth size is larger than twice of the fifth size; after forming the second side wall, removing the second mandrel layer; after the second mandrel layer is removed, removing the second side wall of the second area; and after removing the second side wall of the second area, etching the substrate by taking the second side wall of the first area as a mask, and forming a fin part in the substrate.
Optionally, 3 discrete first mask layers are formed on the surface of the second material layer of each first region.
The invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor device, the first mask layers have the same size and the first grooves have the same size in the first direction parallel to the surface of the substrate, and the method is easy to realize by adopting a photoetching process. And forming an initial first doping layer, a second groove and an initial third groove which are respectively positioned in the initial first doping layer through reverse transmission of the first mask layer. And thinning the sidewall of the initial first doping layer exposed by the initial third groove to form a first doping layer, so that the initial third groove is formed into a third groove, and the sizes of the second groove and the third groove are different. And forming a first doped mask layer, a second doped mask layer and a third groove by reversely transferring the first doped layer, wherein the sizes of the second groove and the third groove are different, and the sizes of the first doped mask layer and the second doped mask layer are also different. And forming an imaging layer of a subsequent SADP process by taking the first doped mask layer and the second doped mask layer as masks, thereby realizing fin parts with different pitches. Thereby improving the performance of the semiconductor device.
Further, the distance between the two second side walls of the side wall of the third opening is the size of the third opening minus the thickness of the two second side walls; the third opening is formed by reverse transfer of the first doped mask layer, and the size of the third opening is equal to that of the first doped mask layer and is the first size. The distance between the two second side walls of the side wall of the fourth opening is the size of the fourth opening minus the thicknesses of the two second side walls; the fourth opening is formed by reverse transfer of the second doped mask layer, and the size of the fourth opening is equal to that of the second doped mask layer and is the fourth size. The distance between the second side walls on the two sides of the second mandrel layer of the first region is the size of the second mandrel layer, the size of the second mandrel layer is formed by reverse transfer of the third groove, the size of the second mandrel layer is equal to the size of the third groove, the third groove is formed by reverse transfer of the first doping layer, and the size of the third groove is equal to the size of the first doping layer and is equal to the third size. Therefore, the fin parts with multiple pitches can be realized by reasonably designing the first size, the third size and the fourth size. Thereby improving the performance of the semiconductor device.
Drawings
Fig. 1 to 15 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the prior art semiconductor devices is poor.
As semiconductor devices have developed, it is desirable to form multiple pitch fins, i.e., the distance between adjacent fins has multiple dimensions. Meanwhile, the size of the fin of the FinFET device is further reduced, and the small-sized fin cannot be realized by using the photolithography technology, but is realized by using the SADP process. However, it is difficult to form multiple pitch fins even by the SADP process. Therefore, semiconductor devices with multiple pitch fins are difficult to implement.
In an embodiment of the present invention, a substrate is provided; sequentially forming a first material layer and a second material layer on the surface of a substrate; forming first mask layers on the surfaces of the second material layers, wherein a first groove is formed between every two adjacent first mask layers, the first mask layers have a first size, and the first grooves have a second size; forming a first hard doped layer having first ions in the first material layer at the bottom of the first trench; removing the first material layer to form a second groove; thinning the initial first doping layer to form a first doping layer, and forming a second groove into an initial third groove, wherein the first doping layer has a third size, and the initial third groove has a fourth size; forming a first doped mask layer and a second doped mask layer in the second material layer, wherein the first doped mask layer is positioned at the bottom of the second groove, and the second doped mask layer is positioned at the bottom of the initial third groove; and removing the first doping layer and the second material layer to form a third groove. And forming a third groove by thinning the initial first doping layer, so that the sizes of the second groove and the initial third groove are different, and forming a first doping mask layer and a second doping mask layer with different sizes by reverse transmission of the first doping layer. And forming fin parts with different intervals by the first doping mask layer and the second doping mask layer with different sizes, wherein the method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 15 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1, a substrate is provided.
In this embodiment, the substrate includes a plurality of first regions I and second regions II located between adjacent first regions I.
In this embodiment, the substrate includes: a substrate 200, an initial first mandrel layer 202 on a surface of the substrate 200, and an initial second mandrel layer 204 on a surface of the initial first mandrel layer 202.
In this embodiment, the substrate further includes: a first protection layer 201 formed on the surface of the substrate 200, wherein the initial first mandrel layer 202 is positioned on the surface of the first protection layer 201; forming a second protective layer 203 on the surface of the initial first mandrel layer 202, wherein the initial second mandrel layer 204 is positioned on the surface of the second protective layer 203; and forming a third protective layer 205 on the surface of the initial second mandrel layer 204.
The substrate 200 is used to provide a material layer for forming the fin.
The substrate 200 includes: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 200 is made of: silicon, the substrate 200 is formed using a selective epitaxy process.
The materials of the first protective layer 201, the second protective layer 203 and the third protective layer 205 include: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
The first protection layer 201, the second protection layer 203 and the third protection layer 205 are etching stop layers.
In this embodiment, the first, second, and third protective layers 201, 203, and 205 are made of silicon oxide.
The material of the initial first mandrel layer 202 includes: amorphous silicon, amorphous carbon, polycrystalline silicon SiCO, or SiCOH.
The material of the initial second mandrel layer 204 includes: amorphous silicon, amorphous carbon, polycrystalline silicon SiCO, or SiCOH. A
In this embodiment, the material of the initial first mandrel layer 202 is polysilicon. The material of the initial second mandrel layer 204 is polysilicon.
With continued reference to fig. 1, a first material layer 210 is formed on the substrate surface; a second material layer 220 is formed on the first material layer 210.
In this embodiment, the first material layer 210 is located on the surface of the third protection layer 205.
In this embodiment, a first isolation layer 211 is formed on the surface of the first material layer 210; the second material layer 220 is located on the surface of the first isolation layer 211.
The first material layer 210 provides a material layer for the subsequent formation of an initial first doped layer.
The second material layer 220 provides a material layer for the subsequent formation of the first doped mask layer and the second doped mask layer.
The material of the first material layer 210 includes: amorphous silicon, amorphous carbon, polycrystalline silicon, SiCO, or SiCOH.
The material of the second material layer 220 includes: amorphous silicon, amorphous carbon, polycrystalline silicon, SiCO, or SiCOH.
In this embodiment, the material of the first material layer 210 is amorphous silicon. The material of the second material layer 220 is amorphous silicon.
The process of forming the first material layer 210 includes: a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the first material layer 210 is a chemical vapor deposition process. In other embodiments, the first material layer is formed using a physical vapor deposition process or an atomic layer deposition process.
The process of forming the second material layer 220 includes: a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the second material layer 220 is a chemical vapor deposition process. In other embodiments, the first material layer is formed using a physical vapor deposition process or an atomic layer deposition process.
Referring to fig. 2, a plurality of discrete first mask layers 230 are formed on the surface of the second material layer 220, a first trench 231 is formed between adjacent first mask layers 230 in the first region I, the first mask layer 230 has a first dimension a along the first direction, and the first trench 231 has a second dimension B along the first direction.
In this embodiment, 3 discrete first mask layers 230 are formed on the surface of the second material layer 220 in each first region I.
The first mask layer 230 exposes the surface of the second material layer 220 in the second region II.
In this embodiment, a sixth trench 232 is formed between the first mask layers 230 adjacent to the first region I.
The sixth groove 232 has a dimension of a seventh dimension C in the first direction parallel to the substrate surface.
In this embodiment, the material of the first mask layer 230 is a photoresist material. In other embodiments, the first mask layer is made of a hard mask layer, and the hard mask layer includes: amorphous carbon, silicon oxide, silicon nitride, or titanium nitride.
The method of forming the first mask layer 230 includes: forming an initial first mask layer on the surface of the second material layer 220; the initial first mask layer is exposed and developed to form the first mask layer 230.
In a first direction parallel to the surface of the substrate, the first mask layers have the same size, and the first grooves have the same size, which is easily realized by adopting a photoetching process.
Referring to fig. 3, first ions are doped in the second material layer 220 at the bottom of the first trench 231, forming an initial first doped layer 241 in the second material layer.
The initial first doped layer 241 has first ions therein.
The dimension of the initial first doped layer 241 is a second dimension B.
The method for forming the initial first doping layer 241 includes: the second material layer 220 is doped with first ions by using the first mask layer 230 as a mask, and the doped ions of the first ion doping are first ions, so that the second material layer 220 at the bottom of the first trench 231 is formed as an initial first doped layer 241.
The first ion doping process comprises the following steps: an ion implantation process or a solid source doping process.
In this embodiment, the first ion doping process is an ion implantation process. In other embodiments, the first ion doping process is a solid source doping process.
The first ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, or indium ions.
In this embodiment, the first ions are boron ions.
The initial first doping layer 241 is formed by doping the second material layer 220 with first ions, and the first ions enter into the ion gap of the second material layer 220, so that the ion state of the initial first doping layer 241 is stable and is not easy to etch.
The initial first doped layer 241 provides a material layer for the subsequent formation of a first doped layer.
In this embodiment, the method further includes: an initial second doped layer 242 is formed within the second material layer 220 of the second region II.
In this embodiment, the initial second doping layer 242 is formed during the formation of the initial first doping layer 241.
In this embodiment, after the initial first doping layer 241 is formed, the first mask layer 230 is removed. The process of removing the first mask layer 230 is an ashing process.
Referring to fig. 4, after the initial first doping layer 241 is formed, the second material layer 220 is removed, and a second trench 221 and an initial third trench 222 respectively located at both sides of the initial first doping layer 241 are formed.
The dimensions of the second groove 221 and the initial third groove 222 are the first dimension a.
The second trenches 221 and the initial third trenches 222 expose the surface of the first isolation layer 211.
The process of removing the second material layer 220 includes: a dry etching process or a wet etching process.
In the process of removing the second material layer 220, the second material layer 220 has a first etching rate, and the initial first doping layer 241 has a second etching rate, and the first etching rate is greater than the second etching rate.
In a specific embodiment, the ratio of the first etching rate to the second etching rate is 5-10.
The first etching rate is greater than the second etching rate, which can ensure that the consumption of the initial first doping layer 241 is less while the second material layer 220 is removed.
In this embodiment, the process of removing the second material layer 220 is a wet etching process; the parameters of the wet etching process comprise: HF and H2A hydrofluoric acid solution with the volume ratio of O being 1/2000-1/100.
The initial first doped layer, the second trench, and the initial third trench are formed by reverse transfer of the first mask layer. Therefore, the size of the initial first doping layer is the same as that of the first groove and is the second size B; the sizes of the second groove and the initial third groove are the same as the size of the first mask layer and are the first size A.
Referring to fig. 5, after forming the second trench 221 and the initial third trench 222, thinning the sidewall of the initial first doping layer 241 exposed by the initial third trench 222 to form a first doping layer 243, so that the initial third trench 222 is formed as a third trench 224, wherein along the first direction, the size of the first doping layer 243 is a third size E, the third size E is smaller than the second size B, and the size of the third trench 224 is a fourth size D; the fourth dimension D is greater than the first dimension a.
The method of thinning the sidewalls of the initial first doping layer 241 exposed by the initial third trenches 222 includes: forming a second mask layer 250 on the surface of the first isolation layer 211, wherein the second mask layer 250 is located on the initial second doping layer 242, a part of the surface of the initial first doping layer 241 and a part of the surface of the second material layer, and exposes the initial third groove 222 and the top surface of the part of the first mask layer 241 at two sides of the initial third groove 222; and etching and removing part of the initial first doping layer 241 by using the second mask layer 250 as a mask, so that the initial first doping layer 241 forms a first doping layer 243.
The process of etching away part of the initial first doping layer 241 includes: anisotropic dry etching process. In this embodiment, the parameters of the dry etching process include: using a gas of CF4、CH2F2、CH3F and O2，CF4The flow rate of (2) is 50sccm to500sccm，CH2F2The flow rate of (C) is 0 to 100sccm, CH3The flow rate of F is 0 to 100sccm, O2The flow rate of the gas source is 10sccm to 100sccm, the source radio frequency power is 50 watts to 500 watts, the bias radio frequency power is 100 watts to 1000 watts, and the pressure of the chamber is 100 millitorr to 200 millitorr.
In this embodiment, the second mask layer 250 is made of photoresist.
The second groove 221 and the initial third groove 222 have the same size, and the third groove 224 has a size larger than that of the initial third groove 222, so that the size of the second groove 221 does not correspond to that of the third groove 224.
In this embodiment, after the first doping layer 243 is formed, the second mask layer 250 is removed. The process of removing the second mask layer 250 is an ashing process.
Referring to fig. 6, second ions are doped in the first material layer 210 at the bottom of the second trench 221 to form a first doped mask layer 251 in the first material layer 210, and second ions are doped in the first material layer 210 at the bottom of the third trench 224 to form a second doped mask layer 252 in the first material layer 210.
The first doped mask layer 251 and the second doped mask layer 252 both have second ions therein.
The method for forming the first doped mask layer 251 includes: and ion doping the first material layer 210 at the bottom of the second trench 221 by using the first doping layer 243 as a mask, wherein the ion-doped doping ions are second ions, so that the first material layer 210 at the bottom of the second trench 221 is formed as a first doping mask layer 251.
The method for forming the second doped mask layer 252 includes: the first material layer 210 at the bottom of the third trench 224 is ion-doped by using the first doping layer 243 as a mask, and the ion-doped doping ions are second ions, so that the first material layer 210 at the bottom of the third trench 224 is formed as a second doping mask layer 252.
In this embodiment, the second doped mask layer 252 is formed during the process of forming the first doped mask layer 251. In other embodiments, after the first doped mask layer is formed, a second doped mask layer is formed or the first doped mask layer is formed after the second doped mask layer is formed.
In this embodiment, the method for forming the first doped mask layer 251 and the second doped mask layer 252 includes: and performing second ion doping on the first material layer 210 by using the first doping layer 243 and the initial second doping layer 242 as masks, where the second ion-doped doping ions are second ions, so that the first material layer 210 at the bottom of the second trench 221 is formed as a first doping mask layer 251, and the first material layer 210 at the bottom of the third trench 224 is formed as a second doping mask layer 252.
The second ion doping process comprises: an ion implantation process or a solid source doping process.
In this embodiment, the second ion doping process is an ion implantation process. In other embodiments, the first ion doping process is a solid source doping process.
The second ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, or indium ions.
In this embodiment, the second ions are boron ions.
The first doped mask layer 251 and the second doped mask layer 252 are formed by doping the first material layer 210 with second ions, and the second ions enter into ion gaps of the first material layer 210, so that the first doped mask layer 251 and the second doped mask layer 252 are stable in ion state and are not easy to etch.
Along a first direction, the size of the first doped mask layer 251 is a first size a; the second doped mask layer 252 has a fourth dimension D, which is greater than the first dimension a.
Referring to fig. 7, after the first doping mask layer 251 and the second doping mask layer 252 are formed, the first doping layer 243 is removed.
In this embodiment, during the process of removing the first doping layer 243, the initial second doping layer 242 is also removed.
The second groove 221 and the third groove 224 expose the first isolation layer 211.
The first isolation layer 211 is made of silicon oxide, and the first doping layer 243 is made of polysilicon doped with boron ions. The materials of the first isolation layer 211 and the first doping layer 243 are different. By properly selecting the etching parameters, it can be ensured that the influence on the first isolation layer 211 is reduced under the condition of removing the first doping layer 243.
The process of removing the first doping layer 243 includes: a dry etching process or a wet etching process.
The process of etching to remove part of the first doped layer 243 includes: anisotropic dry etching process. In this embodiment, the parameters of the dry etching process include: using HBr and O as gas2HBr flow rate of 50sccm to 500sccm, O2The flow rate of the gas is 0 to 100sccm, the source radio frequency power is 50 to 500 watts, the bias radio frequency power is 0 to 50 watts, and the chamber pressure is 50 to 500 mtorr.
Referring to fig. 8, after removing the first doping layer 243, the first isolation layer 211 is removed; after removing the first isolation layer 211, the first material layer 210 is removed, and a fifth trench 253 is formed in the substrate surface of the first region I.
The bottom of the fifth groove 253 exposes the substrate surface of the first region I.
In the first direction, the dimension of the fifth groove 253 is a third dimension E.
The process of removing the first isolation layer 211 includes: a dry etching process or a wet etching process.
The process of removing the first material layer 210 includes: a dry etching process or a wet etching process.
In this embodiment, the process of removing the first material layer 210 is a wet etching process. The parameters of the wet process comprise: HF and H2A hydrofluoric acid solution with the volume ratio of O being 1/2000-1/100.
In the process of removing the first material layer 210, the first material layer 210 has a first etching rate, and the first doped mask layer 251 and the second doped mask layer 252 have a second etching rate, and the first etching rate is greater than the second etching rate.
In a specific embodiment, the ratio of the first etching rate to the second etching rate is 5-20.
The first etching rate is greater than the second etching rate, which can ensure that the first material layer 210 is removed and the consumption of the first doped mask layer 251 and the second doped mask layer 252 is low.
In this embodiment, the substrate further includes a second region II, and the first doped mask layer 251 and the second doped mask layer 252 expose the substrate surface of the second region II.
In this embodiment, a seventh trench 254 is formed between the first doped mask layer 251 and the second doped mask layer 252 adjacent to the first region I.
The dimension of the seventh groove 254 in the first direction parallel to the substrate surface is a seventh dimension C.
By the reverse transfer of the first doping layer 243, the first doping mask layer 251, the second doping mask layer 252 and the third trench 253 are formed, and the first doping mask layer 251 and the second doping mask layer 252 have different sizes in the first direction.
And forming a patterning layer of a subsequent SADP process by using the first doped mask layer 251 and the second doped mask layer 252 as masks, thereby forming fin portions with different pitches. Please refer to fig. 9 to fig. 15.
Referring to fig. 9, the first doped mask layer 251 and the second doped mask layer 252 are used as masks, the initial first mandrel layer 204 is etched to form a first mandrel layer 260, a first opening 261 is formed between the adjacent first mandrel layers 260 in the first region I, and a second opening 262 is formed between the adjacent first mandrel layers 260 in the first region I.
In a first direction parallel to the substrate surface, the first opening 261 has a first dimension a and the second opening 262 has a seventh dimension C.
If the initial first mandrel layer 204 is made of polysilicon, the first mandrel layer 260 is made of polysilicon.
The process of etching the initial first mandrel layer 204 includes: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the first doped mask layer 251 and the second doped mask layer 252 are used as masks, and the third protection layer 205 and the initial first mandrel layer 204 are etched to form a first mandrel layer 260.
The first opening 261 and the second opening 262 expose the surface of the second protective layer 203. The second protection layer 203 is an etching stop layer when the initial first mandrel layer 204 is etched.
Referring to fig. 10, a first sidewall 270 is formed on a sidewall of the first mandrel layer 260, the first opening 261 is filled with the first sidewall 270, and the first sidewall 270 is also located on a sidewall of the second opening 262.
The material of the first sidewall spacers 270 includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
In this embodiment, the first sidewall spacers 270 are made of silicon nitride.
The method for forming the first side wall 270 includes: forming an initial first layer of sidewall material within said first opening 261, within said second opening 262 and on the surface of first mandrel layer 260; and etching back the initial first sidewall material layer until the surface of the first mandrel layer 260, the bottom surfaces of the first opening 261 and the second opening 262 are exposed, so as to form the first sidewall 270.
Referring to fig. 11, after forming the first sidewall spacers 270, the first mandrel layer 260 is removed.
In this embodiment, before removing the first mandrel layer 260, removing the third protection layer 205 on top of the first mandrel layer 260 is further included.
The process of removing the first mandrel layer 260 includes: a dry etching process or a wet etching process.
In this embodiment, the material of the first mandrel layer 260 is polysilicon, and the process of removing the first mandrel layer 260 is a wet etching process.
Referring to fig. 12, after removing the first mandrel layer 260, the initial second mandrel layer 202 is etched using the first sidewall 270 as a mask, and a second mandrel layer 280 is formed on the first region I substrate 200, where the second mandrel layer 280 is also located on the second region II substrate 200.
In this embodiment, the method further includes: etching the second protective layer 203 and the initial second mandrel layer 202 by using the first side wall 270 as a mask; the second mandrel layer 280 is formed.
The second mandrel layer 280 in the first region I has a third opening 281 and a fourth opening 282 on two sides.
In a first direction parallel to the substrate surface, the size of the third opening 281 is a first size a; the fourth opening 282 has a fourth dimension D.
The second region II has a fifth opening 283 between the adjacent second mandrel layers 280.
The fifth opening 283 has a seventh dimension C in the first direction parallel to the substrate surface.
The third opening 281, the fourth opening 282 and the fifth opening 283 expose the surface of the first protection layer 201.
Referring to fig. 13, a second sidewall 290 is formed on the sidewall of the second mandrel layer 280, and the second sidewall 290 is further located on the substrate 200 in the second region II.
In a first direction parallel to the substrate surface, the second sidewall 290 has a fifth dimension e, the first dimension a is greater than twice the fifth dimension e, and the fourth dimension D is greater than twice the fifth dimension e.
The second sidewall 290 covers the sidewalls of the third opening 281, the fourth opening 282 and the fifth opening 283.
The dimension of the second sidewall 290 in the first region I in the first direction parallel to the substrate surface determines the width of the subsequently formed fin. The second sidewalls are positioned in the third and fourth openings 281 and 282, and the size of the third and fourth openings 281 and 282 determines the distance between the second sidewalls 290 positioned in the third opening 281 and the size of the fourth opening 282 determines the distance between the second sidewalls 290 positioned in the fourth opening 282 in the first direction parallel to the substrate surface.
The second sidewalls 290 of the third opening 281 are separated from each other by a first distance a, which is the size of the third opening 281 minus the thickness of the two second sidewalls 290.
In this embodiment, the first distance a is the first dimension a-2 and the fifth dimension e.
The distance between the two second sidewalls 290 of the sidewalls of the fourth opening 282 is a second distance b, which is the size of the fourth opening 282 minus the thickness of the two second sidewalls 290.
In this embodiment, the second distance b is the fourth dimension D-2 and the fifth dimension e.
The distance between the second sidewalls 290 on both sides of the second mandrel layer 280 in the first zone I is a third distance c, and the third distance c is equal to the size of the second mandrel layer 280 in the first zone I.
In this embodiment, the third distance c is equal to the third dimension E.
The material of the second sidewall 290 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
In this embodiment, the second sidewall spacers 290 are made of silicon nitride.
The method for forming the second sidewall spacer 290 includes: forming an initial second sidewall material layer within the third opening 281, within the fourth opening 282, within the fifth opening 283, and on the surface of the second mandrel layer 280; the initial second sidewall material layer is etched back until the surface of the second mandrel layer 280, the bottom surfaces of the third opening 281, the fourth opening 282, and the fifth opening 283 are exposed, so as to form the second sidewall 290.
Referring to fig. 14, after forming the second sidewall 290, the second mandrel layer 280 is removed; after the second mandrel layer 280 is removed, the second sidewall 290 of the second region II is removed.
In this embodiment, before removing the second mandrel layer 280, removing the second protection layer 203 on top of the second mandrel layer 280 is further included.
The process of removing the second mandrel layer 280 includes: a dry etching process or a wet etching process.
The method for removing the second sidewall 290 of the second region II includes: forming a third mask layer on the substrate 200, wherein the third mask layer covers the surface of the second sidewall 290 of the first region I and exposes the second sidewall 290 of the second region II; and removing the second sidewall 290 of the second region II by using the third mask layer as a mask.
The size of the second side wall 290 is a fifth size e, and a first distance a, a second distance b and a third distance c are arranged between adjacent second side walls 290 of the first region I.
Referring to fig. 15, after removing the second sidewall 290 of the second region II, the substrate 200 is etched by using the second sidewall 290 of the first region I as a mask, and a fin 291 is formed in the substrate 200.
The width of the fin 290 is a fifth dimension e.
The spacing between fins 290 includes a first distance a, a second distance b, and a third distance c.
The first distance a is the first dimension a-2 and the fifth dimension e.
The second distance b is the fourth dimension D-2 and the fifth dimension e.
The third distance c is equal to a third dimension E.
Therefore, by adopting the method for forming the semiconductor device provided by the embodiment, the fin portions with multiple pitches can be obtained by reasonably designing the values of the first dimension a, the third dimension E and the fourth dimension D.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a first material layer on the surface of the substrate;
forming a second material layer on the first material layer;
forming a plurality of discrete first mask layers on the surface of the second material layer, wherein a first groove is formed between every two adjacent first mask layers, and the first mask layers have a first size and a second size in a first direction parallel to the surface of the substrate;
doping first ions in the second material layer at the bottom of the first groove, and forming an initial first doping layer in the second material layer;
after an initial first doping layer is formed, removing the second material layer on two sides of the initial first doping layer, and forming a second groove and an initial third groove which are respectively positioned on two sides of the initial first doping layer, wherein the second groove and the initial second groove have a first size in a first direction parallel to the surface of the substrate;
after a second groove and an initial third groove are formed, thinning the side wall of the initial first doping layer exposed by the initial third groove to form a first doping layer, so that the initial third groove is formed into a third groove, and in a first direction parallel to the surface of a substrate, the size of the first doping layer is a third size, the third size is smaller than a second size, the third groove is a fourth size, and the fourth size is larger than the first size;
doping second ions in the first material layer at the bottom of the second groove, and forming a first doped mask layer in the first material layer;
doping second ions in the first material layer at the bottom of the third groove, and forming a second doped mask layer in the first material layer;
and after a first doped mask layer and a second doped mask layer are formed, removing the first doped layer and the first material layer to form a fifth groove.
2. The method according to claim 1, wherein the method for forming the initial first doping layer comprises: and carrying out first ion doping on the second material layer by taking the first mask layer as a mask, wherein the doping ions of the first ion doping are first ions, so that the second material layer at the bottom of the first groove is formed into an initial first doping layer.
3. The method of claim 2, wherein the first ion doping process comprises: an ion implantation process or a solid source doping process.
4. The method according to claim 2, wherein the first ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, or indium ions.
5. The method for forming a semiconductor device according to claim 1, wherein the method for forming the first doped mask layer comprises: and ion doping is carried out on the first material layer at the bottom of the second groove by taking the first doping layer as a mask, and the ion-doped doping ions are second ions, so that the first material layer at the bottom of the second groove is formed into a first doping mask layer.
6. The method for forming a semiconductor device according to claim 1 or 5, wherein the method for forming the second doped mask layer comprises: and carrying out ion doping on the first material layer at the bottom of the third groove by taking the first doping layer as a mask, wherein the ion-doped doping ions are second ions, so that the first material layer at the bottom of the third groove is formed into a second doping mask layer.
7. The method of claim 1, wherein the second doped mask layer is formed during the forming of the first doped mask layer.
8. The method according to claim 1, wherein the second ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, or indium ions.
9. The method for forming a semiconductor device according to claim 1, further comprising: forming a first isolation layer on the surface of the first material layer, wherein the second material layer is positioned on the surface of the first isolation layer; the second groove and the third groove are exposed out of the surface of the first isolation layer; and after a first doped mask layer and a second doped mask layer are formed, removing the first doped layer, the first isolation layer and the second material layer to form a fifth groove.
10. The method for forming a semiconductor device according to claim 9, wherein the method for forming the fifth trench includes: removing the first doped layer; removing the first isolation layer after removing the first doping layer; and removing the second material layer after removing the first isolating layer.
11. The method according to claim 1, wherein the material of the first material layer comprises: amorphous silicon, amorphous carbon, polycrystalline silicon, SiCO, or SiCOH.
12. The method of claim 11, wherein the process of removing the first material layer comprises: a dry etching process or a wet etching process.
13. The method according to claim 1, wherein the material of the second material layer comprises: amorphous silicon, amorphous carbon, polycrystalline silicon, SiCO, or SiCOH.
14. The method of claim 1, wherein thinning the sidewalls of the initial first doped layer exposed by the initial third trench comprises: forming a second mask layer on the surface of the first material layer, wherein the second mask layer is positioned on the surface of part of the initial first doped layer and the surface of part of the second material layer, and exposes the initial third groove and the top surface of part of the first mask layer at two sides of the initial third groove; and etching and removing part of the first mask layer by taking the second mask layer as a mask so as to form a first doping layer on the initial first doping layer.
15. The method of forming a semiconductor device according to claim 1, wherein the substrate comprises: the multilayer chip comprises a substrate, an initial first mandrel layer positioned on the surface of the substrate, and an initial second mandrel layer positioned on the surface of the initial first mandrel layer.
16. The method of forming a semiconductor device according to claim 15, wherein the substrate further comprises: the first protection layer is formed on the surface of the substrate, and the initial first mandrel layer is positioned on the surface of the first protection layer; forming a second protective layer on the surface of the initial first mandrel layer, wherein the initial second mandrel layer is positioned on the surface of the second protective layer; and forming a third protective layer on the surface of the initial second mandrel layer, wherein the first material layer is positioned on the surface of the third protective layer.
17. The method of forming a semiconductor device according to claim 15, wherein the substrate comprises: a plurality of first regions and second regions located between adjacent first regions; the first mask layer is positioned on the surface of the second material layer in the first area; the first doped mask layer and the second doped mask layer are positioned on the surface of the substrate in the first area, and the first doped mask layer and the second doped mask layer are exposed out of the surface of the substrate in the second area; the method for forming the semiconductor device further comprises the following steps: etching the initial first mandrel layer by taking the first doped mask layer and the second doped mask layer as masks to form a first mandrel layer, wherein a first opening is formed between the adjacent first mandrel layers of the first region, the size of the first opening is a first size, and a second opening is formed between the first mandrel layers of the adjacent first regions; forming a first side wall on the side wall of the first mandrel, wherein the first side wall is filled in the first opening and is also positioned on the side wall of the second opening; after the first side wall is formed, removing the first mandrel layer; after the first mandrel layer is removed, etching the initial second mandrel layer by taking the first side wall as a mask, and forming a second mandrel layer on the first area substrate, wherein the second mandrel layer is also positioned on the second area substrate, and both sides of the second mandrel layer of the first area on the second area substrate are respectively provided with a third opening and a fourth opening, and in the first direction parallel to the surface of the substrate, the size of the third opening is the first size, and the size of the fourth opening is the fourth size; forming a second side wall on the side wall of the second mandrel layer, wherein the second side wall is also positioned on the second region substrate, the second side wall covers the third opening and the side wall of the fourth opening, the second side wall has a fifth size, the first size is larger than twice of the fifth size, and the fourth size is larger than twice of the fifth size; after forming the second side wall, removing the second mandrel layer; after the second mandrel layer is removed, removing the second side wall of the second area; and after removing the second side wall of the second area, etching the substrate by taking the second side wall of the first area as a mask, and forming a fin part in the substrate.
18. The method as claimed in claim 1, wherein 3 discrete first mask layers are formed on the surface of the second material layer of each first region.
19. A semiconductor device formed by the method of any one of claims 1 to 18.
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