CN113782428A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113782428A
CN113782428A CN202010518370.XA CN202010518370A CN113782428A CN 113782428 A CN113782428 A CN 113782428A CN 202010518370 A CN202010518370 A CN 202010518370A CN 113782428 A CN113782428 A CN 113782428A
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layer
etched
side wall
forming
top surface
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CN113782428B (en
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王智东
张昕哲
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched, a core layer positioned on the layer to be etched and side walls positioned on two sides of the core layer, and the top surfaces of the side walls are cambered surfaces; and forming a supplement structure on the top surface of the side wall to completely cover the arc surface, wherein the top surface of the supplement structure is a flat plane. Because the top surface is a flat plane rather than an arc surface when the complementary structure and the side wall are jointly used as the etching mask, the phenomenon that the depth of a graph formed on the layer to be etched is different because the top surface of the side wall is an arc surface when the side wall is used as the etching mask is avoided, the graph with the same structure line depth is favorably formed on the layer to be etched, and the accuracy and the stability of graph transfer are improved; the method for forming the semiconductor structure is suitable for any manufacturing process needing pattern transfer, simple in process and capable of improving practicability.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In a semiconductor integrated circuit fabrication process, a series of processes, such as deposition, photolithography, etching, and planarization processes, are used to form a semiconductor structure. Among them, photolithography and etching are the main patterning means in the semiconductor manufacturing process.
The photolithography process generally includes forming a photosensitive material layer (e.g., a photoresist layer) on a substrate, and then transferring a pattern on a mask plate (mask) onto the photosensitive material layer by exposure, so as to form a pattern in the photosensitive material layer to form a patterned mask layer and define an area to be etched; in the etching process, the mask layer is usually used as a mask, and a region to be etched in the layer to be etched is etched, so that a pattern in the mask layer is transferred into the layer to be etched, and a required structure is formed in the layer to be etched.
With the continuous development of super-large integrated circuits, the Critical Dimension (CD) of semiconductor devices is continuously reduced, and the influence of the photolithography process on the device performance is more and more obvious. Therefore, under the condition that the critical dimension is smaller and smaller, how to improve the precision and stability of the pattern transfer becomes a research hotspot in the industry.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can improve the precision and stability of pattern transfer.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched, a core layer positioned on the layer to be etched and side walls positioned on two sides of the core layer, and the top surfaces of the side walls are cambered surfaces;
and forming a supplement structure on the top surface of the side wall, wherein the top surface of the supplement structure is a flat plane.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including:
the structure of the layer to be etched comprises the layer to be etched and a side wall positioned on the layer to be etched, wherein the top surface of the side wall is an arc surface;
and the supplement structure is positioned on the top surface of the side wall and completely covers the top surface, and the top surface of the supplement structure is a flat plane.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the method for forming the semiconductor structure, the complementary structure with the flat top surface is formed on the arc-shaped top surface of the side wall to completely cover the arc surface, and then the complementary structure and the side wall are used as the etching mask to etch the layer to be etched to form the target graph structure. Because the top surface is a flat plane rather than an arc surface when the complementary structure and the side wall are jointly used as the etching mask, the phenomenon that the depth of a graph formed on the layer to be etched is different because the top surface of the side wall is an arc surface when the side wall is used as the etching mask is avoided, the graph with the same structure line depth is favorably formed on the layer to be etched, and the accuracy and the stability of graph transfer are improved; the method for forming the semiconductor structure is suitable for any manufacturing process needing pattern transfer, simple in process and capable of improving practicability.
In an alternative scheme, the side wall and the complementary structure can be etched to obtain the side wall with the preset width and the complementary structure with the preset width, and the accuracy of pattern transfer is further improved.
Drawings
FIGS. 1-3 are schematic diagrams of a method of forming a semiconductor structure;
fig. 4 to fig. 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the accuracy and stability of pattern transfer are not good when the critical dimension is smaller. The method combines the reasons of poor precision and stability of pattern transfer analysis of a semiconductor structure.
Referring to fig. 1-3, fig. 1-3 are schematic structural views illustrating a method for forming a semiconductor structure.
As shown in fig. 1, in a process for forming a semiconductor body structure, the method comprises the following steps:
providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer 201 to be etched, and a core layer 202 is formed on the layer 201 to be etched;
conformally covering a side wall material layer 203a on the core layer 202 and the layer to be etched exposed from the core layer 202;
and removing the top of the core layer 202 and the side wall material layer 203a on the layer to be etched 201 exposed from the core layer 202, and taking the remaining side wall material layer on the side wall of the core layer as a side wall 203. The top surface of the formed sidewall 203 is an arc surface under the influence of the sidewall forming process, and when the sidewall 203 is subsequently etched downwards by using the sidewall 203 as an etching mask, the line depth H1 of the etched first groove and the line depth H2 of the etched second groove are inconsistent, so that the process effect of the subsequent patterning process and the precision of pattern transfer are poor.
In order to improve the precision and stability of pattern transfer, the embodiment of the invention provides a semiconductor structure and a forming method thereof. Because the top surface is a flat plane rather than an arc surface when the complementary structure and the side wall are jointly used as the etching mask, the phenomenon that the depth of a graph formed on the layer to be etched is different because the top surface of the side wall is an arc surface when the side wall is used as the etching mask is avoided, the graph with the same structure line depth is favorably formed on the layer to be etched, and the accuracy and the stability of graph transfer are improved; the method for forming the semiconductor structure is suitable for any manufacturing process needing pattern transfer, simple in process and capable of improving practicability.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Referring to fig. 4-11, fig. 4-11 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention. The semiconductor structure provided by the embodiment of the invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 4-5, a layer-to-be-etched structure 10 (shown in fig. 5) is provided, the layer-to-be-etched structure including a layer-to-be-etched, a core layer on the layer-to-be-etched, and sidewalls on both sides of the core layer, the sidewalls having top surfaces with arc surfaces.
The layer structure to be etched is formed on the substrate. The base may include a substrate 100. The substrate 100 may be made of silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, and may be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or the like. The material of the substrate may be a material suitable for process requirements or easy integration.
The step of forming the layer structure to be etched comprises the following steps:
and providing a layer to be etched 101, wherein the layer to be etched 101 is an etching object of a subsequent etching process and is used for forming a target graph structure.
In an embodiment, the layer to be etched 101 may be used to form a gate structure, a forming process of the layer to be etched 101 may be an atomic layer deposition process or a chemical vapor deposition process, and a material of the layer to be etched 101 may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In another embodiment, the layer to be etched may also be used to form the fin, and the material of the layer to be etched may be single crystal silicon or polycrystalline silicon.
A core layer 102 is formed on the layer to be etched 101, and the core layer 102 provides a process basis for forming a sidewall subsequently.
The material of the core layer 102 may be single crystalline silicon, polycrystalline silicon, or amorphous carbon.
A side wall material layer 103a is conformally covered on the core layer 102 and the layer to be etched 101 exposed from the core layer 102.
In this embodiment, the sidewall material Layer 103a is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process has good conformal covering capability, is favorable for ensuring that the side wall material layer can be conformally covered on the core layer and the layer to be etched, which is exposed out of the core layer, in the step of forming the side wall material layer, and is favorable for improving the thickness uniformity of the side wall material layer and correspondingly favorable for improving the thickness uniformity of the subsequently formed side wall by adopting the atomic layer deposition process. In other embodiments, the sidewall material layer may also be formed by a Chemical Vapor Deposition (CVD) process.
Then, the top of the core layer 102 and the exposed side wall material layer 103a on the layer to be etched of the core layer 102 are removed, and the remaining side wall material layer on the side wall of the core layer 102 is used as the side wall 103. The material of the sidewall spacers 103 may be one or a combination of at least two of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
In this embodiment, the material of the sidewall 103 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process cost, has simple removal process, is not easy to have residues, and is prepared for subsequent removal.
In this embodiment, a maskless etching process is used to remove the top end of the core layer 102 and the sidewall material layer 103a on the layer to be etched 101, so as to form the sidewall 103. And a Mask (Mask) is not needed by adopting the maskless etching process, so that the process cost is reduced. Of course, in other embodiments, other processes may be used to form the sidewall spacers.
Specifically, a maskless dry etching process is adopted for etching, the dry etching process has the characteristic of anisotropic etching, so that the damage to other film layer structures is small while the top of the core layer and the side wall material layer on the layer to be etched are completely removed, and the phenomenon that the thickness of the formed side wall is not easy to thin due to the fact that the side wall material layer is transversely etched is avoided, so that the side wall can play a role in etching a mask in the subsequent step of forming a target pattern.
Under the influence of the sidewall generation process, the top surface of the obtained sidewall 103 is an arc surface (as shown in fig. 5), and in order to avoid the accuracy reduction of the subsequent pattern transfer, the method for forming the semiconductor structure provided by the embodiment of the present invention further includes the following steps after the sidewall is formed:
referring to fig. 6 to 8, after the sidewall 103 is formed, a complementary structure is formed on the top surface of the sidewall 103 to completely cover the arc surface, and the top surface of the complementary structure is a flat plane.
And forming a supplement structure with a flat top surface on the arc-shaped top surface of the side wall to completely cover the arc surface, and subsequently etching the layer to be etched by using the supplement structure and the side wall as an etching mask together to form a target pattern structure. Because the top surface is a flat plane rather than an arc surface when the complementary structure and the side wall are jointly used as the etching mask, the phenomenon that the depth of a graph formed on the layer to be etched is different because the top surface of the side wall is an arc surface when the side wall is used as the etching mask is avoided, the graph with the same structure line depth is favorably formed on the layer to be etched, and the accuracy and the stability of graph transfer are improved; the method for forming the semiconductor structure is suitable for any manufacturing process needing pattern transfer, simple in process and capable of improving practicability.
The formation process of the complementary structure is not limited as long as the complementary structure having a flat top surface can be formed. In one embodiment, the complementary structure with a planar top surface can be formed by ion treatment, which may include ion implantation, ion beam mixing, ion sputtering, and the like.
In this embodiment, in order to facilitate forming the supplemental structure 104, the forming process of the supplemental structure 104 is an ion implantation process.
In order to ensure that the complementary structure 104 with a plane top surface is formed on the sidewall 103 with a cambered top surface, the included angle between the ion implantation direction and the surface normal of the layer to be etched cannot be too large or too small, and the complementary structure cannot be ensured to completely cover the cambered surface of the sidewall when the included angle is too large or too small. Therefore, in this embodiment, the angle between the direction of ion implantation and the normal of the surface of the layer to be etched 101 is 30 ° to 60 °, for example, the angle between the direction of ion implantation and the normal of the surface of the layer to be etched may be 35 °, 30 °, 45 °, 50 °, or 55 °.
In this embodiment, the material of the sidewall 103 is silicon oxide. The ion implanted ions may be one of germanium ions, silicon ions, boron ions, carbon ions, phosphorus ions, or a combination of at least two of the foregoing. When the ion beam strikes the surface of the side wall, the ion beam and the surface of the side wall generate a series of physical and chemical interactions to form a new surface layer (namely a supplement structure), and the ion implantation process ensures that the problem of peeling between the supplement structure and the side wall does not exist.
As shown in fig. 5, the arc surface of the sidewall of the first side of the core layer and the arc surface of the sidewall of the second side of the core layer are symmetrical with respect to the normal of the core layer (dotted line in fig. 5). Specifically, a step of forming a complementary structure 104 on the top surface of the sidewall 103, where the top surface of the complementary structure 104 is a flat plane:
as shown in fig. 6, first, a first supplemental structure 1041 is formed on a top surface of a sidewall on a first side of the core layer 102, where the top surface of the first supplemental structure 1041 is a flat plane;
when the ion beam hits the surface of the side wall 103 on the first side of the core layer, a series of physical and chemical interactions between the ion beam and the surface of the side wall 103 occur to form a new first supplemental structure 1041 covering at least the top surface of the side wall on the first side of the core layer.
Next, as shown in fig. 7, a second supplemental structure 1042 is formed on the top surface of the sidewall on the second side of the core layer 102, and the top surface of the second supplemental structure 1042 is a flat plane.
When the ion beam hits the surface of the sidewall 103 on the second side of the core layer, a series of physical and chemical interactions between the ion beam and the surface of the sidewall occur to form a new second complementary structure 1042 covering at least the top surface of the sidewall on the second side of the core layer.
As shown in fig. 8, the first supplemental structure 1041 and the second supplemental structure 1042 together constitute the supplemental structure 104.
As shown in fig. 9, since the formation of the complementary structure 104 may cause the width of the sidewall and the complementary structure to be increased when the entire sidewall and the complementary structure are used as a subsequent etching mask, which eventually causes the distance between the adjacent target pattern structures (e.g., gate structures) to be reduced, and further easily causes the leakage of the semiconductor structure, in a specific embodiment, after the formation of the complementary structure on the top surface of the sidewall 103, the method may further include:
and etching the side wall 103 and the complementary structure 104 to make the side wall 103 and the complementary structure 104 have a predetermined width.
It should be noted that the predetermined width refers to a preset width of the etching mask, that is, the entire width of the side wall on the first side of the core layer and the first supplemental structure, or the entire width of the side wall on the second side of the core layer and the second supplemental structure when the layer to be etched is subsequently etched by using the side wall and the supplemental structure as the mask.
In this embodiment, the sidewall 103 and the complementary structure 104 are etched by a dry etching process. In order to avoid the influence on other structural layers in the process of etching the side wall and supplementing the structure, the etching gas can be oxygen (O)2) And sulfur dioxide (SO)2) At least one of (a). Because of O2And SO2The silicon-containing structure layer is not affected, so that the stability of other structure layers can be ensured.
Of course, in other embodiments, the width of the pre-formed sidewall may also be set to be narrower than the width of the subsequent etching mask, so that after the complementary structure is formed subsequently, the overall width of the first complementary structure and the sidewall or the overall width of the second complementary structure and the sidewall meets the accuracy requirement of the etching mask width.
With continued reference to fig. 10, after forming the supplemental structure, the method for forming a semiconductor structure according to the embodiment of the present invention further includes:
the core layer 102 (shown in fig. 9) is removed.
In this embodiment, the core layer is removed by a dry etching process. And in the process of removing the core layer by using a dry etching process, taking the layer to be etched as an etching stop layer. The dry etching process can improve the process compatibility, does not need to replace a machine table, and is favorable for improving the working efficiency. In other embodiments, an ashing process may also be used to remove the core layer.
The material of the core layer and the material of the subsequently formed side wall have etching selectivity, and the probability of damage to the side wall is low in the subsequent process of removing the core layer.
In one embodiment, the material of the core layer may be amorphous carbon. The amorphous carbon is an organic material, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the core layer, has simple removal process and is not easy to have residues, and is prepared for removing the core layer subsequently. In other embodiments, the material of the core layer may also be silicon oxide or polysilicon.
With continuing reference to fig. 11, after removing the core layer, the method for forming a semiconductor structure according to the embodiment of the present invention further includes:
and etching the layer to be etched by taking the side wall and the complementary structure as masks to form a target pattern structure 106.
Specifically, the complementary structure and the side wall are used as an etching mask together, so that the complementary structure and the side wall can be used for any process in the forming process of the semiconductor structure. Thus, in one embodiment, the layer to be etched may comprise a structural layer of gate material.
The gate material structure layer provides for subsequent formation of a gate structure that spans the fin.
The gate material structure layer may be a stacked structure, and the gate material structure layer includes a gate oxide material layer (not shown) conformally covering the fin portion and a gate material layer (not shown) on the gate oxide material layer. In other embodiments, the gate material structure layer may also be a single-layer structure, that is, the gate material structure layer only includes the gate material layer.
In this embodiment, the gate oxide layer may be made of silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride. In this embodiment, the gate material layer is made of polysilicon. In other embodiments, the material of the gate material layer may also be amorphous carbon.
Specifically, the step of forming the gate material structure layer includes: forming a gate oxide material layer which conformally covers the surface of the fin part; and forming a gate oxide material layer, and then forming the gate material layer on the gate oxide material layer.
The step of etching the layer to be etched by using the side wall and the complementary structure as masks to form the target pattern structure 106 includes:
and etching the gate material structure layer by taking the side wall and the complementary structure as masks to form a gate structure, and taking the gate structure as the target pattern structure 106.
In another embodiment, the layer to be etched may comprise a silicon substrate layer;
the step of etching the layer to be etched by taking the side wall and the complementary structure as masks to form a target pattern structure comprises the following steps:
and etching the substrate by taking the side wall and the complementary structure as masks to form discrete fins, wherein the discrete fins are taken as the target graphic structure.
In other embodiments, the step of etching the layer to be etched with the side wall and the complementary structure as masks to form the target pattern structure may further include:
forming a dielectric layer on the substrate, wherein the dielectric layer covers the grid material structure layer;
the step of etching the layer to be etched comprises: and etching the dielectric layer and the gate material structure layer by taking the side wall and the complementary structure as masks to form a gate structure, wherein the gate structure is taken as the target pattern structure.
It should be noted that, in the process of etching the gate material structure layer to form the gate structure, after the sidewall and the complementary structure are completely consumed, the dielectric layer is used as a mask to continuously etch the gate material structure.
The dielectric layer is made of at least one of silicon nitride, silicon oxide or silicon oxynitride.
It should be noted that the layer to be etched is not limited to forming the gate structure and the fin, but may be any layer structure in the process that needs to perform pattern transfer.
In order to solve the above problem, embodiments of the present invention further provide a semiconductor structure.
Referring to fig. 10, a semiconductor structure provided in an embodiment of the invention includes:
the method comprises the steps of etching a layer structure to be etched, wherein the layer structure to be etched comprises a layer 101 to be etched and a side wall 103 positioned on the layer 101 to be etched, and the top surface of the side wall 103 is an arc surface;
and the complementary structure 104 is positioned on the top surface of the side wall 103 and completely covers the top surface, and the top surface of the complementary structure 104 is a flat plane.
The layer to be etched 101 is an etching object of a subsequent etching process and is used for forming a target pattern structure.
The material of the sidewall spacers 103 may include one or at least two of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The material of the supplemental structure 104 may include at least one of germanium oxide, silicon oxide, boron oxide, or an oxygen-containing species of phosphorus.
In one embodiment, the layer to be etched 101 may include a gate material structure layer, and a gate structure may be formed subsequently, with the gate structure as the target pattern structure.
In other embodiments, the layer to be etched may also be a dielectric layer formed on the substrate, and the dielectric layer covers the gate material structure layer;
in another embodiment, the layer to be etched may comprise a silicon substrate layer;
and etching the substrate by taking the side wall and the complementary structure as masks to form discrete fins, wherein the discrete fins are taken as the target graphic structure.
In this embodiment, the layer structure to be etched is formed on a base, and the base may include the silicon substrate 100. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
It should be noted that the layer to be etched is not limited to forming the gate structure and the fin, but may be any layer structure in the process that needs to perform pattern transfer.
According to the semiconductor structure provided by the embodiment of the invention, because the supplement structure with the flat top surface is formed on the arc-shaped top surface of the side wall and completely covers the arc surface, the supplement structure and the side wall are used as the etching mask to etch the layer to be etched in the following process, when the target graph structure is formed, because the supplement structure and the side wall are used as the etching mask together, the top surface is the flat surface and not the arc surface, the difference of the depth of the graph formed on the layer to be etched can be avoided when the side wall is used as the etching mask because the top surface of the side wall is the arc surface, the graph with the same structure line depth can be formed on the layer to be etched, and the accuracy and the stability of graph transfer are improved; the semiconductor structure provided by the embodiment of the invention is suitable for any processing procedure needing pattern transfer, has simple process and improves the practicability.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched, a core layer positioned on the layer to be etched and side walls positioned on two sides of the core layer, and the top surfaces of the side walls are cambered surfaces;
and forming a supplementary structure on the top surface of the side wall to completely cover the cambered surface, wherein the top surface of the supplementary structure is a flat plane.
2. The method of claim 1, wherein the complementary structure is formed by an ion implantation process, and the ion implantation direction is in a range of 30 ° to 60 ° from the normal of the surface of the layer to be etched.
3. The method of claim 2, wherein the ion implantation comprises one or a combination of at least two of germanium ions, silicon ions, boron ions, carbon ions, and phosphorus ions.
4. The method of claim 1, wherein the arc surfaces of the sidewall spacer on the first side of the core layer and the arc surfaces of the sidewall spacer on the second side of the core layer are symmetrical with respect to the core layer, and the step of forming the supplemental structure on the top surface of the sidewall spacer, wherein the step of forming the supplemental structure with the top surface being a flat plane comprises:
forming a first complementary structure on the top surface of the side wall on the first side of the core layer, wherein the top surface of the first complementary structure is a flat plane;
and forming a second supplementary structure on the top surface of the side wall positioned on the second side of the core layer, wherein the top surface of the second supplementary structure is a flat plane.
5. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the supplemental structure on the top surface of the sidewall spacer, the step of forming the supplemental structure having a flat top surface further comprises:
and etching the side wall and the complementary structure to enable the side wall and the complementary structure to have a preset width.
6. The method of claim 5, wherein an etching gas used to etch the sidewalls and the supplemental structure comprises at least one of oxygen and sulfur dioxide.
7. The method for forming a semiconductor structure according to claim 1, wherein the forming of the supplemental structure on the top surface of the sidewall spacer further comprises, after the top surface of the supplemental structure is a flat plane:
and removing the core layer.
8. The method of forming a semiconductor structure of claim 7, wherein after removing the core layer, further comprising:
and etching the layer to be etched by taking the side wall and the complementary structure as masks to form a target pattern structure.
9. The method for forming a semiconductor structure according to claim 8, wherein the layer to be etched includes a gate material structure layer, and the step of etching the layer to be etched using the sidewall spacers and the supplemental structure as masks to form a target pattern structure includes:
and etching the grid material structure layer by taking the side wall and the complementary structure on the side wall as masks to form a grid structure, and taking the grid structure as the target pattern structure.
10. The method for forming a semiconductor structure according to claim 9, wherein the step of etching the layer to be etched using the sidewalls and the complementary structures on the sidewalls as masks to form the target pattern structure further comprises:
forming a dielectric layer, wherein the dielectric layer covers the grid material structure layer;
the step of etching the layer to be etched comprises: and etching the dielectric layer and the grid material structure layer by taking the side wall and the complementary structure on the side wall as masks to form a grid structure, wherein the grid structure is taken as the target pattern structure.
11. The method of claim 10, wherein a material of the dielectric layer comprises at least one of silicon nitride, silicon oxide, or silicon oxynitride.
12. The method of forming a semiconductor structure of claim 8, wherein the layer to be etched comprises a silicon substrate layer;
the step of etching the layer to be etched by taking the side wall and the complementary structure on the side wall as masks to form a target pattern structure comprises the following steps:
and etching the silicon substrate layer by taking the side wall and the complementary structure on the side wall as masks to form discrete fins, wherein the discrete fins are taken as the target graphic structure.
13. The method of forming a semiconductor structure, as recited in any of claims 1-12, wherein the step of forming the layer-to-be-etched structure comprises:
providing a layer to be etched;
forming a core layer on the layer to be etched;
conformally covering a side wall material layer on the core layer and the layer to be etched exposed out of the core layer;
and removing the top of the core layer and the side wall material layer on the layer to be etched exposed out of the core layer, and taking the residual side wall material layer positioned on the side wall of the core layer as a side wall.
14. The method for forming a semiconductor structure according to any one of claims 1 to 12, wherein a material of the sidewall spacers includes one or at least two of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
15. The method of forming a semiconductor structure of any of claims 1-12, wherein the material of the core layer comprises single crystal silicon, polycrystalline silicon, or amorphous carbon.
16. A semiconductor structure, comprising:
the etching method comprises the steps of etching a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched and a side wall positioned on the layer to be etched, and the top surface of the side wall is an arc surface;
and the supplement structure is positioned on the top surface of the side wall and completely covers the top surface, and the top surface of the supplement structure is a flat plane.
17. The semiconductor structure of claim 16, wherein the material of the sidewall spacers comprises one or at least two of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
18. The semiconductor structure of claim 16, wherein a material of the supplemental structure is at least one of germanium oxide, silicon oxide, boron oxide, or an oxygen-containing species of phosphorus.
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