CN113782428B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113782428B
CN113782428B CN202010518370.XA CN202010518370A CN113782428B CN 113782428 B CN113782428 B CN 113782428B CN 202010518370 A CN202010518370 A CN 202010518370A CN 113782428 B CN113782428 B CN 113782428B
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layer
side wall
etched
forming
top surface
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CN113782428A (en
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王智东
张昕哲
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched, a core layer positioned on the layer to be etched and side walls positioned on two sides of the core layer, and the top surface of the side walls is a cambered surface; and forming a supplementary structure on the top surface of the side wall so as to completely cover the cambered surface, wherein the top surface of the supplementary structure is a flat plane. The top surface is a flat plane instead of an arc surface when the complementary structure and the side wall are used as an etching mask together, so that the situation that the patterns formed on the layer to be etched are different in depth due to the fact that the top surface of the side wall is the arc surface when the side wall is used as the etching mask is avoided, patterns with the same structure line depth are formed on the layer to be etched, and the accuracy and the stability of pattern transfer are improved; the method for forming the semiconductor structure is suitable for any process requiring pattern transfer, is simple in process and improves practicality.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the semiconductor integrated circuit manufacturing process, a series of processes such as deposition, photolithography, etching, and planarization processes are employed to form a semiconductor structure. Among them, photolithography and etching are the main patterning means in the semiconductor manufacturing process.
The photolithography process generally forms a photosensitive material layer (e.g., photoresist layer) on a substrate, and then transfers a pattern on a mask plate (mask) onto the photosensitive material layer through exposure, so as to form a pattern in the photosensitive material layer, so as to form a patterned mask layer, and define a region to be etched; the etching process generally uses the mask layer as a mask to etch the region to be etched in the layer to be etched, so that the pattern in the mask layer is transferred to the layer to be etched, and a required structure is formed in the layer to be etched.
With the continued development of ultra-large integrated circuits, the critical dimensions (critical dimension, CD) of semiconductor devices are continually reduced, and the impact of lithographic processes on device performance is becoming more and more pronounced. Therefore, with smaller and smaller critical dimensions, how to improve the accuracy and stability of pattern transfer is a research hotspot in the industry.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the accuracy and stability of pattern transfer.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched, a core layer positioned on the layer to be etched and side walls positioned on two sides of the core layer, and the top surface of the side wall is a cambered surface;
and forming a supplement structure on the top surface of the side wall, wherein the top surface of the supplement structure is a flat plane.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises:
the structure of the layer to be etched comprises a layer to be etched, and a side wall positioned on the layer to be etched, wherein the top surface of the side wall is a cambered surface;
the supplementing structure is positioned on the top surface of the side wall and completely covers the top surface, and the top surface of the supplementing structure is a flat plane.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the method for forming the semiconductor structure, the complementary structure with the flat top surface is formed on the arc-shaped top surface of the side wall so as to completely cover the arc surface, and then the complementary structure and the side wall are used as an etching mask together to etch the layer to be etched, so that the target pattern structure is formed. The top surface is a flat plane instead of an arc surface when the complementary structure and the side wall are used as an etching mask together, so that the situation that the patterns formed on the layer to be etched are different in depth due to the fact that the top surface of the side wall is the arc surface when the side wall is used as the etching mask is avoided, patterns with the same structure line depth are formed on the layer to be etched, and the accuracy and the stability of pattern transfer are improved; the method for forming the semiconductor structure is suitable for any process requiring pattern transfer, is simple in process and improves practicality.
In an alternative scheme, the side wall and the complementary structure can be etched to obtain the side wall with the preset width and the complementary structure with the preset width, so that the accuracy of pattern transfer is further improved.
Drawings
FIGS. 1-3 are schematic diagrams of a method of forming a semiconductor structure;
fig. 4 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the accuracy and stability of pattern transfer are poor under the condition that the critical dimension is smaller and smaller. The reasons for poor accuracy and stability of pattern transfer are analyzed by combining a semiconductor structure.
Referring to fig. 1-3, fig. 1-3 are schematic structural views of a method for forming a semiconductor structure.
As shown in fig. 1, in a process of forming a semiconductor body structure, the method includes the following steps:
providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer 201 to be etched, and forming a core layer 202 on the layer 201 to be etched;
conformally covering a side wall material layer 203a on the core layer 202 and the layer to be etched exposed from the core layer 202;
and removing the top of the core layer 202 and the sidewall material layer 203a on the layer 201 to be etched exposed by the core layer 202, and taking the remaining sidewall material layer on the sidewall of the core layer as the sidewall 203. The top surface of the formed side wall 203 is an arc surface under the influence of the side wall forming process, and when the side wall 203 is used as an etching mask for downward etching in the follow-up process, the line depth H1 of the etched first groove is inconsistent with the line depth H2 of the etched second groove, so that the process effect of the follow-up patterning process and the pattern transferring precision are poor.
In order to improve the accuracy and stability of pattern transfer, the embodiment of the invention provides a semiconductor structure and a forming method thereof, wherein a complementary structure with a flat top surface is formed on the arc-shaped top surface of a side wall so as to completely cover the arc surface, and then the complementary structure and the side wall are used as an etching mask to etch the layer to be etched together to form a target pattern structure. The top surface is a flat plane instead of an arc surface when the complementary structure and the side wall are used as an etching mask together, so that the situation that the patterns formed on the layer to be etched are different in depth due to the fact that the top surface of the side wall is the arc surface when the side wall is used as the etching mask is avoided, patterns with the same structure line depth are formed on the layer to be etched, and the accuracy and the stability of pattern transfer are improved; the method for forming the semiconductor structure is suitable for any process requiring pattern transfer, is simple in process and improves practicality.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Referring to fig. 4-11, fig. 4-11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention. The following describes a semiconductor structure provided by an embodiment of the present invention in detail with reference to the accompanying drawings.
Referring to fig. 4-5, a layer structure to be etched 10 (shown in fig. 5) is provided, where the layer structure to be etched includes a layer to be etched, a core layer located on the layer to be etched, and side walls located on two sides of the core layer, and top surfaces of the side walls are cambered surfaces.
The layer structure to be etched is formed on the substrate. The base may include a substrate 100. The material of the substrate 100 may be silicon, germanium, silicon carbide, gallium arsenide, indium gallium carbide, or the like, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
The step of forming the layer structure to be etched comprises the following steps:
the method comprises the steps of providing a layer 101 to be etched, wherein the layer 101 to be etched is an etching object of a subsequent etching process and is used for forming a target pattern structure.
In one embodiment, the layer to be etched 101 may be used to form a gate structure, the forming process of the layer to be etched 101 may be an atomic layer deposition process or a chemical vapor deposition process, and the material of the layer to be etched 101 may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In another embodiment, the layer to be etched may also be used to form the fin, and the material of the layer to be etched may be monocrystalline silicon or polycrystalline silicon.
A core layer 102 is formed on the layer 101 to be etched, and the core layer 102 provides a process basis for forming a sidewall subsequently.
The material of the core layer 102 may be monocrystalline silicon, polycrystalline silicon, or amorphous carbon.
And conformally covering the core layer 102 and the side wall material layer 103a on the layer 101 to be etched, wherein the layer 101 is exposed from the core layer 102.
In this embodiment, an atomic layer deposition process (Atomic Layer Deposition, ALD) is used to form the sidewall material layer 103a. The atomic layer deposition process has good conformal coverage capability, is favorable for ensuring that the side wall material layer can be conformally covered on the core layer and the layer to be etched exposed from the core layer in the step of forming the side wall material layer, and is favorable for improving the thickness uniformity of the side wall material layer and correspondingly favorable for improving the thickness uniformity of the side wall formed subsequently by adopting the atomic layer deposition process. In other embodiments, the sidewall material layer may also be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
And then, removing the top of the core layer 102 and the sidewall material layer 103a on the layer to be etched exposed from the core layer 102, and taking the remaining sidewall material layer on the sidewall of the core layer 102 as the sidewall 103. The material of the side wall 103 may be one or a combination of at least two of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.
In this embodiment, the material of the sidewall 103 is silicon oxide. The silicon oxide is a dielectric material with common process and lower cost, has higher process compatibility, is beneficial to reducing the process cost, has simple removal process of the silicon oxide, is not easy to have residues, and is prepared for subsequent removal.
In this embodiment, a maskless etching process is used to remove the top end of the core layer 102 and the sidewall material layer 103a on the layer 101 to be etched, so as to form the sidewall 103. A Mask (Mask) is not needed by adopting a maskless etching process, so that the process cost is reduced. Of course, in other embodiments, other processes may be used to form the sidewall.
Specifically, a maskless dry etching process is adopted for etching, and the dry etching process has the characteristic of anisotropic etching, so that the damage to other film structures is small while the top of the core layer and the side wall material layer on the layer to be etched are completely removed, and the side wall thickness formed by lateral etching of the side wall material layer is prevented from being thinned, and the side wall can play a role of etching a mask in the subsequent step of forming a target pattern.
The top surface of the obtained side wall 103 is a cambered surface (as shown in fig. 5) under the influence of the side wall generating process, so as to avoid the reduction of the accuracy of the subsequent pattern transfer.
Referring to fig. 6-8, after forming the side wall 103, a complementary structure is formed on the top surface of the side wall 103 to completely cover the cambered surface, where the top surface of the complementary structure is a flat plane.
And forming a complementary structure with a flat top surface on the arc-shaped top surface of the side wall so as to completely cover the arc surface, and then etching the layer to be etched by taking the complementary structure and the side wall together as an etching mask to form a target pattern structure. The top surface is a flat plane instead of an arc surface when the complementary structure and the side wall are used as an etching mask together, so that the situation that the patterns formed on the layer to be etched are different in depth due to the fact that the top surface of the side wall is the arc surface when the side wall is used as the etching mask is avoided, patterns with the same structure line depth are formed on the layer to be etched, and the accuracy and the stability of pattern transfer are improved; the method for forming the semiconductor structure is suitable for any process requiring pattern transfer, is simple in process and improves practicality.
The formation process of the supplemental structure is not limited as long as the supplemental structure having a flat top surface can be formed. In one embodiment, the supplemental structure with a planar top surface may be formed by ion treatment, which may include ion implantation, ion beam mixing, ion sputtering, and the like.
In this embodiment, in order to facilitate forming the supplemental structure 104, the forming process of the supplemental structure 104 is an ion implantation process.
In order to ensure that the complementary structure 104 with the plane top surface is formed on the side wall 103 with the arc surface top surface, the included angle between the ion implantation direction and the normal line of the surface of the layer to be etched cannot be too large or too small, and the included angle cannot be ensured to be too large or too small to ensure that the complementary structure completely covers the arc surface of the side wall. Therefore, in this embodiment, the angle between the direction of ion implantation and the normal line of the surface of the layer 101 to be etched is 30 ° to 60 °, for example, the angle between the direction of ion implantation and the normal line of the surface of the layer to be etched may be 35 °,30 °,45 °,50 ° or 55 °.
In this embodiment, the material of the sidewall 103 is silicon oxide. The ion implanted ions may be one or a combination of at least two of germanium ions, silicon ions, boron ions, carbon ions, and phosphorous ions. When the ion beam strikes the surface of the side wall, a series of physical and chemical interactions are generated between the ion beam and the surface of the side wall to form a new surface layer (namely a complementary structure), and the ion implantation process ensures that the problem of peeling between the complementary structure and the side wall is avoided.
As shown in fig. 5, the cambered surface of the side wall on the first side of the core layer and the cambered surface of the side wall on the second side of the core layer are symmetrical with respect to the normal line (dotted line in fig. 5) of the core layer. Specifically, a step of forming a complementary structure 104 on the top surface of the side wall 103, where the top surface of the complementary structure 104 is a flat plane:
as shown in fig. 6, first, a first complementary structure 1041 is formed on a top surface of a side wall located on a first side of the core layer 102, where the top surface of the first complementary structure 1041 is a flat plane;
when the ion beam strikes the surface of the sidewall 103 on the first side of the core layer, a series of physical and chemical interactions between the ion beam and the surface of the sidewall 103 occur, forming a new first supplemental structure 1041 that covers at least the top surface of the sidewall on the first side of the core layer.
Next, as shown in fig. 7, a second supplemental structure 1042 is formed on the top surface of the sidewall on the second side of the core layer 102, and the top surface of the second supplemental structure 1042 is a flat plane.
When the ion beam strikes the surface of the sidewall 103 on the second side of the core layer, a series of physical and chemical interactions between the ion beam and the surface of the sidewall form a new second supplemental structure 1042 that covers at least the top surface of the sidewall on the second side of the core layer.
As shown in fig. 8, the first supplemental structure 1041 and the second supplemental structure 1042 together constitute a supplemental structure 104.
As shown in fig. 9, since the formation of the supplemental structure 104 may cause the width of the sidewall and the supplemental structure to increase when the supplemental structure is used as a subsequent etching mask, the spacing between the adjacent target pattern structures (e.g., gate structures) to be formed becomes smaller, and thus the leakage of the semiconductor structure is easily caused, in one embodiment, the method further includes, after forming the supplemental structure on the top surface of the sidewall 103:
and etching the side wall 103 and the complementary structure 104 so that the side wall 103 and the complementary structure 104 have a predetermined width.
It should be noted that, the predetermined width refers to a predetermined width of the etching mask, that is, an overall width of the side wall and the first complementary structure on the first side of the core layer or an overall width of the side wall and the second complementary structure on the second side of the core layer when the layer to be etched is etched by taking the side wall and the complementary structure as the mask.
In this embodiment, a dry etching process is used to etch the sidewall 103 and the complementary structure 104. In order to avoid the influence on other structural layers during the process of etching the side wall and the complementary structure, the etching gas can select oxygen (O 2 ) And sulfur dioxide (SO) 2 ) At least one of them. Because of O 2 And SO 2 The silicon-containing structural layer is not affected, so that the stability of other structural layers can be ensured.
Of course, in other embodiments, the width of the pre-formed side wall may be set to be narrower than the width of the subsequent etching mask, so that after the subsequent formation of the complementary structure, the overall width of the first complementary structure and the side wall or the overall width of the second complementary structure and the side wall meets the accuracy requirement of the etching mask width.
With continued reference to fig. 10, after forming the supplemental structure, the method for forming a semiconductor structure according to the embodiment of the present invention further includes:
the core layer 102 (shown in fig. 9) is removed.
In this embodiment, a dry etching process is used to remove the core layer. And in the process of removing the core layer by a dry etching process, taking the layer to be etched as an etching stop layer. The dry etching process can improve process compatibility without replacing a machine, and is beneficial to improving working efficiency. In other embodiments, an ashing process may also be used to remove the core layer.
The material of the core layer and the material of the side wall formed later have etching selection ratio, and the probability of damage to the side wall is lower in the process of removing the core layer later.
In a specific embodiment, the material of the core layer may be amorphous carbon. The amorphous carbon is an organic material, has higher process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the core layer, has simple amorphous carbon removal process, is not easy to have residues, and is prepared for the subsequent removal of the core layer. In other embodiments, the material of the core layer may also be silicon oxide or polysilicon.
With continued reference to fig. 11, after the core layer is removed, the method for forming a semiconductor structure provided in the embodiment of the present invention further includes:
and etching the layer to be etched by taking the side wall and the supplementary structure as masks to form a target pattern structure 106.
Specifically, the complementary structure and the side wall are used as an etching mask together, so that the method can be used for any manufacturing process in the process of forming the semiconductor structure. Thus, in one embodiment, the layer to be etched may comprise a structural layer of gate material.
The gate material structure layer provides for subsequent formation of a gate structure across the fin.
The gate material structure layer may be a stacked structure, and the gate material structure layer includes a gate oxide material layer (not shown) conformally covering the fin portion and a gate material layer (not shown) on the gate oxide material layer. In other embodiments, the gate material structure layer may also be a single layer structure, i.e., the gate material structure layer includes only the gate material layer.
In this embodiment, the material of the gate oxide material layer may be silicon oxide. In other embodiments, the material of the gate oxide material layer may also be silicon oxynitride. In this embodiment, the material of the gate material layer is polysilicon. In other embodiments, the material of the gate material layer may also be amorphous carbon.
Specifically, the step of forming the gate material structure layer includes: forming a gate oxide material layer conformally covering the surface of the fin part; after forming the gate oxide material layer, forming a gate material layer on the gate oxide material layer.
The step of forming the target pattern structure 106 by etching the layer to be etched using the side wall and the complementary structure as masks includes:
and etching the gate material structure layer by taking the side wall and the supplementary structure as masks to form a gate structure, and taking the gate structure as the target pattern structure 106.
In another embodiment, the layer to be etched may include a silicon substrate layer;
and etching the layer to be etched by taking the side wall and the supplementary structure as masks, wherein the step of forming the target pattern structure comprises the following steps of:
and etching the substrate by taking the side wall and the supplementary structure as masks to form discrete fins, wherein the discrete fins serve as the target pattern structure.
In other embodiments, the step of etching the layer to be etched with the side wall and the complementary structure as masks, and the step of forming the target pattern structure may further include:
forming a dielectric layer on the substrate, wherein the dielectric layer covers the gate material structure layer;
the step of etching the layer to be etched comprises the following steps: and etching the dielectric layer and the gate material structure layer by taking the side wall and the supplementary structure as masks to form a gate structure, wherein the gate structure is used as the target pattern structure.
It should be noted that, in the process of etching the gate material structure layer to form the gate structure, after the side wall and the complementary structure are completely consumed, the dielectric layer is used as a mask to continue etching the gate material structure.
The dielectric layer is made of at least one of silicon nitride, silicon oxide or silicon oxynitride.
It should be noted that the layer to be etched is not limited to forming the gate structure and the fin, but may be any layer structure in a process requiring pattern transfer.
In order to solve the above problems, the embodiment of the invention further provides a semiconductor structure.
Referring to fig. 10, a semiconductor structure provided in an embodiment of the present invention includes:
the structure of the layer to be etched comprises a layer to be etched 101 and a side wall 103 positioned on the layer to be etched 101, wherein the top surface of the side wall 103 is a cambered surface;
and the supplementary structure 104 is positioned on the top surface of the side wall 103 and completely covers the top surface, and the top surface of the supplementary structure 104 is a flat plane.
The layer 101 to be etched is an etching object of a subsequent etching process, and is used for forming a target pattern structure.
The material of the sidewall 103 may include one or at least two of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride.
The material of the supplemental structure 104 may include at least one of germanium oxide, silicon oxide, boron oxide, or phosphorous oxide.
In a specific embodiment, the layer to be etched 101 may include a gate material structure layer, and a gate structure may be formed later, where the gate structure is used as the target pattern structure.
In other embodiments, the layer to be etched may also be a dielectric layer formed on the substrate, where the dielectric layer covers the gate material structural layer;
in another embodiment, the layer to be etched may comprise a silicon substrate layer;
and etching the substrate by taking the side wall and the supplementary structure as masks to form discrete fins, wherein the discrete fins serve as the target pattern structure.
In this embodiment, the layer structure to be etched is formed on a base, which may include a silicon substrate 100. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
It should be noted that the layer to be etched is not limited to forming the gate structure and the fin, but may be any layer structure in a process requiring pattern transfer.
According to the semiconductor structure provided by the embodiment of the invention, the complementary structure with the flat top surface is formed on the arc-shaped top surface of the side wall, and the complementary structure completely covers the cambered surface, so that the complementary structure and the side wall are jointly used as an etching mask to etch the layer to be etched, when the target pattern structure is formed, the top surface is flat and is not the cambered surface when the complementary structure and the side wall are jointly used as the etching mask, the situation that the patterns formed on the layer to be etched are different in depth due to the fact that the top surface of the side wall is the cambered surface when the side wall is used as the etching mask can be avoided, the patterns with the same structural line depth are formed on the layer to be etched, and the accuracy and stability of pattern transfer are improved; the semiconductor structure provided by the embodiment of the invention is suitable for any process needing pattern transfer, has simple process and improves the practicability.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a layer structure to be etched, wherein the layer structure to be etched comprises a layer to be etched, a core layer positioned on the layer to be etched and side walls positioned on two sides of the core layer, and the top surface of the side wall is a cambered surface;
and forming a supplementary structure on the top surface of the side wall so as to completely cover the cambered surface, wherein the top surface of the supplementary structure is a flat plane.
2. The method of claim 1, wherein the complementary structure is formed by ion implantation in a direction at an angle of 30 ° -60 ° to the normal of the surface of the layer to be etched.
3. The method of forming a semiconductor structure of claim 2, wherein the ion implanted ions comprise one or a combination of at least two of germanium ions, silicon ions, boron ions, carbon ions, and phosphorous ions.
4. The method of forming a semiconductor structure according to claim 1, wherein the cambered surface of the sidewall on the first side of the core layer and the cambered surface of the sidewall on the second side of the core layer are symmetrical with respect to the core layer, the step of forming a complementary structure on the top surface of the sidewall, the top surface of the complementary structure being a flat plane, comprises:
forming a first supplement structure on the top surface of the side wall positioned on the first side of the core layer, wherein the top surface of the first supplement structure is a flat plane;
and forming a second supplementary structure on the top surface of the side wall positioned on the second side of the core layer, wherein the top surface of the second supplementary structure is a flat plane.
5. The method of forming a semiconductor structure of claim 1, wherein the step of forming a supplemental structure on a top surface of the sidewall, the supplemental structure having a top surface that is planar, further comprises:
and etching the side wall and the supplementary structure so that the side wall and the supplementary structure have preset widths.
6. The method of claim 5, wherein an etching gas for etching the sidewall and the supplemental structure comprises at least one of oxygen and sulfur dioxide.
7. The method for forming a semiconductor structure according to claim 1, wherein after forming a complementary structure on a top surface of the sidewall, the complementary structure has a flat top surface, further comprising:
and removing the core layer.
8. The method of forming a semiconductor structure of claim 7, wherein said removing said core layer further comprises:
and etching the layer to be etched by taking the side wall and the supplementary structure as masks to form a target pattern structure.
9. The method of forming a semiconductor structure of claim 8, wherein the layer to be etched comprises a gate material structure layer, and the step of etching the layer to be etched with the sidewall and the supplemental structure as masks, the step of forming a target pattern structure comprises:
and etching the grid material structure layer by taking the side wall and the complementary structure on the side wall as masks to form a grid structure, and taking the grid structure as the target pattern structure.
10. The method of forming a semiconductor structure of claim 9, wherein the step of etching the layer to be etched using the sidewall and the supplemental structure on the sidewall as a mask, the step of forming a target pattern structure further comprises:
forming a dielectric layer, wherein the dielectric layer covers the grid material structure layer;
the step of etching the layer to be etched comprises the following steps: and etching the dielectric layer and the grid material structure layer by taking the side wall and the complementary structure on the side wall as masks to form a grid structure, wherein the grid structure is used as the target pattern structure.
11. The method of forming a semiconductor structure of claim 10, wherein the material of the dielectric layer comprises at least one of silicon nitride, silicon oxide, or silicon oxynitride.
12. The method of forming a semiconductor structure of claim 8, wherein the layer to be etched comprises a silicon substrate layer;
and etching the layer to be etched by taking the side wall and the complementary structure on the side wall as masks, wherein the step of forming the target pattern structure comprises the following steps of:
and etching the silicon substrate layer by taking the side wall and the complementary structure on the side wall as masks to form discrete fins, wherein the discrete fins serve as the target pattern structure.
13. The method of forming a semiconductor structure according to any one of claims 1 to 12, wherein the step of forming the layer structure to be etched comprises:
providing a layer to be etched;
forming a core layer on the layer to be etched;
covering a side wall material layer on the core layer and the layer to be etched exposed from the core layer in a conformal manner;
and removing the top of the core layer and the side wall material layer on the layer to be etched, which is exposed by the core layer, and taking the rest side wall material layer on the side wall of the core layer as a side wall.
14. The method of forming a semiconductor structure as claimed in any one of claims 1-12, wherein the sidewall material comprises one or at least two of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
15. The method of forming a semiconductor structure of any of claims 1-12, wherein the material of the core layer comprises single crystal silicon, polysilicon, or amorphous carbon.
16. A semiconductor structure, comprising:
the structure of the layer to be etched comprises a layer to be etched and a side wall positioned on the layer to be etched, wherein the top surface of the side wall is a cambered surface;
the supplementing structure is positioned on the top surface of the side wall and completely covers the top surface, and the top surface of the supplementing structure is a flat plane.
17. The semiconductor structure of claim 16, wherein a material of the sidewall comprises one or at least two of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
18. The semiconductor structure of claim 16, wherein the material of the supplemental structure is at least one of germanium oxide, silicon oxide, boron oxide, or phosphorous oxide.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101593687A (en) * 2008-05-30 2009-12-02 中芯国际集成电路制造(北京)有限公司 Polysilicon gate, side wall, semiconductor device and forming method thereof
TW201128736A (en) * 2010-02-08 2011-08-16 Taiwan Semiconductor Mfg Method for manufacturing an SRAM and method for manufacturing a semiconductor device
WO2012071940A1 (en) * 2010-12-03 2012-06-07 北京大学 Method for fabricating fine line
CN103794476A (en) * 2012-10-30 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned triple pattern
CN106558497A (en) * 2015-09-29 2017-04-05 中国科学院微电子研究所 Semiconductor device manufacturing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101435520B1 (en) * 2008-08-11 2014-09-01 삼성전자주식회사 Semiconductor device and method of forming patterns for semiconductor device
CN104465386A (en) * 2013-09-24 2015-03-25 中芯国际集成电路制造(北京)有限公司 Method for forming semiconductor structure
US9614053B2 (en) * 2013-12-05 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Spacers with rectangular profile and methods of forming the same
US9515089B1 (en) * 2015-05-14 2016-12-06 International Business Machines Corporation Bulk fin formation with vertical fin sidewall profile

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101593687A (en) * 2008-05-30 2009-12-02 中芯国际集成电路制造(北京)有限公司 Polysilicon gate, side wall, semiconductor device and forming method thereof
TW201128736A (en) * 2010-02-08 2011-08-16 Taiwan Semiconductor Mfg Method for manufacturing an SRAM and method for manufacturing a semiconductor device
WO2012071940A1 (en) * 2010-12-03 2012-06-07 北京大学 Method for fabricating fine line
CN103794476A (en) * 2012-10-30 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned triple pattern
CN106558497A (en) * 2015-09-29 2017-04-05 中国科学院微电子研究所 Semiconductor device manufacturing method

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