CN113113303B - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

Info

Publication number
CN113113303B
CN113113303B CN202110363878.1A CN202110363878A CN113113303B CN 113113303 B CN113113303 B CN 113113303B CN 202110363878 A CN202110363878 A CN 202110363878A CN 113113303 B CN113113303 B CN 113113303B
Authority
CN
China
Prior art keywords
layer
dielectric layer
mask
insulating layer
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110363878.1A
Other languages
Chinese (zh)
Other versions
CN113113303A (en
Inventor
辛欣
王景皓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202110363878.1A priority Critical patent/CN113113303B/en
Publication of CN113113303A publication Critical patent/CN113113303A/en
Application granted granted Critical
Publication of CN113113303B publication Critical patent/CN113113303B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps: removing the first upper dielectric layer and part of the insulating layer positioned in the array area by adopting a first dry etching process so as to enable the top surface of the rest insulating layer positioned in the array area to be flush with the top surface of the first lower dielectric layer; removing the first lower dielectric layer to form a patterned insulating layer located in the array region; etching the first mask layer in the array area by adopting a second dry etching process to form a patterned first mask layer; the second dry etching process simultaneously etches part of the insulating layer and the second upper dielectric layer in the core area, and the insulating layer and the third upper dielectric layer in the peripheral area; the top surface of the residual insulating layer positioned in the core area is flush with the top surface of the second lower dielectric layer; and etching the conductive layer and the active region in the array region to form a contact hole. The embodiment of the invention can simplify the manufacturing process of the semiconductor structure.

Description

Method for manufacturing semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
In the manufacturing process of the semiconductor structure, in order to transfer the design pattern to the substrate of the semiconductor structure, firstly, the patterning of the photoresist is realized through photoetching, then, the pattern on the photoresist is transferred to the mask layer, and finally, the substrate is etched through the patterned mask layer so as to realize the pattern transfer.
With the continuous miniaturization of semiconductor manufacturing processes, especially after the semiconductor manufacturing processes enter the era of 7nm and 5nm, the integration level of semiconductor structures is continuously improved, and the manufacturing processes of semiconductor structures and the performance of semiconductor structures are required to be further improved under the aim of pursuing higher pattern density.
Disclosure of Invention
Embodiments of the present invention provide a method for manufacturing a semiconductor structure, so as to improve a manufacturing process of the semiconductor structure and performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate comprises an array area, a core area and a peripheral area, and the array area comprises an active area and an isolation area; forming a conducting layer, a first mask layer and a dielectric layer which are arranged in a stacked mode on the substrate, wherein the dielectric layer comprises a first dielectric layer located on the array area, a second dielectric layer located on the core area and a third dielectric layer located on the peripheral area; a first groove is formed between the adjacent first dielectric layers, and a second groove is formed between the adjacent second dielectric layers; the first dielectric layer comprises a first lower dielectric layer and a first upper dielectric layer which are arranged in a stacked mode, the second dielectric layer comprises a second lower dielectric layer and a second upper dielectric layer which are arranged in a stacked mode, and the third dielectric layer comprises a third lower dielectric layer and a third upper dielectric layer which are arranged in a stacked mode; forming an insulating layer, wherein the insulating layer covers the surface of the dielectric layer and fills the first groove and the second groove; removing the first upper dielectric layer and part of the insulating layer positioned in the array area by adopting a first dry etching process so as to enable the top surface of the rest insulating layer positioned in the array area to be flush with the top surface of the first lower dielectric layer; removing the first lower dielectric layer to form the patterned insulating layer positioned in the array area; etching the first mask layer in the array area by using the patterned insulating layer as a mask and adopting a second dry etching process to form the patterned first mask layer; the second dry etching process simultaneously etches part of the insulating layer and the second upper dielectric layer in the core region and the insulating layer and the third upper dielectric layer in the peripheral region; the top surfaces of the rest of the insulating layers in the core area are flush with the top surface of the second lower dielectric layer; and etching part of the conductive layer and part of the active area in the array area by taking the patterned first mask layer as a mask so as to form a contact hole.
In addition, after the step of forming the insulating layer and before the step of removing the insulating layer and the first upper dielectric layer located in the array region, the method further includes: and forming a photoresist layer on the insulating layer in the core region and the peripheral region.
In addition, the step of removing the first lower dielectric layer includes: and removing the first lower dielectric layer and the photoresist layer in the array region in the same step by adopting a third dry etching process.
In addition, the etching selection ratio of the third dry etching process to the photoresist layer and the first lower dielectric layer is 0.8-1.2.
In addition, the thickness of the insulating layer higher than the dielectric layer is 35-45 nm.
In addition, the etching selection ratio of the first dry etching process to the first upper dielectric layer and the insulating layer is 0.8-1.2.
In addition, the etching selection ratio of the second dry etching process to the second upper dielectric layer and the insulating layer is 0.8-1.2.
In addition, after the conductive layer is formed, the method further includes: and forming a third mask layer and a second mask layer which are stacked on the conductive layer, wherein the first mask layer is also positioned on the second mask layer.
In addition, the step of etching a part of the conductive layer and a part of the active region in the array region by using the patterned first mask layer as a mask to form a contact hole includes: etching a part of the second mask layer in the array area by taking the patterned first mask layer as a mask to form the patterned second mask layer, and simultaneously removing the second lower dielectric layer and a part of the first mask layer in the core area and removing the third lower dielectric layer and the first mask layer in the peripheral area; etching a part of the third mask layer in the array area by using the patterned second mask layer as a mask through a fourth etching process to form the patterned third mask layer, and simultaneously removing the insulating layer and the first mask layer in the core area; and etching part of the conducting layer and part of the active area in the array area by taking the patterned third mask layer as a mask so as to form the contact hole.
In addition, the etching selection ratio of the fourth dry etching process to the insulating layer and the second mask layer is greater than 10; and the etching selection ratio of the fourth dry etching process to the first mask layer and the second mask layer is greater than 10.
In addition, the thickness of the second mask layer is larger than that of the second lower dielectric layer.
In addition, the material of the first mask layer comprises silicon oxynitride, and the material of the second mask layer comprises a carbon material or a carbon-containing compound.
In addition, the material of the third mask layer is the same as that of the insulating layer.
In addition, the material of the third mask layer and the material of the insulating layer include silicon oxide.
In addition, the forming method of the insulating layer comprises an atomic layer deposition process.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
the embodiment of the invention adopts the first dry etching process to enable the top surface of the residual insulating layer positioned in the array area to be flush with the top surface of the first lower dielectric layer, namely the etching degree of the first dry etching on the insulating layer and the first upper dielectric layer is equivalent, so that the etching of the first lower dielectric layer is not influenced, and the precision of pattern transfer can be improved. In addition, the first mask layer in the array area is etched by adopting a second dry etching process, wherein the second dry etching process simultaneously etches a part of the insulating layer and the second upper dielectric layer in the core area and etches the insulating layer and the third upper dielectric layer in the peripheral area. The second dry etching can also keep the etching progress of the array region, the core region and the peripheral region consistent, and a certain region does not need to be processed independently, so that the process steps are simplified. In addition, the top surface of the residual insulating layer in the core area is flush with the top surface of the second lower dielectric layer. The second dry etching has the same etching degree on the insulating layer and the second upper dielectric layer, so that the etching of the second lower dielectric layer is not influenced, and the pattern of the core area is prevented from being influenced.
In addition, the thickness of the second mask layer is larger than that of the second lower dielectric layer. The etching of the second mask layer and the etching of the second lower dielectric layer are carried out in the same process step, and the second dielectric layer is also positioned on the first mask layer. Therefore, the first mask layer penetrating the core area and the peripheral area is etched while the second mask layer is etched, so that the step of independently processing the first mask layer can be omitted, and the production process is simplified.
In addition, the material of the third mask layer is the same as that of the insulating layer. Therefore, the two etching methods have the same etching rate in the same etching process and keep more consistent etching degree, so that the condition that one etching method is independently processed can be avoided, and the process steps can be simplified.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1-9 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to an embodiment of the invention.
Detailed Description
As is known in the art, the manufacturing process of the semiconductor structure and the performance of the semiconductor structure need to be further improved. The analysis shows that the main reasons are as follows: in order to transfer a lithographic pattern onto a substrate of a semiconductor structure, it is often necessary to form multiple different mask layers on the substrate; the substrate usually comprises a plurality of different areas, the different areas need to form different patterns, and the mask layer covers the different areas of the substrate at the same time; due to the fact that patterns to be formed in different regions are different, in the process of etching the mask layer, the etching degrees of different mask layers in the regions are different, and therefore the problems that the patterns in some regions are invalid, collapse or the accuracy is reduced can occur. In addition, the etching process of the mask layer in a plurality of areas is still complicated at present.
To solve the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: and removing part of the insulating layer and the first upper dielectric layer in the array area by adopting a first dry etching process so as to enable the top surface of the rest insulating layer in the array area to be flush with the top surface of the first lower dielectric layer, namely the etching degree of the insulating layer and the first upper dielectric layer by the first dry etching is equivalent, and further the etching of the first lower dielectric layer is not influenced, so that the precision of pattern transfer can be improved. In addition, a second dry etching process is adopted to etch the first mask layer positioned in the array area, wherein the second dry etching process simultaneously etches a part of the insulating layer and the second upper dielectric layer positioned in the core area, and etches the insulating layer and the third upper dielectric layer positioned in the peripheral area; the top surface of the residual insulating layer in the core area is flush with the top surface of the second lower dielectric layer. The second dry etching has the same etching degree on the insulating layer and the second upper dielectric layer, so that the etching of the second lower dielectric layer is not influenced, meanwhile, the etching progress of the array area, the core area and the peripheral area can be kept consistent through the second dry etching, and a certain area does not need to be processed independently, so that the process steps are simplified, and the production cost is reduced.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
Fig. 1 to 9 are schematic structural diagrams corresponding to steps in the method for manufacturing a semiconductor structure provided in this embodiment.
Referring to fig. 1, a substrate 10 is provided, the substrate 10 including an array region a, a core region b, and a peripheral region c, the array region a including an active region 101 and an isolation region 102.
Specifically, the array region a is adapted to form transistors, word lines, and bit lines, and the core region b and the peripheral region c are adapted to form circuits. The core region b is suitable for forming a core circuit, and the peripheral region c is suitable for forming a peripheral circuit.
In this embodiment, the material of the substrate 10 may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. The isolation region 102 is used to isolate the adjacent active regions 101, and the material of the isolation region 102 may be an insulating material such as silicon oxide, silicon nitride, or silicon carbide. The material of the active region 101 is a semiconductor material, and may be, for example, an elemental semiconductor, an inorganic compound semiconductor, or an oxide semiconductor, and the semiconductor material has dopant ions therein, such as boron or phosphorus.
In this embodiment, the substrate 10 in the array region a and the core region b further has a capping layer 103, and the material of the capping layer 103 is an insulating material, such as silicon nitride.
With continued reference to fig. 1, a conductive layer 104, a first mask layer 141, and a dielectric layer are formed on a substrate 10 in a stacked arrangement.
The conductive layer 104 may be used to form bit lines in the array region a or gate structures in the core region b and the peripheral region c. Specifically, the material of the conductive layer 104 may be polysilicon. The resistance of the conductive layer 104 can be flexibly adjusted by doping ions. In other embodiments, the material of the conductive layer may also be a low resistance metal. In this embodiment, the conductive layer 104 is formed by a chemical vapor deposition method.
The first mask layer 141 is a hard mask. In this embodiment, the first mask layer 141 is made of silicon oxynitride, and in other embodiments, the first mask layer may be made of silicon nitride. In this embodiment, the first mask layer 141 is formed by a chemical vapor deposition method.
The dielectric layers comprise a first dielectric layer 11 positioned on the array area a, a second dielectric layer 12 positioned on the core area b and a third dielectric layer 13 positioned on the peripheral area c; the first dielectric layer 11 includes a first lower dielectric layer 111 and a first upper dielectric layer 112 which are stacked, the second dielectric layer 12 includes a second lower dielectric layer 121 and a second upper dielectric layer 122 which are stacked, and the third dielectric layer 12 includes a third lower dielectric layer 131 and a third upper dielectric layer 132 which are stacked.
Further, the step of forming the dielectric layer includes: forming an initial dielectric layer on the first mask layer 141, where the initial dielectric layer includes an initial lower dielectric layer and an initial upper dielectric layer, a forming process of the initial lower dielectric layer may be a spin coating process, and a forming process of the initial upper dielectric layer may be a chemical vapor deposition process; and etching parts of the initial dielectric layers positioned in the array area a and the core area b to form mutually separated first dielectric layers 11 positioned on the array area a and mutually separated second dielectric layers 12 positioned on the core area b, wherein a first groove 161 is formed between the adjacent first dielectric layers 11, and a second groove 162 is formed between the adjacent second dielectric layers 12.
In this embodiment, the material of the initial upper dielectric layer is the same as the material of the first mask layer 141, that is, the materials of the second upper dielectric layer 122 and the third upper dielectric layer 132 are the same as the material of the first mask layer 141. The main reason is that the first mask layer 141, the second upper dielectric layer 122 and the third upper dielectric layer 132 are etched in the same process step in the following steps, and when the materials are the same, the etching rates of the first mask layer 141, the second upper dielectric layer 122 and the third upper dielectric layer 132 are the same in the same process, so that the etching degrees of the first mask layer, the second upper dielectric layer and the third upper dielectric layer can be kept consistent; namely, after the etching process is finished, the three parts can be etched through; this can avoid a separate etching process for one of the non-etched through layers, thereby simplifying the manufacturing process.
In this embodiment, the material of the initial lower dielectric layer is a carbon material. That is, the materials of the first lower dielectric layer 111, the second lower dielectric layer 121 and the third lower dielectric layer 131 are carbon materials. In other embodiments, the material of the first, second and third lower dielectric layers may also be a carbon-containing compound.
In this embodiment, after forming the conductive layer, the method further includes: a third mask layer 143 and a second mask layer 142 are formed over the conductive layer 104 in a stacked manner, and the first mask layer 141 is also located on the second mask layer 142. The multiple mask layers can improve the precision of pattern transfer.
The third mask layer 143 and the second mask layer 142 will be specifically described below.
The third mask layer 143 is a hard mask, and in this embodiment, the material of the third mask layer 143 is silicon oxide. In other embodiments, the material of the third mask layer may be silicon nitride or silicon oxynitride. In this embodiment, the third mask layer 143 is formed by chemical vapor deposition.
In this embodiment, the material of the second mask layer 142 is the same as the material of the second lower dielectric layer 121 and the third lower dielectric layer 131. The main reason is that the second mask layer 142, the second lower dielectric layer 121 and the third lower dielectric layer 131 are etched in the same process step; when the materials are the same, the etching rates of the three are the same in the same process, so that the etching degrees of the three are kept consistent, and the independent treatment of one of the three can be avoided, thereby simplifying the production steps. Specifically, the material of the second mask layer 142 is a carbon material. In other embodiments, the material of the second mask layer may also be different from the material of the second lower dielectric layer and the third lower dielectric layer.
In this embodiment, the second mask layer 142 is formed by a spin-on process, and in other embodiments, the second mask layer may be formed by a chemical vapor deposition process.
Referring to fig. 2, an insulating layer 120 is formed, and the insulating layer 120 covers the surface of the dielectric layer 12 and fills the first trench 161 (refer to fig. 1) and the second trench 162 (refer to fig. 1).
In this embodiment, the material of the insulating layer 120 is the same as that of the third mask layer 143. The main reason is that when the two materials are the same, the two materials can have the same etching rate by using the same process; the two are etched in the same step subsequently, so that the two have more consistent etching degree; namely, after the etching process is finished, both can be etched through; this can avoid a separate etching process for one of the non-etched through layers, thereby simplifying the manufacturing process. Specifically, the material of the insulating layer 120 may be silicon oxide.
It is understood that in other embodiments, the material of the insulating layer may be different from the material of the third mask layer.
The thickness of the insulating layer 120 above the dielectric layer is 35-45 nm, such as 36nm, 40nm or 42nm, in a direction perpendicular to the top surface of the substrate 10. And forming photoresist layers in the core region b and the peripheral region c, etching the insulating layer 120 and the photoresist layers together after forming the photoresist layers, wherein when the thickness of the insulating layer 120 is in the above range, the etching process time is short, and the excessively thick photoresist layers are not consumed, so that the patterns of the core region b and the peripheral region c are not influenced.
The method of forming the insulating layer 120 includes an atomic layer deposition process. The uniformity of the insulating layer 120 can be improved by utilizing the atomic layer deposition process, the thickness of the insulating layer 12 at each position can be ensured to be the same, and the accuracy of pattern transfer can be improved.
Referring to fig. 3, a photoresist layer 140 is formed, and the photoresist layer 140 is positioned on the insulating layer 120 in the core region b and the peripheral region c.
Since the photoresist layer 140 covers the core region b and the peripheral region c, the pattern of the core region b and the peripheral region c is not affected when the patterned insulating layer 120 is subsequently formed in the array region a. In this embodiment, before forming the photoresist layer 140, the insulating layer 120 is not etched back to remove the insulating layer 120 higher than the first upper dielectric layer 112, but the photoresist layer 140 is directly formed on the insulating layer 120. The insulating layer 120 above the first upper dielectric layer 112 is etched simultaneously with the etching of the photoresist layer 140 and the first mask layer 141. Therefore, the present embodiment can omit the back etching step, thereby simplifying the manufacturing process.
Referring to fig. 4, the first upper dielectric layer 112 (refer to fig. 3) and a portion of the insulating layer 120 located in the array region a are removed using a first dry etching process, so that the top surface of the remaining insulating layer 120 located in the array region a is flush with the top surface of the first lower dielectric layer 111.
Specifically, the first dry etching process first etches the insulating layer 120, so that the insulating layer 120 exposes the top surface of the first upper dielectric layer 112 (refer to fig. 3), and the top surface of the insulating layer 120 is flush with the top surface of the first upper dielectric layer 112; further, the first dry etching process simultaneously etches the first upper dielectric layer 112 and the insulating layer 120, and the etching speed of the first upper dielectric layer 112 and the etching speed of the insulating layer 120 are kept consistent. It can be understood that, if there is a large difference between the etching rate of the first upper dielectric layer 112 and the etching rate of the insulating layer 120, for example, a portion of the first upper dielectric layer 112 remains on the first lower dielectric layer 111, and the top of the insulating layer 120 has a recess and exposes the top sidewall of the first lower dielectric layer 111, then during the process of removing the photoresist layer 140, the etching gas may remove the exposed first lower dielectric layer 111, thereby causing the pattern of the first lower dielectric layer 111 to fail, and the remaining first upper dielectric layer 112 collapses in the spatial position occupied by the original first lower dielectric layer 111, thereby affecting the subsequent etching and causing the decrease of the pattern precision.
In this embodiment, the etching speed of the first upper dielectric layer 112 and the insulating layer 120 is controlled by the first dry etching process, so that the first upper dielectric layer 112 can be completely removed, and the top surface of the remaining insulating layer 120 is flush with the top surface of the first lower dielectric layer 111, and thus, the subsequent etching of the first lower dielectric layer 111 is not affected, and the pattern precision can be improved.
Furthermore, the etching selection ratio of the first dry etching process to the first upper dielectric layer 112 and the insulating layer 120 is 0.8-1.2. Preferably, the etching selectivity ratio of the first upper dielectric layer 112 to the insulating layer 120 is 1, so that the etching degrees of the two are close to each other, and the top surface of the remaining insulating layer 120 can be flush with the top surface of the first lower dielectric layer 111.
In this embodiment, the first dry etching process also removes a portion of the photoresist layer 140, so as to shorten the subsequent etching time for the photoresist layer 140 and improve the production efficiency.
Specifically, in this embodiment, the etching gas of the first dry etching process includes C4F6(flow rate of 20-30 Sccm), O2(flow rate is 5-15 Sccm) and Ar (flow rate is 300-500 Sccm); and the etching temperature is 20-50 ℃, for example, 27 ℃, 39 ℃ or 45 ℃; the pressure of the chamber is 3-9 mtorr, such as 4mtorr, 7mtorr or 8 mtorr; the RF power is 600W-1000W, such as 700W, 800W or 900W.
Referring to fig. 5, the first lower dielectric layer 111 (refer to fig. 4) is removed to form a patterned insulating layer 120 located at the array region a.
Specifically, in this embodiment, a third dry etching process is adopted, and the first lower dielectric layer 111 and the photoresist layer 140 in the array region a are removed in the same step. The removal of the photoresist 140 and the first lower dielectric layer 111 are integrated in the same process step, so that the production flow can be simplified, and the production efficiency can be improved.
Further, the etching selection ratio of the third dry etching process to the photoresist layer 140 and the first lower dielectric layer 111 is 0.8-1.2. Thus, the two can be removed at the same time without separately processing one of the two, thereby reducing the complexity of the production process.
Specifically, in this embodiment, the etching gas of the third dry etching process includes SF6(flow rate is 10-30 Sccm), CH2F2(flow rate 50-80 Sccm), N2(the flow rate is 30-50 Sccm) and He (the flow rate is 80-120 Sccm); and the etching temperature is 20-60 ℃, for example, 30 ℃, 40 ℃ or 50 ℃; the pressure of the chamber is 3-7 mtorr, such as 4mtorr, 5mtorr or 6 mtorr; the RF power is 400W-600W, such as 450W, 500W or 550W.
Referring to fig. 6, the patterned insulating layer 120 is used as a mask, and the first mask layer 141 in the array region a is etched by using a second dry etching process to form a patterned first mask layer 141; wherein, the second dry etching process simultaneously etches part of the insulating layer 120 and the second upper dielectric layer 122 (refer to fig. 5) in the core region b and the insulating layer 120 and the third upper dielectric layer 132 (refer to fig. 5) in the peripheral region c; the top surface of the remaining insulating layer 120 in the core region b is flush with the top surface of the second lower dielectric layer 121.
The top surface of the remaining insulating layer 120 in the core region b is flush with the top surface of the second lower dielectric layer 121, i.e., the etching degree of the second upper dielectric layer 122 and the insulating layer 120 is kept consistent. It can be understood that if there is a large difference between the etching speed of the second upper dielectric layer 122 and the etching speed of the insulating layer 120, for example, a portion of the second upper dielectric layer 122 remains on the second lower dielectric layer 121, and the top of the insulating layer 120 has a recess and exposes the top sidewall of the second lower dielectric layer 121; thus, in the subsequent etching process, the etching gas may remove the exposed second lower dielectric layer 121 first, but not remove the remaining second upper dielectric layer 122; thereby causing failure of the pattern of the second lower dielectric layer 121 and causing the remaining second upper dielectric layer 122 to collapse in the spatial position occupied by the original second lower dielectric layer 121, thereby affecting the subsequent etching and causing a decrease in pattern accuracy.
In this embodiment, the etching speed of the second upper dielectric layer 122 and the etching speed of the insulating layer 120 are controlled by the second dry etching process, so that the second upper dielectric layer 122 can be completely removed, and the top surface of the remaining insulating layer 120 is flush with the top surface of the second lower dielectric layer 121, so that the subsequent etching is not affected, and the pattern precision can be improved.
Furthermore, the etching selection ratio of the second dry etching process to the second upper dielectric layer 122 and the insulating layer 120 is 0.8-1.2. Preferably, the etch selectivity is 1. Therefore, the etching degree of the insulating layer 120 and the etching degree of the second lower dielectric layer 121 can be close to each other, and the top surface of the remaining insulating layer 120 can be flush with the top surface of the second lower dielectric layer 121.
Specifically, in this embodiment, the etching gas of the second dry etching process includes SF6(flow rate is 15-20 Sccm), CH2F2(flow rate of 60-80 Sccm), N2(the flow rate is 35-45 Sccm) and He (the flow rate is 90-110 Sccm); and the etching temperature is 30-50 ℃, for example, 34 ℃, 42 ℃ or 48 ℃; the pressure of the chamber is 4-6 mtorr, for example, 5 mtorr; the RF power is 450W-550W, such as 460W, 470W or 520W.
Referring to fig. 7 to 9, a portion of the conductive layer 104 and a portion of the active region 101 in the array region a are etched using the patterned first mask layer 141 as a mask to form a contact hole 15.
The formation process of the contact hole 105 will be specifically described below.
Referring to fig. 7, using the patterned first mask layer 141 as a mask, a portion of the second mask layer 142 in the array region a is etched to form the patterned second mask layer 142, and simultaneously, the second lower dielectric layer 121 (refer to fig. 6) and a portion of the first mask layer 141 in the core region b are removed and the third lower dielectric layer 131 (refer to fig. 6) and the first mask layer 141 (refer to fig. 6) in the peripheral region c are removed.
In the process, the etching degree of the array area a, the etching degree of the core area b and the etching degree of the peripheral area c are kept relatively consistent, so that a certain area does not need to be independently processed, and the production process is further simplified. The main reasons are as follows: in the direction perpendicular to the top surface of the substrate 10, the thickness of the second mask layer 142 is greater than the thicknesses of the second lower dielectric layer 121 and the third lower dielectric layer 131, and the material of the second mask layer 142 is the same as the material of the second lower dielectric layer 121 and the third lower dielectric layer 131, so that when etching penetrates through the second lower dielectric layer 121 and the third lower dielectric layer 131, the second mask layer 142 with a partial thickness does not penetrate yet; the remaining thickness of the second mask layer 142 may be penetrated together with the first mask layers 141 of the core region b and the peripheral region c; so that a step of separately processing the first mask layer 141 can be omitted to simplify the manufacturing process.
Referring to fig. 8, a portion of the third mask layer 143 in the array region a is etched by using the patterned second mask layer 142 as a mask using a fourth etching process to form the patterned third mask layer 143, and the insulating layer 120 (see fig. 7) and the first mask layer 141 (see fig. 7) in the core region b are removed.
The etching selection ratio of the fourth dry etching process to the insulating layer 120 and the second mask layer 142 is greater than 10; the etching selection ratio of the fourth dry etching process to the first mask layer 141 and the second mask layer 142 is greater than 10. It can be understood that, when the etching selection ratio of the insulating layer 120 and the second mask layer 142 and the etching selection ratio of the first mask layer 141 and the second mask layer 142 are maintained at a larger value, the insulating layer 120 and the first mask layer 141 can be removed more completely, and the second mask layer 142 is not damaged too much, so that the second mask layer 142 can have a flatter top surface without affecting the patterns of the core region b and the peripheral region c.
Specifically, in this embodiment, the etching gas of the fourth dry etching process is C4F6(flow rate of 20-30 Sccm), O2(the flow rate is 8-12 Sccm) and Ar (the flow rate is 350-450 Sccm); the etching temperature is 30-40 ℃, such as 32 ℃, 35 ℃ or 38 ℃; the chamber pressure is 4-8 mtorr, such as 5mtorr, 6mtorr or 7 mtorr; the radio frequency power is 750W-850W, such as 770W, 780W or 820W.
Referring to fig. 9, using the patterned third mask layer 143 as a mask, a portion of the conductive layer 104 and a portion of the active region 101 in the array region a are etched to form a contact hole 15. In this embodiment, the capping layer 103 in the array region a is also etched.
After the contact hole 15 is formed, wet etching or dry etching may be employed to remove the remaining second mask layer 142 (refer to fig. 8).
In summary, in the embodiment, the etching degree of the insulating layer and the first upper dielectric layer by the first dry etching is equivalent, so that the etching of the first lower dielectric layer is not affected. In addition, the second dry etching has the same etching degree on the insulating layer and the second upper dielectric layer, so that the etching of the second lower dielectric layer is not influenced. Meanwhile, the etching progress of the array area, the core area and the peripheral area can be kept consistent, and a certain area does not need to be processed independently, so that the production cost is reduced. Therefore, the embodiment can simplify the production process and improve the precision of the etched pattern.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises an array area, a core area and a peripheral area, and the array area comprises an active area and an isolation area;
forming a conducting layer, a first mask layer and a dielectric layer which are arranged in a stacked mode on the substrate, wherein the dielectric layer comprises a first dielectric layer located on the array area, a second dielectric layer located on the core area and a third dielectric layer located on the peripheral area; a first groove is formed between the adjacent first dielectric layers, and a second groove is formed between the adjacent second dielectric layers; the first dielectric layer comprises a first lower dielectric layer and a first upper dielectric layer which are arranged in a stacked mode, the second dielectric layer comprises a second lower dielectric layer and a second upper dielectric layer which are arranged in a stacked mode, and the third dielectric layer comprises a third lower dielectric layer and a third upper dielectric layer which are arranged in a stacked mode;
forming an insulating layer, wherein the insulating layer covers the surface of the dielectric layer and fills the first groove and the second groove;
removing the first upper dielectric layer and part of the insulating layer positioned in the array area by adopting a first dry etching process so as to enable the top surface of the rest insulating layer positioned in the array area to be flush with the top surface of the first lower dielectric layer;
removing the first lower dielectric layer to form the patterned insulating layer positioned in the array area;
etching the first mask layer in the array area by using the patterned insulating layer as a mask and adopting a second dry etching process to form the patterned first mask layer; the second dry etching process simultaneously etches part of the insulating layer and the second upper dielectric layer in the core region and the insulating layer and the third upper dielectric layer in the peripheral region; the top surfaces of the rest of the insulating layers in the core area are flush with the top surface of the second lower dielectric layer;
and etching part of the conductive layer and part of the active area in the array area by taking the patterned first mask layer as a mask so as to form a contact hole.
2. The method of claim 1, further comprising, after the step of forming the insulating layer and before the step of removing the portion of the insulating layer and the first upper dielectric layer in the array region:
and forming a photoresist layer on the insulating layer in the core region and the peripheral region.
3. The method of claim 2, wherein the removing the first lower dielectric layer comprises:
and removing the first lower dielectric layer and the photoresist layer in the array region in the same step by adopting a third dry etching process.
4. The method for manufacturing the semiconductor structure according to claim 3, wherein an etching selection ratio of the third dry etching process to the photoresist layer and the first lower dielectric layer is 0.8-1.2.
5. The method of claim 2, wherein the thickness of the insulating layer above the dielectric layer is between 35nm and 45 nm.
6. The method for manufacturing a semiconductor structure according to claim 1, wherein an etching selection ratio of the first dry etching process to the first upper dielectric layer and the insulating layer is 0.8-1.2.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein an etching selection ratio of the second dry etching process to the second upper dielectric layer to the insulating layer is 0.8-1.2.
8. The method of claim 1, further comprising, after forming the conductive layer: and forming a third mask layer and a second mask layer which are stacked on the conductive layer, wherein the first mask layer is also positioned on the second mask layer.
9. The method of claim 8, wherein the step of etching a portion of the conductive layer and a portion of the active region in the array region using the patterned first mask layer as a mask to form contact holes comprises:
etching a part of the second mask layer positioned in the array area by taking the patterned first mask layer as a mask to form the patterned second mask layer, and simultaneously removing the second lower dielectric layer and a part of the first mask layer positioned in the core area and removing the third lower dielectric layer and the first mask layer positioned in the peripheral area;
etching a part of the third mask layer in the array area by using the patterned second mask layer as a mask through a fourth dry etching process to form the patterned third mask layer, and simultaneously removing the insulating layer and the first mask layer in the core area;
and etching part of the conductive layer and part of the active area in the array area by taking the patterned third mask layer as a mask so as to form the contact hole.
10. The method for manufacturing a semiconductor structure according to claim 9, wherein an etching selection ratio of the fourth dry etching process to the insulating layer and the second mask layer is greater than 10; and the etching selection ratio of the fourth dry etching process to the first mask layer and the second mask layer is greater than 10.
11. The method of claim 8, wherein a thickness of the second mask layer is greater than a thickness of the second lower dielectric layer.
12. The method of claim 8, wherein the material of the first mask layer comprises silicon oxynitride, and the material of the second mask layer comprises a carbon material or a carbon-containing compound.
13. The method according to claim 8, wherein a material of the third mask layer is the same as a material of the insulating layer.
14. The method of claim 13, wherein a material of the third mask layer and a material of the insulating layer comprise silicon oxide.
15. The method of claim 1, wherein the insulating layer is formed by an atomic layer deposition process.
CN202110363878.1A 2021-04-02 2021-04-02 Method for manufacturing semiconductor structure Active CN113113303B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110363878.1A CN113113303B (en) 2021-04-02 2021-04-02 Method for manufacturing semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110363878.1A CN113113303B (en) 2021-04-02 2021-04-02 Method for manufacturing semiconductor structure

Publications (2)

Publication Number Publication Date
CN113113303A CN113113303A (en) 2021-07-13
CN113113303B true CN113113303B (en) 2022-06-24

Family

ID=76713830

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110363878.1A Active CN113113303B (en) 2021-04-02 2021-04-02 Method for manufacturing semiconductor structure

Country Status (1)

Country Link
CN (1) CN113113303B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658955B (en) * 2021-08-12 2024-03-29 长鑫存储技术有限公司 Semiconductor structure and forming method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110126931A (en) * 2010-05-18 2011-11-24 주식회사 하이닉스반도체 Method for forming bit line contact of semiconductor device
US9905569B1 (en) * 2016-08-24 2018-02-27 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN108257919A (en) * 2016-12-29 2018-07-06 联华电子股份有限公司 Stochastic and dynamic handles the forming method of memory component
CN108666312A (en) * 2017-03-30 2018-10-16 联华电子股份有限公司 Dynamic RAM element and preparation method thereof with embedded flash memories
CN108899321A (en) * 2018-07-20 2018-11-27 上海华虹宏力半导体制造有限公司 The manufacturing method of flash memory
CN112582261A (en) * 2019-09-27 2021-03-30 长鑫存储技术有限公司 Method for manufacturing memory node contact window

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100782488B1 (en) * 2006-08-24 2007-12-05 삼성전자주식회사 Semiconductor device having buried interconnections and method of fabricating the same
KR20130089120A (en) * 2012-02-01 2013-08-09 에스케이하이닉스 주식회사 Methods for fabricating semiconductor device with fine pattenrs

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110126931A (en) * 2010-05-18 2011-11-24 주식회사 하이닉스반도체 Method for forming bit line contact of semiconductor device
US9905569B1 (en) * 2016-08-24 2018-02-27 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN108257919A (en) * 2016-12-29 2018-07-06 联华电子股份有限公司 Stochastic and dynamic handles the forming method of memory component
CN108666312A (en) * 2017-03-30 2018-10-16 联华电子股份有限公司 Dynamic RAM element and preparation method thereof with embedded flash memories
CN108899321A (en) * 2018-07-20 2018-11-27 上海华虹宏力半导体制造有限公司 The manufacturing method of flash memory
CN112582261A (en) * 2019-09-27 2021-03-30 长鑫存储技术有限公司 Method for manufacturing memory node contact window

Also Published As

Publication number Publication date
CN113113303A (en) 2021-07-13

Similar Documents

Publication Publication Date Title
CN113113303B (en) Method for manufacturing semiconductor structure
KR100824994B1 (en) Method for forming contact hole in semiconductor device
KR20070113604A (en) Method for forming micro pattern of semiconductor device
KR100613392B1 (en) Method for fabricating self aligned contact hole
KR100680948B1 (en) Method for manufacturing storage node contact of semiconductor device
KR100832015B1 (en) Method for forming contact hole in semiconductor device
KR20030000592A (en) method for manufacturing of semiconductor device with STI/DTI structure
CN112908836B (en) Semiconductor structure and forming method thereof
JP4257357B2 (en) Manufacturing method of semiconductor device
CN113496944A (en) Method for forming semiconductor structure
KR20070000719A (en) Method for forming bit line contact of semiconductor device
KR100772077B1 (en) A method for forming contact hole of semiconductor device
KR100273322B1 (en) Method for fabricating semiconductor device
KR100723769B1 (en) Method of manufacturing in flash memory device
KR100427718B1 (en) Method for manufacturing a semiconductor device
KR20080076235A (en) Method of forming a dual damascene pattern in a semiconductor device
CN116417332A (en) Method for manufacturing semiconductor structure
KR100344826B1 (en) Method for fabricating node contact of semiconductor device
KR100772699B1 (en) Method for forming semiconductor device
KR20060113265A (en) Method for manufacturing semiconductor device using recess gate process
CN113782428A (en) Semiconductor structure and forming method thereof
KR20090030507A (en) Method for fabricating semiconductor device
KR20100033024A (en) Method for forming a pattern of semiconductor device
KR20060002182A (en) A method for forming a semiconductor device
KR20080062011A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant