CN114388352A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114388352A
CN114388352A CN202011134152.2A CN202011134152A CN114388352A CN 114388352 A CN114388352 A CN 114388352A CN 202011134152 A CN202011134152 A CN 202011134152A CN 114388352 A CN114388352 A CN 114388352A
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China
Prior art keywords
layer
planarization
material layer
mask
etching
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CN202011134152.2A
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Chinese (zh)
Inventor
张冬平
张海洋
郑二虎
纪世良
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011134152.2A priority Critical patent/CN114388352A/en
Publication of CN114388352A publication Critical patent/CN114388352A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and method of forming the same, the method comprising: providing an initial substrate, wherein the initial substrate is provided with an etching hard mask and a planarization material layer positioned on the etching hard mask; performing a photolithography process on the planarization material layer to form a patterned planarization layer; etching the etching hard mask by taking the patterned planarization layer as a mask to form a patterned etching hard mask layer; and etching the initial substrate by taking the patterned etching hard mask layer as a mask to form a target pattern. The scheme can improve the performance of the formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are widely used as the most basic semiconductor devices, and thus, as the density and integration of semiconductor devices increase, the feature size of transistors also becomes smaller.
Photolithography (photolithography) is a commonly used patterning method, and is one of the most critical techniques in semiconductor manufacturing processes. With the decreasing semiconductor process nodes, the self-aligned multiple patterning (SAMP) method has become a patterning method favored in recent years. The side wall is formed by substances generated by depositing two sides of a preset pattern, and the pattern transfer is realized by adopting a side wall image transfer technology. The method can increase the density of the patterns formed on the surface of the wafer, and further reduce the distance (pitch) between two adjacent patterns, thereby completing the manufacture of small-size patterns. This technique is commonly used for line/space formation. Wherein, SADP (Self-aligned Double Patterning) can increase the density of the pattern by 2 times, and SAQP (Self-aligned quad Patterning) can increase the density by 4 times. SAMP only needs one-time photoetching, and on one hand, mask position errors caused by multiple photoetching do not exist; on the other hand, the method has great cost advantage. The technology is widely applied to the field of 10 nm-level processing at present.
However, the conventional semiconductor structure still has the problem of poor performance.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve a photoetching process window so as to further improve the density and the structural performance of a formed semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing an initial substrate, wherein the initial substrate is provided with an etching hard mask and a planarization material layer positioned on the etching hard mask;
performing a photolithography process on the planarization material layer to form a patterned planarization layer;
etching the etching hard mask by taking the patterned planarization layer as a mask to form a patterned etching hard mask layer;
and etching the initial substrate by taking the patterned etching hard mask layer as a mask to form a target pattern.
Optionally, before forming the patterned planarization layer, the method further comprises: performing a material modification treatment process on part of the planarization material layer to form a reserved area of the planarization material layer, wherein the planarization material layer positioned on the side part of the reserved area is a non-reserved area; after the patterned planarization layer is formed, the method further includes removing the planarization layer corresponding to the non-reserved area to form the patterned planarization layer.
Optionally, the step of performing a material modification treatment process on a portion of the planarization material layer includes:
forming a first spin-on material layer on the planarization material layer;
forming a first Anti-reflective Coating (ARC) layer on the first spin-on material layer;
forming a patterned mask layer on the first anti-reflective material layer;
sequentially etching the first anti-reflection material layer and the first spin-coating material layer by using the patterned mask layer to form a patterned first anti-reflection layer and a patterned first spin-coating layer;
performing a material modification treatment process on the planarization material layer by taking the patterned first spin coating layer, the first anti-reflection layer and the first mask layer as masks to form a reserved area of the planarization material layer;
and after the material modification treatment process is executed, removing the patterned first spin-on coating, the first anti-reflection layer and the first mask layer.
Optionally, the material modification treatment process comprises an ion implantation process.
Optionally, the step of forming a patterned planarization layer comprises:
forming a bottom mandrel material layer and a plurality of discrete first mandrel layers on the bottom mandrel material layer on the planarization material layer after performing a material modification treatment process on a portion of the planarization material layer;
forming a first side wall mask layer covering the side wall of the first mandrel layer;
removing the first mandrel layer, and etching the bottom mandrel material layer by taking the first side wall mask layer as a mask to form a plurality of discrete second mandrel layers;
removing the first side wall mask layer;
forming a second side wall mask layer covering the side wall of the second mandrel layer;
removing the second mandrel layer, and etching the planarization material layer by taking the second side wall mask layer as a mask to form a patterned planarization layer;
and removing the second side wall mask layer.
Optionally, before forming the bottom mandrel material layer on the planarization material layer, further comprising: a first etch hard mask is formed over the planarization material layer.
Optionally, the material of the first etching hard mask is silicon oxide.
Optionally, prior to the plurality of discrete first mandrel layers on the bottom mandrel material layer, the method further comprises: a second etch hard mask is formed over the bottom mandrel material layer.
Optionally, the material of the second etching hard mask is silicon oxide.
Optionally, the process of removing the planarization layer corresponding to the non-reserved region is a wet etching process.
Optionally, the sizes of the reserved regions in the fin width direction are the same or different.
Optionally, a buffer material layer is further formed between the initial substrate and the etching hard mask.
Optionally, the material of the planarization material layer is amorphous silicon.
Optionally, the material of the etching hard mask is silicon nitride.
An embodiment of the present invention further provides a semiconductor structure, where the semiconductor structure includes:
an initial substrate;
an etching hard mask is arranged on the initial substrate;
a planarization material layer on the etch hard mask;
a plurality of discrete second mandrel layers on the layer of planarizing material.
Optionally, the material of the planarization material layer is amorphous silicon.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the scheme, an initial substrate is provided, and the initial substrate is provided with an etching hard mask and a planarization material layer positioned on the etching hard mask; performing a photolithography process on the planarization material layer to form a patterned planarization layer; etching the etching hard mask by taking the patterned planarization layer as a mask to form a patterned etching hard mask layer; and etching the initial substrate by taking the patterned etching hard mask layer as a mask to form a target pattern. Because the planarization material layer is formed on the etching hard mask after the etching hard mask is formed on the initial substrate, the subsequent patterning process of the mask layer can be carried out on the planarization material layer with a flat surface, the load Effect (Pattern Loading Effect) can be eliminated, the photoetching process window is improved, and the density and the structural performance of the formed semiconductor device are further improved.
Drawings
FIG. 1 is a flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 2 to 15 are schematic diagrams of intermediate structures formed in the steps of the method for forming a semiconductor structure according to the embodiment of the present invention.
Detailed Description
In Back End Of Line (BEOL) processing Of Fin Field Effect transistors (finfets), self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) is typically used to form a substrate and discrete fins on the substrate.
However, in the conventional self-aligned double patterning or self-aligned quadruple patterning process, the mask layer is patterned on the non-flat surface, thereby causing a loading effect and reducing the performance of the formed semiconductor structure.
In order to solve the above problems, in the technical method provided in the embodiment of the present invention, after the etching hard mask is formed on the initial substrate, the planarization material layer is formed on the etching hard mask, so that the patterning process of the subsequent mask layer can be performed on a flat surface, thereby eliminating a loading effect and improving the performance of the formed semiconductor structure.
Fig. 1 is a flow chart illustrating a method of forming a semiconductor structure in an embodiment of the invention. Referring to fig. 1, a method for forming a semiconductor structure in an embodiment of the present invention may specifically include:
step S101: providing an initial substrate, wherein the initial substrate is provided with an etching hard mask and a planarization material layer positioned on the etching hard mask;
step S102: performing a photolithography process on the planarization material layer to form a patterned planarization layer;
step S103: etching the etching hard mask by taking the patterned planarization layer as a mask to form a patterned etching hard mask layer;
step S104: and etching the initial substrate by taking the patterned etching hard mask layer as a mask to form a target pattern.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
A method for forming a semiconductor structure in an embodiment of the invention will be described in further detail with reference to fig. 2 to 15.
Referring to fig. 2, an initial substrate 100 is provided.
In a specific implementation, the initial base 100 is used for forming a substrate and discrete fins on the substrate by subsequent etching.
In this embodiment, the initial substrate 100 is made of silicon. In other embodiments, the initial substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and may also be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate, or other types of substrates. In still other embodiments, the initial base may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process foundation for a subsequent substrate formation, and the second semiconductor layer is used to provide a process foundation for a subsequent fin formation. In other embodiments, the initial substrate may further include other functional layers to be etched, for example: and a gate material layer.
Referring to fig. 3, an etch hard mask 110 and a planarization material layer 120 on the etch hard mask 110 are formed on an initial substrate 100.
The etching hard mask 110 is used to subsequently form an etching mask for etching the initial substrate 100 to form a target pattern.
In this embodiment, the material of the etching hard mask 110 is silicon nitride (SiN). In other embodiments, the material of the etch hard mask 110 may also be silicon oxide (SiO)2) Silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxycarbonitride (SiOCN), or combinations thereof.
The process of forming the etch hard mask 110 includes a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a thermal treatment process, or a combination thereof.
The planarization material layer 120 is used to provide a process foundation for the subsequent formation of a planarization layer.
In this embodiment, the material of the planarization material layer 120 is amorphous silicon.
The process of forming the planarization material layer 120 is an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or the like.
In this embodiment, before forming the etching hard mask 110 on the initial substrate 100, a step of forming a buffer material layer 105 on the initial substrate 100 is further included. The buffer material layer 105 is used to provide a buffer effect when forming the etching hard mask 110, and can enhance the adhesion between the initial substrate 100 and the etching hard mask 110, so that the problem of misalignment generated when forming the etching hard mask 110 directly on the initial substrate 100 can be avoided.
In this embodiment, the material of the buffer material layer 105 is silicon oxide.
In this embodiment, before forming the planarization material layer 120 on the etching hard mask 110, a step of forming a bottom etching hard mask 111 on the etching hard mask 110 is further included. The bottom etching hard mask 111 is used as an etching mask for etching the hard mask 110, and can be used for providing a buffer effect when forming the etching hard mask 110, so that the adhesion between the etching hard mask 110 and the planarization material layer 120 can be enhanced, and the problem of dislocation generated when directly forming the planarization material layer 120 on the etching hard mask 110 can be avoided.
Referring to fig. 4, a material modification process is performed on a portion of the planarization material layer 120 to form a remaining region I of the planarization material layer, where the planarization material layer located at the side of the remaining region I is a non-remaining region II.
In this embodiment, the material modification process is an ion implantation process, and the material of the planarization material layer 120 is amorphous silicon. Specifically, the etching selection ratio of the ion implantation region of the amorphous silicon can be increased through the ion implantation process, so that the ion implantation region in the amorphous silicon is reserved and removed after the patterned planarization layer is formed subsequently.
In this embodiment, the material of the planarization material layer 120 is amorphous silicon (a-Si).
The step of performing a material ion implantation process on a portion of the planarization material layer 120 includes: forming a first Spin-On Coating (Spin-On Coating) material layer (not shown) covering the planarization material layer 120, a first Anti-Reflection Coating (Si-ARC) material layer (not shown) On the first Spin-On material layer, and a patterned first mask layer (not shown) On the first Si-ARC layer; sequentially etching the first Si-ARC material layer and the first spin-on material layer by taking the patterned first mask layer as a mask to form a patterned first Si-ARC layer and the first spin-on layer; and performing an ion implantation process on the planarization material layer 120 by using the patterned first mask layer, the first Si-ARC and the first spin-on coating as masks to form a reserved region I of the planarization material layer 120, wherein a region of the planarization material layer 120, which is not subjected to the ion implantation process, is a non-reserved region II.
In this embodiment, the first Spin-On material layer is a Spin-On Carbon (SOC) material layer.
It is understood that, when the ion implantation process is performed on the planarization material layer 120, the amount of the target pattern (e.g., fin portion) formed on each of the remaining regions I can be controlled by controlling the size of each of the remaining regions I formed in the planarization material layer 120. Therefore, the size of each reserved area I in the embodiment of the present invention may be adjusted according to the number of the finally formed target patterns, so that the target patterns with different sparsities are formed in the initial substrate corresponding to each reserved area I.
In other embodiments, after forming the etching hard mask and the planarization material layer on the etching hard mask on the initial substrate, the photolithography process can be directly performed on the planarization material layer to form the patterned planarization layer, without performing a material modification process on the planarization material layer in advance, so as to form a target pattern with uniform pattern density by subsequently etching the initial substrate.
By forming the planarization material layer 120 on the etching hard mask 110, the film layer formed on the planarization material layer 120 can be formed on the planarization material layer having a flat surface in the subsequent process of patterning the planarization material layer 120 to form a patterned planarization layer, and the flatness of the surface of the film layer formed thereon can be improved, so that the loading effect can be eliminated, thereby improving the topography quality and the dimensional accuracy of the film layer formed on the planarization material layer 120 in the process of forming a semiconductor structure, and improving the performance of the formed semiconductor structure.
After a material modification treatment process is performed on a portion of the planarization material layer 120, a photolithography process is performed on the remaining region I and the non-remaining region II in the planarization material layer 120 to form a patterned planarization layer.
Fig. 5-13 illustrate schematic views of intermediate structures formed by steps of forming a patterned planarization layer, in an embodiment of the present invention. Referring to fig. 5 to 13, the step of forming the patterned planarization layer includes:
referring to fig. 5, a bottom mandrel material layer 130 is formed on the planarization material layer 120.
The bottom mandrel material layer 130 provides a process foundation for the subsequent formation of a patterned second mandrel layer. Wherein, a second sidewall mask layer formed on the sidewall of the second mandrel layer is used as a mask for patterning the etching hard mask 110.
After the second sidewall mask layer on the sidewall of the second mandrel layer is formed, the second mandrel layer needs to be removed, so the bottom mandrel material layer 130 is a material that is easy to be removed, and the process of removing the second mandrel layer has less damage to other film layers. In this embodiment, the material of the bottom mandrel material layer 130 is amorphous silicon. In other embodiments, the material of the bottom mandrel material layer is silicon nitride. In other embodiments, the material of the bottom mandrel material layer may also be amorphous carbon, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. In other embodiments, the material of the bottom mandrel material Layer may also be an Organic Dielectric Layer (ODL) material.
The process of forming the bottom mandrel material layer 130 is an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, or the like.
In this embodiment, before forming the bottom mandrel material layer 130, the method further includes: a first etch hard mask 121 is formed on the planarization material layer 120.
The first etch hard mask 121 is used to subsequently etch the etch mask of the planarization material layer 120 and may provide a buffer for the bottom mandrel material layer 130 that is subsequently formed on the first etch hard mask 121.
In this embodiment, the first etching hard mask 121 is made of silicon dioxide.
The process of forming the first etching hard mask 121 is an atomic layer deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
In this embodiment, after forming the bottom mandrel material layer 130, a step of forming a second etching hard mask 131 on the bottom mandrel material layer 130 is further included.
The second etch hard mask 131 serves as an etch mask for subsequent etching of the bottom mandrel material layer 130 and may provide a buffer for the top mandrel material layer subsequently formed thereon.
In this embodiment, the second etching hard mask 131 is made of silicon dioxide.
The second etching hard mask 131 is formed by an atomic layer deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
Referring to fig. 6, a plurality of discrete first mandrel layers 140 are formed on the bottom mandrel material layer 130.
The step of forming a plurality of discrete first mandrel layers 140 comprises: forming a top mandrel material layer on the bottom mandrel material layer 130, forming a second spin-on material layer (not shown) covering the top mandrel material layer, a second Si-ARC material layer (not shown) on the second spin-on material layer, and a patterned second mask layer (not shown) on the second Si-ARC layer; sequentially etching the second Si-ARC material layer and the second spin-on material layer by taking the patterned second mask layer as a mask to form a patterned second Si-ARC layer and the second spin-on layer; etching the top mandrel material layer with the patterned second mask layer, the second Si-ARC and the second spin-on layer as masks, forming a plurality of discrete first mandrel layers 140 on the bottom mandrel material layer 130; after the first mandrel layer 140 is formed, the patterned second mask layer, second Si-ARC layer, and second spin-on layer are removed.
In this embodiment, the material of the second spin-on material layer is SOC.
The top mandrel material layer provides a process basis for forming the first mandrel layer by subsequent etching. The first sidewall mask layer forming the sidewall of the first mandrel layer provides a process basis for etching the bottom mandrel material layer 130.
After forming the second sidewall mask layer on the sidewall of the first mandrel layer 140, the first mandrel layer 140 needs to be removed, so the top mandrel material layer is a material that is easy to be removed, and the process of removing the first mandrel layer 140 has less damage to other film layers. In this embodiment, the material of the top mandrel material layer is amorphous silicon. In other embodiments, the material of the top mandrel material layer is silicon nitride. In other embodiments, the material of the top mandrel material Layer may also be amorphous carbon, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or Organic Dielectric Layer (ODL) material.
The process for forming the top mandrel material layer is an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 7, a first sidewall mask layer 145 is formed to cover the sidewalls of the first mandrel layer 140.
The first sidewall mask layer 145 serves as a mask for subsequent patterning of the bottom mandrel material layer 130.
The first sidewall mask layer 145 includes: forming a first sidewall mask material layer (not shown) conformally covering bottom mandrel material layer 130 and first mandrel layer 140; the first sidewall mask material layer covering the bottom mandrel material layer 130 and the first sidewall mask material layer covering the top of the first mandrel layer 140 are removed, and only the first sidewall mask material layer covering the sidewall of the first mandrel layer 140 is remained as the first sidewall mask layer 145.
In this embodiment, in order to improve the uniformity of the thickness of the first sidewall mask material layer and reduce the difficulty in controlling the thickness of the first sidewall mask material layer, an atomic layer deposition process is used to form the first sidewall mask material layer. In other embodiments, the first sidewall mask material layer can also be formed by a chemical vapor deposition process.
In this embodiment, the first sidewall mask layer 145 is made of silicon nitride. Silicon nitride is a commonly used sidewall mask material in the SADP process. The hardness and the density of the silicon nitride are high, and the etching selectivity of the silicon nitride and the amorphous silicon is high, so that the probability of damage to the first side wall mask layer 145 in the subsequent process of removing the first mandrel layer 140 can be reduced.
In this embodiment, when the second etch hard mask 131 is also formed on the bottom mandrel material layer 130, the first sidewall mask material layer conformally covers the second etch hard mask 131 and the first mandrel layer 140.
In this embodiment, an anisotropic maskless dry etching (blanket dry etch) process is used to selectively etch the first sidewall mask material layer along the normal direction of the surface of the initial substrate 100, so as to form the first sidewall mask layer 145 on the sidewall of the first mandrel layer 140.
Referring to fig. 8, after the first sidewall mask layer 145 is formed, the first mandrel layer 140 is removed.
The first mandrel layer 140 is removed to provide a process foundation for the subsequent patterning of the bottom mandrel material layer 130.
In this embodiment, the first mandrel layer 140 is removed by etching using a wet etching process. Specifically, the first mandrel layer 140 is made of amorphous silicon, and the etching solution adopted in the wet etching process is Cl2And HBr or TMAH (Tetra-Methyl Ammonium Hydroxide). In other embodiments, the first mandrel layer 140 may be removed by a dry etching process or a combination of dry etching and wet etching.
Referring to fig. 9, the bottom mandrel material layer 130, a plurality of discrete second mandrel layers 135, is etched using the first sidewall mask layer 145 as a mask.
The second mandrel layer 135 provides a foundation for the subsequent formation of a second sidewall mask layer. In subsequent processes, the second sidewall mask layer is formed on the sidewall of the second mandrel layer 135, and the second sidewall mask layer is used to pattern the planarization material layer 120 to form a patterned planarization layer.
In this embodiment, the material of the second mandrel layer 135 is amorphous silicon.
In this embodiment, the second etching hard mask 131 is formed on the bottom mandrel material layer 130 along the direction from the initial substrate 100 to the bottom mandrel material layer 130, so that the second etching hard mask 131 and the bottom mandrel material layer 130 are sequentially etched by using the dry etching process with the first sidewall mask layer 145 as a mask, and a patterned second etching hard mask layer (not shown) and a second mandrel layer 135 are formed.
After forming the plurality of discrete second mandrel layers 135, a step of removing the first sidewall mask layer 145 is included.
When the second etching hard mask 131 is formed on the bottom mandrel material layer 130, after the first sidewall mask layer 145 is removed, a step of removing the patterned second etching hard mask layer is further included.
Referring to fig. 10, a second sidewall mask layer 155 is formed on the sidewall of the second mandrel layer 135.
The second sidewall mask layer 155 serves as a mask for patterning the planarization material layer 120.
In this embodiment, the second sidewall mask layer 155 is made of silicon nitride. The material of the second sidewall mask layer 155 can be described with reference to the aforementioned description of the first sidewall mask layer 135, and is not described herein again.
Specifically, the step of forming the second sidewall mask layer 155 includes: forming a second sidewall mask material layer conformally covering the second mandrel layer 135 and the planarizing material layer 120; the second sidewall mask material layer on the top of the second mandrel layer 135 and on the planarization material layer 120 is removed by a maskless etching process, and the remaining second sidewall mask material layer on the sidewall of the second mandrel layer 135 is retained as a second sidewall mask layer 155.
For a detailed description of the step of forming the second sidewall mask layer 155, reference may be made to the above description of forming the first mask sidewall 135, which is not repeated herein.
Referring to fig. 11, after forming the second sidewall mask layer 155, the second mandrel layer 135 is removed.
Removing second mandrel layer 135 provides a process foundation for subsequent patterning of the planarization material layer 120.
In this embodiment, the second mandrel layer 135 is removed by etching using a wet etching process. For a detailed description of the process of removing the second mandrel layer 135, reference may be made to the corresponding description of the process of removing the first mandrel layer 140, and details are not repeated here.
Referring to fig. 12, the planarization material layer 120 is etched using the second sidewall mask layer 155 as a mask to form a patterned planarization layer 125.
Planarization layer 125 provides a process foundation for patterned etching of hard mask 110.
The process of forming the patterned planarization layer 125 is a dry etching process. Specifically, the second sidewall mask layer 155 is used as a mask, and the first etching hard mask 121 and the planarization material layer 120 are sequentially etched by using a dry etching process to form a patterned first etching hard mask layer (not shown) and a planarization layer 125.
After the patterned planarization layer 125 is formed, the steps of removing the second sidewall mask layer 155 and the first etching hard mask layer are included. In this embodiment, the second sidewall mask layer 155 and the remaining first etching hard mask layer are removed by etching using a wet etching process. In other embodiments, the second sidewall mask layer 155 and the first etching hard mask layer may be etched and removed by a dry etching process.
Referring to fig. 13, after forming the patterned planarization layer 125, the planarization layer 125 corresponding to the non-reserved region II is removed to form a patterned planarization layer 126.
The planarization layer 126 provides a process foundation for the patterned etch hard mask 110.
In this embodiment, the process of removing the planarization layer 125 corresponding to the non-reserved region II is a wet etching process.
Since the planarization layer corresponding to the reserved region I in the patterned planarization layer 125 is subjected to the material modification treatment process, the etching selection rate of the wet etching process on the planarization layer 125 corresponding to the reserved region I is higher than the etching selection rate of the planarization layer 125 corresponding to the non-reserved region II, the planarization layer 125 corresponding to the non-reserved region II can be removed quickly, the influence on the planarization layer 125 corresponding to the reserved region I is small, the maintenance of the topography quality of the planarization layer 125 corresponding to the reserved region I is facilitated, and the topography quality of the formed target pattern can be improved.
It should be noted that the number of the discrete planarization layers 126 in the planarization layer 125 corresponding to each of the remaining regions I may be the same or at least partially different, and may be controlled by the size of each of the remaining regions I formed when the material modification treatment process is performed on a portion of the planarization material layer 120, which is not limited herein.
As can be seen from the above description, the pattern density of the corresponding film layer is uniform before the formation of the patterned planarization layer 126, i.e., during the formation of the patterned planarization layer 125, so that the loading effect caused by the non-uniform pattern density can be eliminated, the pattern quality of the corresponding film layer can be improved, and the quality of the finally formed semiconductor structure can be improved.
Referring to fig. 14, the etch hard mask 110 is etched using the patterned planarization layer 126 as a mask to form a patterned etch hard mask layer 115.
The process of forming the patterned etch hard mask layer 115 is a dry etch process. Specifically, the bottom etching hard mask 111 and the etching hard mask 110 are sequentially etched by using the patterned planarization layer 126 as a mask and using a dry etching process to form a patterned etching hard mask layer 111 'and the etching hard mask layer 110'.
Referring to fig. 15, the initial substrate 100 is etched using the patterned etching hard mask layer 111' as a mask to form a target pattern 101.
In this embodiment, after patterning the initial substrate 100, the remaining initial substrate 100 is used as a substrate 102, the target pattern 102 is a fin portion, and the fin portion 101 and the substrate 102 are integrated.
The process of forming the target pattern 101 is a dry etching process. Specifically, the patterned etching hard mask layer 111 ' and the etching hard mask layer 110 ' are used as masks, the buffer material layer 105 and the initial substrate 100 are sequentially etched by using a dry etching process to form the patterned buffer layer 105 ' and the fin portion 101, and the remaining initial substrate 100 is used as the substrate 102.
In other embodiments, when the initial substrate includes a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, in the step of etching the substrate, only the first semiconductor layer is etched, the first semiconductor layer is used as a substrate, and the remaining second semiconductor layer protruding from the first semiconductor layer is used as a fin portion. Accordingly, the material of the fin may also be different from the material of the substrate.
Correspondingly, the embodiment of the invention also provides a semiconductor structure.
With continued reference to fig. 11, the semiconductor structure includes: an initial substrate 100; the initial substrate has an etch hard mask 105 thereon; a planarization material layer 120 on the etch hard mask; a plurality of discrete second mandrel layers 155 on the layer of planarizing material.
In this embodiment, the material of the planarization material layer 120 is amorphous silicon.
In this embodiment, the planarization material layer 120 has a reserved area I and a non-reserved area II located at the side of the reserved area I.
It is understood that by controlling the size of the remaining regions I formed in the planarization material layer 120, the number of target patterns (e.g., fins) formed on each remaining region I can be controlled. Therefore, the size of each reserved area I in the embodiment of the present invention may be adjusted according to the number of the finally formed target patterns, so that the target patterns with different sparsities are formed in the initial substrate corresponding to each reserved area I.
In other embodiments, the planarization material layer may also have no reserved area and no reserved area, so as to form a target pattern with uniform pattern density by etching the initial substrate.
In this embodiment, a buffer material layer 105 is further disposed between the initial substrate 100 and the etching hard mask 110. The buffer material layer 105 is used to provide a buffer effect when forming the etching hard mask 110, and can enhance the adhesion between the initial substrate 100 and the etching hard mask 110, so that the problem of misalignment generated when forming the etching hard mask 110 directly on the initial substrate 100 can be avoided.
In this embodiment, a bottom etching hard mask 111 is further disposed between the etching hard mask 110 and the planarization material layer 120. The bottom etching hard mask 111 is used as an etching mask for etching the hard mask 110, and can be used for providing a buffer effect when forming the etching hard mask 110, so that the adhesion between the etching hard mask 110 and the planarization material layer 120 can be enhanced, and the problem of dislocation generated when directly forming the planarization material layer 120 on the etching hard mask 110 can be avoided.
In this embodiment, a first etch hard mask 121 is further disposed between the planarization material layer 120 and the plurality of discrete second mandrel layers 155. The first etch hard mask 121 is used to subsequently etch the etch mask of the planarization material layer 120 and may provide a buffer for the bottom mandrel material layer 130 that is subsequently formed on the first etch hard mask 121.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing an initial substrate, wherein the initial substrate is provided with an etching hard mask and a planarization material layer positioned on the etching hard mask;
performing a photolithography process on the planarization material layer to form a patterned planarization layer;
etching the etching hard mask by taking the patterned planarization layer as a mask to form a patterned etching hard mask layer;
and etching the initial substrate by taking the patterned etching hard mask layer as a mask to form a target pattern.
2. The method of claim 1, further comprising, prior to forming the patterned planarization layer: performing a material modification treatment process on part of the planarization material layer to form a reserved area of the planarization material layer, wherein the planarization material layer positioned on the side part of the reserved area is a non-reserved area; after the patterned planarization layer is formed, the method further includes removing the planarization layer corresponding to the non-reserved area to form the patterned planarization layer.
3. The method of claim 2, wherein the step of performing a material modification treatment process on the portion of the planarization material layer comprises:
forming a first spin-on material layer on the planarization material layer;
forming a first anti-reflection material layer on the first spin-coating material layer;
forming a patterned mask layer on the first anti-reflective material layer;
sequentially etching the first anti-reflection material layer and the first spin-coating material layer by using the patterned mask layer to form a patterned first anti-reflection layer and a patterned first spin-coating layer;
performing a material modification treatment process on the planarization material layer by taking the patterned first spin coating layer, the first anti-reflection layer and the first mask layer as masks to form a reserved area of the planarization material layer;
and after the material modification treatment process is executed, removing the patterned first spin-on coating, the first anti-reflection layer and the first mask layer.
4. The method of claim 3, wherein the material modification treatment process comprises an ion implantation process.
5. The method of claim 2, wherein the step of forming the patterned planarization layer comprises:
forming a bottom mandrel material layer and a plurality of discrete first mandrel layers on the bottom mandrel material layer on the planarization material layer after performing a material modification treatment process on a portion of the planarization material layer;
forming a first side wall mask layer covering the side wall of the first mandrel layer;
removing the first mandrel layer, and etching the bottom mandrel material layer by taking the first side wall mask layer as a mask to form a plurality of discrete second mandrel layers;
removing the first side wall mask layer;
forming a second side wall mask layer covering the side wall of the second mandrel layer;
removing the second mandrel layer, and etching the planarization material layer by taking the second side wall mask layer as a mask to form a patterned planarization layer;
and removing the second side wall mask layer.
6. The method as claimed in claim 2, wherein the step of removing the planarization layer corresponding to the non-reserved region is a wet etching process.
7. The method of claim 1, wherein a buffer material layer is further formed between the initial substrate and the etch hard mask.
8. The method of claim 1, wherein the material of the planarization material layer is amorphous silicon.
9. A semiconductor structure, comprising:
an initial substrate;
an etching hard mask is arranged on the initial substrate;
a planarization material layer on the etch hard mask;
a plurality of discrete second mandrel layers on the layer of planarizing material.
10. The semiconductor structure of claim 9, wherein the material of the planarization material layer is amorphous silicon.
CN202011134152.2A 2020-10-21 2020-10-21 Semiconductor structure and forming method thereof Pending CN114388352A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504610A (en) * 2023-06-21 2023-07-28 长鑫存储技术有限公司 Mask structure, pattern forming method and preparation method of semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504610A (en) * 2023-06-21 2023-07-28 长鑫存储技术有限公司 Mask structure, pattern forming method and preparation method of semiconductor structure
CN116504610B (en) * 2023-06-21 2023-11-17 长鑫存储技术有限公司 Mask structure, pattern forming method and preparation method of semiconductor structure

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