CN111009461B

CN111009461B - Method for manufacturing semiconductor device

Info

Publication number: CN111009461B
Application number: CN201911164621.2A
Authority: CN
Inventors: 刘峻; 傅晓娟
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-11-25
Filing date: 2019-11-25
Publication date: 2021-03-09
Anticipated expiration: 2039-11-25
Also published as: CN111009461A

Abstract

The present invention relates to a method for manufacturing a semiconductor device, including: and sequentially forming a third core mold layer, a third anti-reflection layer, a second core mold layer, a second anti-reflection layer, a first core mold layer and a first anti-reflection layer on the target etching layer. Covering a first side wall material layer on the first core mold pattern in the etching process; etching the first sidewall material layer and the first mandrel pattern to form a first sidewall; etching partial thickness of the second anti-reflection layer by using the first side wall as a mask, and forming a plurality of first grooves in the exposed area of the second anti-reflection layer; covering a second side wall material layer on the second core mold pattern; etching the second sidewall material layer and the second mandrel pattern to form a second sidewall; etching partial thickness of the third anti-reflection layer by taking the second side wall as a mask, and forming a plurality of second grooves in the exposed area of the third anti-reflection layer; and covering a third side wall material layer on the third core mould pattern, and etching the third side wall material layer and the third core mould pattern to form a third side wall positioned on the target etching layer.

Description

Method for manufacturing semiconductor device

Technical Field

The present invention relates to the field of integrated circuit fabrication, and more particularly, to a method for fabricating a semiconductor device using self-aligned multiple patterns.

Background

In the field of integrated circuits, photolithography (lithographics) is a central element of IC fabrication, and is primarily used to transfer chip circuit patterns on a mask to a silicon wafer. The photolithographic process defines the dimensions of the semiconductor device. Current semiconductor devices have increasingly smaller requirements for feature size (Critical Dimension), for example, the channel length of field effect transistors has reached the deep sub-micron range. The smaller the feature size, the higher the integration of the chip, the better the performance, and the lower the power consumption. However, as the size is reduced, the influence on Line Edge Roughness (LER) of the pattern caused by the photoresist exposure process becomes more and more significant. Among the various methods sought to reduce feature size are 193nm immersion lithography, Extreme Ultraviolet (EUV) lithography, and the like. However, these techniques are relatively costly. Moreover, 193nm immersion lithography has not yet achieved process nodes of 14nm and below. Although the EUV lithography technology can reach smaller process nodes, the EUV photoresist still faces greater difficulties and challenges in terms of resolution, line edge roughness, sensitivity and the like, and the EUV photoresist does not have mass production capability at present. Therefore, new techniques are continually being explored to improve the performance of semiconductor devices at smaller feature sizes.

Disclosure of Invention

The invention aims to provide a manufacturing method of a semiconductor device, which can reduce line edge roughness and line width roughness of the semiconductor device under the requirement of smaller feature size.

The present invention is directed to a method for manufacturing a semiconductor device, including: sequentially forming a third core mold layer, a third anti-reflection layer, a second core mold layer, a second anti-reflection layer, a first core mold layer and a first anti-reflection layer on the target etching layer; etching the first anti-reflection layer and the first mandrel layer to form a first mandrel pattern; covering a first sidewall material layer on the first core pattern; etching the first side wall material layer and the first mandrel pattern to form a first side wall; etching partial thickness of the second anti-reflection layer by using the first side walls as masks, and forming a plurality of first grooves in exposed areas of the second anti-reflection layer; etching the second anti-reflection layer and the second mandrel layer to form a second mandrel pattern; covering a second sidewall material layer on the second mandrel pattern; etching the second side wall material layer and the second mandrel pattern to form a second side wall; etching part of the thickness of the third anti-reflection layer by using the second side walls as masks, and forming a plurality of second grooves in the exposed areas of the third anti-reflection layer; etching the third anti-reflection layer and the third mandrel layer to form a third mandrel pattern; covering a third layer of sidewall material over the third core pattern; and etching the third sidewall material layer and the third mandrel pattern to form a third sidewall on the target etching layer.

In an embodiment of the invention, before forming the third core mold layer, forming a hard mask layer on the target etching layer is further included.

In an embodiment of the present invention, the target etching layer has a buried etching stop layer therein.

In an embodiment of the present invention, when the first anti-reflection layer and the first mandrel layer are etched to form the first mandrel pattern, stopping on the second anti-reflection layer; and/or stopping on the third anti-reflection layer when the second anti-reflection layer and the second mandrel layer are etched to form a second mandrel pattern.

In an embodiment of the invention, when the first sidewall material layer and the first mandrel pattern are etched to form the first sidewall, the first sidewall material layer and the first mandrel pattern are stopped on the second anti-reflection layer; and stopping on the third anti-reflection layer when the second side wall material layer and the second mandrel pattern are etched to form a second side wall.

In an embodiment of the invention, after forming the first sidewall, the method further includes: reducing the height of the first side wall; and/or after forming the second side wall, the method further comprises the following steps: and reducing the height of the second side wall.

In an embodiment of the invention, after forming the groove in the exposed region of the second anti-reflection layer, the method further includes: removing the residual first side wall; and/or after the groove is formed on the exposed area of the third anti-reflection layer, the method further comprises the following steps: and removing the residual second side wall.

In an embodiment of the invention, when the third sidewall material layer and the third mandrel pattern are etched to form the third sidewall on the target etching layer, the etching is stopped on the hard mask layer.

In an embodiment of the invention, the method further includes etching the hard mask layer by using the third sidewall as a mask to form a hard mask pattern.

In an embodiment of the invention, the material of the hard mask layer is polysilicon.

In an embodiment of the invention, the material of the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer is titanium nitride, silicon oxynitride, silicon carbide or aluminum oxide.

In the manufacturing method of the semiconductor device, the second anti-reflection layer and the third anti-reflection layer have the function of etching barrier layers, and the patterns are transferred by forming the grooves on the second anti-reflection layer and the third anti-reflection layer, so that the heights of the first side wall and the second side wall are reduced, and the problem of collapse or inclination caused by overhigh side walls is avoided; the polycrystalline silicon is used as the material of the hard mask layer, so that the appearance of the pattern can be modified, and the line edge roughness and the line width roughness are improved.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIGS. 1A-1F are process flow diagrams of a self-aligned double patterning technique;

fig. 2 is an exemplary flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 3A-3S are process diagrams of a method of fabricating a semiconductor device according to an embodiment of the present invention;

fig. 4A-4C are schematic views of a portion of a semiconductor device fabrication process in accordance with an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

Multiple pattern exposure (Multiple Patterning) is one currently used lithography technique to reduce feature size and increase pattern density. Common Self-Aligned Patterning techniques among multiple pattern exposure techniques include Self-Aligned Double Patterning (SADP), Self-Aligned Quadruple Patterning (SAQP), and Self-Aligned octal Patterning (SAOP). With the increase of the number of times, the exposure times are increased, the more process steps are needed, the smaller the line width can be reached, and the higher the resolution is. These self-aligned patterning techniques may be collectively referred to as self-aligned multi-patterning techniques. Further, the eight-fold and above self-aligned pattern technique may be referred to as a self-aligned multi-pattern technique.

FIGS. 1A-1F are process flow diagrams of a self-aligned double patterning technique. Referring to fig. 1A, a lithography object to be SADP is, from the Bottom up, a substrate 101, a hard mask layer 102, a sacrificial layer 103, and a Bottom Anti-Reflective Coatings (BARC) 104 in this order. A layer of photoresist 110 is formed on the bottom anti-reflective coating 104, and the layer of photoresist 110 has a certain pattern according to the user's requirement, as shown in fig. 1A. Referring to fig. 1B, a pattern is transferred to the sacrificial layer 103 by etching, and a pattern layer formed after the sacrificial layer 103 is etched is referred to as a Mandrel pattern 103a, i.e., "Mandrel" or "Core", and thus, the sacrificial layer 103 may also be referred to as a Mandrel layer. Referring to fig. 1C, an Atomic Layer Deposition (ALD) technique is used to deposit a thin film with uniform thickness on the surface and side of the mandrel, which is referred to as a sidewall material 120, i.e., a "Spacer" material. Referring to fig. 1D, the sidewall material 120 formed in the previous step is etched using a reactive ion etching process, which is referred to as Etch Back (Etch Back). Due to the geometric effect of the mandrel sidewall, sidewall material deposited on both sides of the mandrel pattern may remain to form a sidewall 121, i.e., "Spacer". Referring to fig. 1E, the mandrel pattern 103a between the sidewalls 121 is removed using a more selective etchant, leaving only the sidewalls 121. Because the period of the remaining sidewall 121 (which refers to the period when the structures are regularly arranged according to a certain period in space and can represent the spatial density of the structures) is half of the period of the lithography pattern, the multiplication of the spatial pattern density is realized. Finally, referring to fig. 1F, the sidewall patterns formed in fig. 1E are transferred to the hard mask 102 of the substrate 101 by using plasma etching, so as to implement photolithography on the substrate.

The process flow of the techniques such as SAQP and SAOP is similar to SADP, and the number of times of photolithography needs to be increased on the basis of SADP, thereby further reducing the period of photolithography patterns and achieving further multiplication of the density of the space patterns.

In the self-aligned multi-pattern technology, the selection of mandrel, side wall and hard mask materials, and the control of the process parameters of deposition and etching of each material layer are all the keys of the success of the whole process. The process flow of each step needs to be accurately controlled, so that the line edge roughness and the line width roughness are improved while the spatial frequency doubling of the photoetching pattern is realized, and the characteristic size of the semiconductor device is effectively reduced.

The conventional SAOP manufacturing method can realize a line slot width (Slit Pitch) of about 20 nm. However, as the structure of a semiconductor device, especially for a 3D NAND memory, increases with the number of layers and the Aspect Ratio (Aspect Ratio), the etching of the sidewall material may cause the pattern to be formed to collapse. According to the manufacturing method of the semiconductor device, the existing SAOP process is improved, the pattern collapse phenomenon can be avoided, meanwhile, the line edge roughness is reduced, the line width roughness is improved, and the effects of saving the cost and improving the equipment yield are achieved.

Fig. 2 is an exemplary flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 3A to 3S are process diagrams of a method of manufacturing a semiconductor device according to an embodiment of the present invention. The manufacturing method of this embodiment will be described below with reference to fig. 2 and fig. 3A to 3S. The manufacturing method of this embodiment includes the steps of:

step 202, a third core mold layer, a third anti-reflection layer, a second core mold layer, a second anti-reflection layer, a first core mold layer and a first anti-reflection layer are sequentially formed on the target etching layer.

Referring to fig. 3A, a target etching layer 301 is an object to be etched using the manufacturing method of a semiconductor device of the present invention, and is also a main source material layer for performing a semiconductor thin film deposition process. The manufacturing method of the invention can be used in the field of integrated circuit manufacturing, such as 2D/3D NAND flash memory, RAM, MOS devices (CMOS, FET, FinFET) and the like. The target etch layer 301 varies from application to application. In some embodiments, the target etch layer 301 may be a substrate of a semiconductor device, such as a silicon substrate. In some embodiments, the target etch layer 301 may be a semiconductor precursor, such as: tetraethoxysilane (TEOS), borophospho (B, P) dopant, metal precursor, high-k precursor, low-k precursor, and the like. In a preferred embodiment of the present invention, the target etch layer 301 is TEOS.

As shown in fig. 3A, in some embodiments, target etch layer 301 has a buried etch stop layer 302 therein, and the material of etch stop layer 302 may be silicon nitride (SiN). The upper surface of the etch stop layer 302 is covered by the material of the target etch layer 301. Below the etch stop layer 302 there is a buried contact 303 in the target etch layer 301, the material of the contact 303 may be a metal, such as tungsten. As shown in FIG. 3A, a plurality of contacts 303 perpendicular to the surface of the target etch layer 301 are unevenly distributed in the target etch layer 301, and can be used for a metal interconnection structure between a semiconductor device to be formed and other semiconductor devices. It is understood that the size, location, spacing, etc. of the contacts 303 can be set according to the device requirements and are not limited to those shown in fig. 3A.

In the embodiment shown in FIG. 3A, a hard mask layer 304 is also formed on the target etch layer 301, and the material of the hard mask layer 304 may be polysilicon. A third core mold layer 323, a third anti-reflection layer 313, a second core mold layer 322, a second anti-reflection layer 312, a first core mold layer 321, and a first anti-reflection layer 311 are sequentially formed on the hard mask layer 304. The first anti-reflection layer 311, the second anti-reflection layer 312, and the third anti-reflection layer 313 may be made of titanium nitride (TiN), silicon oxynitride (SiON), silicon carbide (SiC), aluminum oxide (AlO), etc., and the first core mold layer 321, the second core mold layer 322, and the third core mold layer 323 may be made of amorphous Carbon (a-C), Spin-On Carbon (SOC), Ashable HardMask (AHM), Transparent Carbon (TC), etc. The materials of the first, second, and third

anti-reflection layers

311, 312, and 313 may be the same or different, and the materials of the first, second, and third core mold layers 321, 322, and 323 may be the same or different.

In a preferred embodiment, the materials of the first, second and third

anti-reflection layers

311, 312 and 313 are all silicon oxynitride, and the materials of the first, second and third core mold layers 321, 322 and 323 are all amorphous carbon.

As shown in fig. 3A, the thickness of the first anti-reflection layer 311 is relatively thin, and the thickness of the second and third

anti-reflection layers

312 and 313 is relatively thick and thicker than a conventional thickness. This is done to form a plurality of first grooves on the second anti-reflection layer 312 in the subsequent step 210 so as to transfer the upper pattern to the second anti-reflection layer 312, and to form a plurality of second grooves on the third anti-reflection layer 313 in the step 218 so as to transfer the upper pattern to the third anti-reflection layer 313.

In some embodiments, the second and third

anti-reflective layers

312, 313 are equal in thickness and both are greater than the thickness of the first anti-reflective layer 311.

In some embodiments, the thickness of second anti-reflective layer 312 and third anti-reflective layer 313 may also be less than or equal to the thickness of first anti-reflective layer 311, especially when they each use different materials.

Step 204, the first anti-reflection layer and the first mandrel layer are etched to form a first mandrel pattern.

In this step, in order to form the first core pattern 321a, a patterned photoresist layer 330 is first formed on the first anti-reflection layer 311, as shown in fig. 3A. The patterned photoresist layer 330 may be formed by photolithography of an initial photoresist layer laid on the first anti-reflection layer 311. The first anti-reflection layer 311 and the first core mold layer 321 are etched using the patterned photoresist layer 330 as a mask.

In some embodiments, this step can be divided into two steps:

firstly, etching the first anti-reflection layer 311 by using the patterned photoresist layer 330 as a mask, transferring a pattern to the first anti-reflection layer 311 to form a first anti-reflection layer pattern 311a, and cleaning the remaining photoresist layer 330;

second, the first core mold layer 321 is etched using the first anti-reflection layer pattern 311a as a mask, and the pattern is transferred to the first core mold layer 321 to form a first core mold pattern 321 a.

In some embodiments, the remaining photoresist layer 330 may not be cleaned in this first step, but the remaining photoresist layer 330 may be cleaned after the etching of the first core mold layer 321 is completed in the second step. The remaining photoresist layer 330 may be cleaned with an etchant.

In the embodiment shown in fig. 3B, the first anti-reflection layer pattern 311a is disposed over the first mold pattern 321a, via step 204. In other embodiments, after step 204, the first anti-reflection layer pattern 311a may be etched away, and only the first core pattern 321a is on the second anti-reflection layer 312.

In some embodiments, the etching of the first anti-reflection layer 311 and the first mold layer 321 in step 204 may stop on the second anti-reflection layer 312. In these embodiments, the material of the second anti-reflection layer 312 may be silicon oxynitride, and the second anti-reflection layer 312 has the function of an etching barrier layer.

At step 206, a first layer of sidewall material is overlaid on the first master pattern.

In this step, as shown in fig. 3C, a first sidewall material layer 341 is uniformly covered on the first core pattern 321a and the first anti-reflection layer pattern 311 a. This step may be performed using an Atomic Layer Deposition process (ALD). The material of the first sidewall material layer 341 may be an oxide or a metal (e.g., a low temperature metal). In a preferred embodiment, the material of the first sidewall material layer 341 is Ultra Low Temperature Oxide (ULTO). The ultra-low temperature oxide is adopted as the side wall material layer, so that better verticality, step coverage and selective etching ratio can be obtained, and the side wall material layer is easier to remove in the subsequent process.

Step 208, the first sidewall material layer and the first mandrel pattern are etched to form a first sidewall.

In some embodiments, step 208 may be divided into two steps:

in a first step, the first sidewall material layer 341 is etched.

As shown in fig. 3D, in this step, the first sidewall material layer 341 is partially etched, the first sidewall material parallel to the substrate surface direction X is removed, and the first sidewall material perpendicular to the substrate surface direction X is remained, i.e., the first sidewall 341a is remained. In some embodiments, the selective etching of the first sidewall material layer 341 may be achieved using an anisotropic barrier-free Dry Etch (Blanket Dry Etch) process.

In some embodiments, through the etching of the first sidewall material layer 341, the first anti-reflection layer pattern 311a and/or a portion of the first core pattern 321a may be simultaneously etched away.

Second, the first core pattern 321a is etched.

As shown in fig. 3E, after the second step, the first core pattern 321a and/or the first anti-reflection layer pattern 311a are etched away, and only the first sidewalls 341a perpendicular to the substrate surface direction X remain on the second anti-reflection layer 312.

Referring to fig. 3A and 3E, in fig. 3A, the photoresist layer 330 defines 2 lines having a line width d1 within a certain width, and a plurality of first line grooves 331 are formed between the lines; in fig. 3E, 4 lines having a line width d2 are formed by the first sidewall 341a within a certain width, and a plurality of second line grooves 341b are formed between the lines. Obviously, d2< d1, the width of the second line groove 341b is smaller than that of the first line groove 331. It can be appreciated that through steps 202 through 208, a first frequency doubling of the original lithographic pattern is achieved, increasing the spatial density of the lines, while reducing the width of the lines and wireways.

In some embodiments, the etching of the first sidewall material layer 341 and the first mold pattern 321a in step 208 may stop on the second anti-reflection layer 312. In these embodiments, the material of the second anti-reflection layer 312 may be silicon oxynitride, and the second anti-reflection layer 312 has the function of an etching barrier layer.

In some embodiments, after the first sidewalls 341a are formed, a step of reducing the height of the first sidewalls 341a is further included. This step may be performed separately after step 208 or may be performed in combination with step 210. Relevant matters will be described in step 210 with reference to the accompanying drawings.

Step 210, etching a part of the thickness of the second anti-reflection layer by using the first sidewall as a mask, and forming a plurality of first grooves in the exposed area of the second anti-reflection layer.

As shown in fig. 3E, the exposed area of the second anti-reflection layer 312 is the area on the second anti-reflection layer 312 not covered by the first sidewall 341 a. Referring to fig. 3F, the second anti-reflection layer 312 is etched by a partial thickness using the first sidewalls 341a as a mask. Before the etching of this step is performed, the thickness of the second anti-reflection layer 312 is assumed to be D1. By controlling the etching rate, the etching depth D2 of the exposed region of the second anti-reflection layer 312, that is, the depth of the first groove 312b, can be controlled. The first groove 312b does not penetrate the second anti-reflection layer 312 due to the partial thickness etching. In some embodiments, the etch depth D2 is 1/3 to 1/2 of the thickness D1. The pattern formed by the first sidewalls 314a may be transferred onto the second anti-reflection layer 312, via step 210. Here, the second anti-reflection layer 312 may be 50% to 100% thicker than the anti-reflection layer for a conventional use. For example, if the same material is used, the second anti-reflective layer 312 may be 50% -100% greater than the thickness of the first anti-reflective layer 311. Assuming that the material of the second anti-reflection layer 312 is SiON, the thickness thereof can be 300-1000 μm.

It is understood that the thickness of the second anti-reflection layer 312 formed in step 202 is thick so that the first groove 312b is formed with a sufficient thickness without being penetrated in step 210. Meanwhile, the etching process in step 208 may also have an etching effect on the second anti-reflection layer 312, so as to reduce the thickness of the second anti-reflection layer 312. Therefore, in step 202, considering the effect of the subsequent process on the second anti-reflection layer 312, a reasonable thickness of the second anti-reflection layer 312 can be calculated, so that the thickness of the second anti-reflection layer 312 is still enough to form the required groove when step 210 is executed.

In some embodiments, as shown in fig. 3F, the height of the first sidewalls 341a is reduced from H1 shown in fig. 3E to H2 shown in fig. 3F. In these embodiments, the height of the first sidewalls 341a may be reduced using an etching process before step 210 is performed. In other embodiments, in step 210, the first sidewalls 341a are etched while the second anti-reflection layer 312 is etched to form the first grooves 312b, so that the height of the first sidewalls 341a is reduced while the first grooves 312b are formed.

Since the height of the first sidewall 341a is reduced, it is possible to prevent the collapse or inclination problem from occurring due to the excessively high height of the first sidewall 341a in the subsequent process.

In some embodiments, after the first groove 312b is formed, a step of removing the remaining first sidewall 341a may be further included. As shown in fig. 3G, the first sidewalls 341a remaining on the second anti-reflection layer 312 may be cleaned away by wet etching. If the height of the remaining first sidewalls 341a is low, cleaning may not be required.

Through this step, a portion of the second anti-reflective layer 312 originally located under the first sidewall 341a forms a new pattern, i.e., the second anti-reflective layer pattern 312a, together with the first groove 312 b. The period of the second anti-reflective layer pattern 312a is the same as the pattern period of the first sidewalls 341a formed in step 208.

In step 212, the second anti-reflection layer and the second mandrel layer are etched to form a second mandrel pattern.

As shown in fig. 3G and 3H, the second anti-reflection layer 312 and the second core mold layer 322 are etched using the pattern formed on the second anti-reflection layer 312 in step 210, forming a second core mold pattern 322a as shown in fig. 3H. In some embodiments, the etch of this step stops on the third anti-reflective layer 313. In these embodiments, silicon oxynitride may be used as the material of the third anti-reflection layer 313, and the third anti-reflection layer 313 functions as an etching barrier.

Similarly to step 204, in the embodiment shown in fig. 3H, the second core mold pattern 322a has a second anti-reflective layer pattern 312a over it, via step 212. In other embodiments, after the step 212, the second anti-reflection layer pattern 312a may be etched away, with only the second mandrel pattern 322a on the third anti-reflection layer 313.

A second layer of sidewall material is placed over the second mandrel pattern, step 214.

In this step, as shown in fig. 3I, a second sidewall material layer 342 is uniformly coated on the second core pattern 322a and the second anti-reflection layer pattern 312 a. This step may be performed using an atomic layer deposition process. The material of the second sidewall material layer 342 can be an oxide or a metal. In a preferred embodiment, the material of the second sidewall material layer 342 is the same as the material of the first sidewall material layer 341, and is an ultra-low temperature oxide.

In step 216, the second sidewall material layer and the second mandrel pattern are etched to form a second sidewall.

This step is similar to step 208. In some embodiments, step 216 may be divided into two steps:

in the first step, the second sidewall material layer 342 is etched.

As shown in fig. 3J, the second sidewall material layer 342 is partially etched in this step, so that the second sidewall material parallel to the substrate surface direction X is removed, and the second sidewall material perpendicular to the substrate surface direction X is remained, i.e. the second sidewall 342a is remained. In some embodiments, an anisotropic barrier-free dry etch process may be used to achieve selective etching of the second sidewall material layer 342.

In some embodiments, the second anti-reflective layer pattern 312a and/or a portion of the second mandrel pattern 322a may be simultaneously etched away through the etching of the second sidewall material layer 342.

Second, the second mandrel pattern 322a is etched.

As shown in fig. 3K, through the second step, the second mandrel pattern 322a and/or the second anti-reflection layer pattern 312a are etched away, leaving only the second sidewall 342a perpendicular to the substrate surface direction X on the third anti-reflection layer 313.

In fig. 3K, 8 lines having a line width d3 are formed by the second sidewalls 342a within a certain width, and a plurality of third line grooves 342b are formed between the lines. As shown in fig. 3A, 3E and 3K, it can be understood that the line widths d2 and d3 are determined by the thickness of the first sidewall material layer 341 and the second sidewall material layer 342 overlaid on the first and

second mandrel patterns

321a and 322a, respectively. Therefore, the line width d2 and the line width d3 may be equal or different. It is apparent that the third line groove 342b has a width smaller than that of the second line groove 341 b.

Through steps 210 to 216, the second frequency doubling is performed on the photoetching pattern, so that the space density of lines is further increased, and the width of the wire grooves is reduced.

In some embodiments, the etching of the second sidewall material layer 342 and the second mandrel pattern 322a in the step 216 may stop on the third anti-reflection layer 313. In these embodiments, silicon oxynitride may be used as the material of the third anti-reflection layer 313, and the third anti-reflection layer 313 functions as an etching barrier.

In some embodiments, after the second sidewalls 342a are formed, a step of reducing the height of the second sidewalls 342a is further included. This step may be performed separately after step 216 or may be performed in combination with step 218. Relevant matters will be described in step 218 with reference to the accompanying drawings.

Step 218, etching a portion of the thickness of the third anti-reflection layer using the second sidewall as a mask to form a plurality of second grooves in the exposed region of the third anti-reflection layer.

As shown in fig. 3K, the exposed area of the third anti-reflection layer 313 is the area on the third anti-reflection layer 313 not covered by the second sidewall 342 a. Step 218 is similar to step 210, and referring to fig. 3L, the third anti-reflective layer 313 is partially etched using the second sidewall 342a as a mask. Before the etching of this step is performed, the thickness of the third antireflection layer 313 is assumed to be D3. By controlling the etching rate, the etching depth D4 of the exposed region of the third anti-reflection layer 313, that is, the depth of the second groove 313b, can be controlled. The second groove 313b does not penetrate the third anti-reflection layer 313 due to the partial thickness etching. In some embodiments, the etch depth D4 is 1/3 to 1/2 of the thickness D3. The pattern formed by the second sidewalls 342a may be transferred onto the third anti-reflection layer 313, via step 218. Here, the third anti-reflection layer 313 may be 50% to 100% greater than the thickness of the anti-reflection layer for general use. For example, if the same material is used, the third anti-reflection layer 313 may be 50% -100% greater than the thickness of the first anti-reflection layer 311. Assuming that the material of the third anti-reflection layer 313 is SiON, the thickness thereof can be 300-1000 μm.

It is understood that the thickness of the third anti-reflection layer 313 formed in step 202 is thick so that the second groove 313b is formed with a sufficient thickness without being penetrated in step 218. Meanwhile, the etching process in step 216 may also have an etching effect on the third anti-reflection layer 313, so as to reduce the thickness of the third anti-reflection layer 313. Therefore, in step 202, considering the effect of the subsequent process on the third anti-reflection layer 313, a reasonable thickness of the third anti-reflection layer 313 can be calculated, so that the thickness of the third anti-reflection layer 313 is still enough to form the required groove when step 218 is performed.

In some embodiments, as shown in fig. 3L, the height of the second sidewalls 342a is reduced from H3 shown in fig. 3K to H4 shown in fig. 3L. In these embodiments, the height of the second sidewall 342a may be reduced by an etching process before step 218 is performed. In other embodiments, in step 218, the second sidewall 342a is etched while the third anti-reflection layer 313 is etched to form the second groove 313b, so that the height of the second sidewall 342a is reduced while the second groove 313b is formed.

Since the height of the second side wall 342a is reduced, the problem of collapse or inclination caused by the over-height of the second side wall 342a in the subsequent process can be avoided.

In some embodiments, after the second groove 313b is formed, a step of removing the remaining second sidewall 342a may be further included. As shown in fig. 3L, the second sidewalls 342a remaining on the third anti-reflection layer 313 may be cleaned away by wet etching. If the height of the remaining second side walls 342a is low, cleaning may not be required.

Through this step, a portion of the third anti-reflection layer 313 originally located under the second sidewall 342a forms a new pattern, i.e., the third anti-reflection layer pattern 313a, together with the second groove 313 b. The period of the third anti-reflective layer pattern 313a is the same as the pattern period of the second sidewalls 342a formed in step 216.

Step 220, the third anti-reflection layer and the third mandrel layer are etched to form a third mandrel pattern.

As shown in fig. 3M and 3N, the third anti-reflection layer 313 and the third mandrel layer 323 are etched using the pattern formed on the third anti-reflection layer 313 at step 218, forming a third mandrel pattern 323a as shown in fig. 3N. In the embodiment where the hard mask layer 304 is formed on the target etch layer 301, the etch of this step stops on the hard mask layer 304.

Similarly to step 212, in the embodiment shown in fig. 3N, the third core mold pattern 323a has a third anti-reflection layer pattern 313a thereon, via step 220. In other embodiments, after step 220, the third anti-reflective layer pattern 313a may be etched away, with only the third core pattern 323a on the hard mask layer 304.

Step 222, a third layer of sidewall material is overlaid on the third core pattern.

Similarly to the step 214, as shown with reference to fig. 3O, a third sidewall material layer 343 is uniformly coated on the third core pattern 323a and the third anti-reflection layer pattern 313 a. This step may be performed using an atomic layer deposition process. The material of the third sidewall material layer 343 may be an oxide or a metal. In a preferred embodiment, the material of the third sidewall material layer 343 is the same as the material of the first and second sidewall material layers 341 and 342, and is an ultra-low temperature oxide.

Step 224, the third sidewall material layer and the third mandrel pattern are etched to form a third sidewall on the target etch layer.

This step is similar to step 216. In some embodiments, step 224 may be divided into two steps:

first, the third sidewall material layer 343 is etched.

As shown in fig. 3P, in this step, the third sidewall material layer 343 is partially etched, the third sidewall material parallel to the substrate surface direction X is removed, and the third sidewall material perpendicular to the substrate surface direction X is remained, that is, the third sidewall 343a is remained. In some embodiments, an anisotropic barrier-free dry etching process may be used to selectively etch the third sidewall material layer 343.

In some embodiments, through the etching of the third sidewall material layer 343, the third anti-reflection layer pattern 313a and/or a portion of the third core pattern 323a may be simultaneously etched away.

Second, the third core pattern 323a is etched.

As shown in fig. 3Q, through the second step, the third core pattern 323a and/or the third anti-reflective layer pattern 313a are etched away, leaving only the third sidewall 343a perpendicular to the substrate surface direction X on the hard mask layer 304.

In fig. 3Q, 16 lines having a line width d4 are formed from the third side walls 343a within a certain width, and a plurality of fourth line grooves 343b are formed between the lines. As shown in fig. 3A, 3E, 3K and 3Q, it can be understood that the line widths d2, d3 and d4 are determined by the thickness of the first sidewall material layer 341, the second sidewall material layer 342 and the third sidewall material layer 343 overlying the first, second and

third core patterns

321a, 322a and 323A, respectively. Therefore, the line widths d2, d3, d4 may or may not be equal. Obviously, the width of the fourth line groove 343b is smaller than the width of the third line groove 343 b.

In embodiments having a hard mask layer 304 on the target etch layer 301, the etching of the third sidewall material layer 343 and the third core pattern 323a in step 224 may stop on the hard mask layer 304. In these embodiments, the hard mask layer 304 may be made of polysilicon, and the hard mask layer 304 may function as an etch stop layer.

In some embodiments, after the third side walls 343a are formed, a step of reducing the height of the third side walls 343a is further included. As shown in fig. 3R, the height of the third sidewall 343a may be reduced by an etching process. This can prevent the collapse or inclination of the third side wall 343a caused by an excessively high height in the subsequent process.

In embodiments without the hard mask layer 304, the third sidewall 343a is formed directly on the target etch layer 301.

Through steps 218 to 224, the third frequency doubling is performed on the photolithography pattern, so that the spatial density of the lines is further increased, and the width of the line grooves is reduced.

Referring to fig. 3S, in some embodiments, the method for manufacturing a semiconductor device of the present invention further includes etching the hard mask layer 304 using the third sidewall 343a as a mask to form a hard mask pattern 304 a. For the target etch layer 301 including the hard mask layer 304, the target etch layer 301 may be continuously etched using the hard mask pattern 304a through this step. In a preferred embodiment of the present invention, the material of the hard mask layer 304 is polysilicon. Due to the physical characteristics of the polysilicon, the formed hard mask pattern 304a has good verticality, so that a line slot with good verticality can be obtained on the target etching layer 301, the pattern morphology can be further modified, and the line edge roughness and the line width roughness can be improved.

Through the steps 202 to 224, the method for manufacturing a semiconductor device of the present invention successfully transfers the pattern to the target etching layer 301, and performs frequency doubling on the initial lithographic pattern 3 times, so that a result eight times (3 times of 2) the density of the initial lithographic pattern can be achieved on the target etching layer 301. Practice proves that according to the manufacturing method of the semiconductor device, the line groove width of 10nm can be obtained at the process node below 5 nm.

In the method for manufacturing a semiconductor device of the present invention, dry etching may be used for the first antireflection layer, the first core mold layer, the second antireflection layer, the second core mold layer, the third antireflection layer, and the third core mold layer.

Fig. 4A-4C are schematic views of a portion of a semiconductor device fabrication process in accordance with an embodiment of the present invention. The in-process semiconductor device structure shown in fig. 4A-4C is based on the semiconductor device structure obtained through the manufacturing process of steps 202 to 224, and processing of the semiconductor device structure is continued as shown with reference to fig. 4A-4C. The foregoing description of the method of manufacturing a semiconductor device using a self-aligned quad pattern and the accompanying drawings may be used to illustrate and explain the semiconductor device shown in fig. 4A-4C.

In the embodiment shown in FIGS. 4A-4C, a hard mask layer 304 is formed on the target etch layer 301. Referring to step 224 and fig. 3S, the hard mask layer 304 is etched using the third sidewalls 343a as a mask, so as to form a hard mask pattern 304 a. Referring to fig. 4A, the third sidewalls 343a remaining on the hard mask pattern 304A of fig. 3S are cleaned. The remaining third side walls 343a may be cleaned by wet etching. In some embodiments, the cleaning of the third sidewalls 343a may etch away a portion of the hard mask pattern 304a, thereby reducing the height of the hard mask pattern 304 a.

Referring to fig. 4B, the target etch layer 301 thereunder is etched using the hard mask pattern 304a as a mask, and a target etch pattern 301a is formed in the target etch layer 301. In the embodiment shown in fig. 4B, target etch layer 301 has buried etch stop layer 302 therein, and etch stop layer 302 and target etch layer 301 are etched together to form etch stop pattern 302 a. A plurality of filled trenches 410 are formed between the respective lines in the target etch pattern 301 a.

Referring to fig. 4C, a metal 411, for example, copper, is filled in the plurality of filling grooves 410 formed in fig. 4B. Before the metal filling, the remaining hard mask pattern 304a may be removed, and an auxiliary material may be deposited in the filling trench 410 to help the metal to better adhere to the sidewall of the filling trench 410.

In the preferred embodiment of the present invention, the fill metal 411 is copper, and the auxiliary material deposited in the fill trench 410 is Ta \ TaN, which not only can make copper better adhere to the sidewalls of the fill trench 410, but also can prevent copper from diffusing into the target etch layer 301. The filling of the Copper metal can be performed by ecp (electrochemical Copper plating) plating.

After the metal filling is completed, the semiconductor device may be subjected to an annealing process and a planarization process by Chemical-Mechanical Polishing (CMP) to obtain a flat upper surface of the semiconductor device.

The semiconductor device obtained by the manufacturing method of the semiconductor device can improve the SAOP effect and line edge roughness and line width roughness under smaller process nodes (the characteristic size is 14nm and below), and can greatly save the cost and improve the equipment yield compared with the prior art such as 193nm immersion lithography technology, extreme ultraviolet lithography technology and the like.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, comprising:

sequentially forming a third core mold layer, a third anti-reflection layer, a second core mold layer, a second anti-reflection layer, a first core mold layer and a first anti-reflection layer on the target etching layer;

etching the first anti-reflection layer and the first mandrel layer to form a first mandrel pattern;

covering a first sidewall material layer on the first core pattern;

etching the first side wall material layer and the first mandrel pattern to form a first side wall;

etching part of the thickness of the second anti-reflection layer by using the first side walls as masks, forming a plurality of first grooves in exposed areas of the second anti-reflection layer, and reducing the height of the first side walls;

etching the second anti-reflection layer and the second mandrel layer to form a second mandrel pattern;

covering a second sidewall material layer on the second mandrel pattern;

etching the second side wall material layer and the second mandrel pattern to form a second side wall;

etching part of the thickness of the third anti-reflection layer by taking the second side wall as a mask, forming a plurality of second grooves in the exposed area of the third anti-reflection layer, and reducing the height of the second side wall;

etching the third anti-reflection layer and the third mandrel layer to form a third mandrel pattern;

covering a third layer of sidewall material over the third core pattern; and

and etching the third side wall material layer and the third mandrel pattern to form a third side wall on the target etching layer.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising forming a hard mask layer on the target etching layer before forming the third core mold layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the target etch layer has a buried etch stop layer therein.

4. The method for manufacturing a semiconductor device according to claim 1,

stopping on the second anti-reflection layer when the first anti-reflection layer and the first mandrel layer are etched to form a first mandrel pattern; and/or

Stopping on the third anti-reflection layer when the second anti-reflection layer and the second mandrel layer are etched to form a second mandrel pattern.

5. The method for manufacturing a semiconductor device according to claim 1,

stopping on the second anti-reflection layer when the first side wall material layer and the first mandrel pattern are etched to form a first side wall;

and stopping on the third anti-reflection layer when the second side wall material layer and the second mandrel pattern are etched to form a second side wall.

6. The method for manufacturing a semiconductor device according to claim 1,

after the groove is formed in the exposed area of the second antireflection layer, the method further comprises the following steps: removing the residual first side wall; and/or

After the groove is formed in the exposed area of the third antireflection layer, the method further comprises the following steps: and removing the residual second side wall.

7. The method of manufacturing a semiconductor device according to claim 2, wherein etching the third sidewall material layer and the third mandrel pattern to form a third sidewall on the target etch layer is stopped on the hard mask layer.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising etching the hard mask layer using the third sidewall as a mask to form a hard mask pattern.

9. The method for manufacturing a semiconductor device according to claim 2 or 7, wherein a material of the hard mask layer is polysilicon.

10. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the first anti-reflection layer, the second anti-reflection layer, and the third anti-reflection layer is titanium nitride, silicon oxynitride, silicon carbide, or aluminum oxide.