CN112951724A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN112951724A CN112951724A CN201911259681.2A CN201911259681A CN112951724A CN 112951724 A CN112951724 A CN 112951724A CN 201911259681 A CN201911259681 A CN 201911259681A CN 112951724 A CN112951724 A CN 112951724A
- Authority
- CN
- China
- Prior art keywords
- mask
- layer
- material layer
- side wall
- core layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 91
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000010410 layer Substances 0.000 claims abstract description 330
- 239000000463 material Substances 0.000 claims abstract description 271
- 239000012792 core layer Substances 0.000 claims abstract description 162
- 238000005530 etching Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000059 patterning Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims description 53
- 125000006850 spacer group Chemical group 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 claims description 4
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000012876 topography Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern; forming a core layer on the mask material layer; forming a mask side wall on the side wall of the core layer; etching part of the mask side wall to remove part of the mask side wall on any side wall of the core layer and expose part of the side wall of the core layer; etching part of the mask side wall, and then patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer; and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern. According to the invention, part of the mask side wall on any side wall of the core layer is removed in an etching mode, so that the appearance quality of the mask side wall and the appearance quality of the corner of the core layer are better, and the quality of a target pattern is favorably improved, thereby improving the performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
A commonly used patterning method in the field of semiconductor manufacturing is photolithography, which uses a photoresist material and a controlled exposure to transfer a mask pattern into one or more material layers, such as a metal layer, a dielectric layer, or a semiconductor substrate. However, due to the limitation of many factors, the minimum pitch (minimum pitch) of the patterns formed by the photolithography process limits the further reduction of the pattern size and the development of smaller and higher density integrated circuits.
In order to increase the integration of semiconductor devices, various double patterning processes have been proposed. In particular, self-aligned double patterning (SADP) is a patterning method that is favored in recent years, and can increase the density of patterns formed on a semiconductor substrate and further reduce the pitch between two adjacent patterns, thereby eliminating the limitation of the photolithography process on the semiconductor manufacturing field.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern; forming a core layer on the mask material layer; forming a mask side wall on the side wall of the core layer; etching part of the mask side wall to remove part of the mask side wall on any side wall of the core layer and expose part of the side wall of the core layer; etching part of the mask side wall, and then patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer; and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern.
Optionally, in the step of providing the substrate, the substrate includes a first region and a second region, and a width of a target pattern formed in the first region is smaller than a width of the target pattern formed in the second region; forming a core layer on the mask material layer, the core layer being located on the mask material layer of the first region and the second region; in the step of etching part of the mask side wall, etching part of the mask side wall in the second region; before patterning the mask material layer by using the remaining core layer and the mask side wall as masks, the forming method further includes: removing the core layer of the first region.
Optionally, after the mask side wall is formed, before etching a part of the mask side wall, removing the core layer in the first region; or, after etching treatment is carried out on part of the mask side wall, the core layer in the first region is removed.
Optionally, the step of removing the core layer of the first region includes: forming a first shielding layer on the mask material layer of the second region, wherein the first shielding layer covers the core layer and the mask side wall; removing the core layer in the first region by taking the first shielding layer as a mask; and removing the first shielding layer after removing the core layer of the first area.
Optionally, the step of performing etching treatment on part of the mask sidewall includes: forming a second shielding layer on the mask material layer, wherein the second shielding layer covers the top of the core layer and the top of the mask side wall, and the second shielding layer exposes the mask side wall to be etched on the core layer side wall; taking the second shielding layer as a mask, and removing the exposed mask side wall; and removing the second shielding layer after the exposed mask side wall is removed.
Optionally, during the etching process of the mask sidewall spacers in the second region, the mask sidewall spacers in the first region are further cut off in the extending direction of the mask sidewall spacers.
Optionally, an anisotropic dry etching process is used to perform etching treatment on part of the mask sidewall.
Optionally, the step of forming a mask sidewall on the sidewall of the core layer includes: forming a side wall material layer which conformally covers the core layer and the mask material layer; and removing the side wall material layers on the top of the core layer and the mask material layer, and reserving the side wall material layers on the side walls of the core layer as mask side walls.
Optionally, in the step of forming the core layer on the mask material layer, the width of the core layer in the first region is smaller than the width of the core layer in the second region.
Optionally, the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polycrystalline silicon, an ODL material, a DARC material or a BARC material, and the material of the mask sidewall is silicon oxide or silicon nitride, wherein the material of the mask material layer is different from the material of the mask sidewall.
Optionally, the material of the first shielding layer includes photoresist.
Optionally, the material of the second shielding layer includes photoresist.
Optionally, the material layer to be patterned is a fin portion material layer, and the target pattern is a fin portion; or, the material layer to be patterned is a gate material layer, and the target pattern is a gate layer; or, the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
Accordingly, an embodiment of the present invention provides a semiconductor structure, including: the patterning device comprises a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern; a core layer on the mask material layer; the mask side wall is positioned on the side wall of the core layer and exposes partial side walls on any side of the core layer; the core layer and the mask side wall are used as a mask for patterning the mask material layer.
Optionally, the substrate includes a first region and a second region, and a width of a target pattern formed in the first region is smaller than a width of the target pattern formed in the second region; the core layer is positioned on the mask material layer of the second area; the mask side wall is also positioned on the mask material layer of the first area.
Optionally, the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polycrystalline silicon, an ODL material, a DARC material or a BARC material, and the material of the mask sidewall is silicon oxide or silicon nitride, wherein the material of the mask material layer is different from the material of the mask sidewall.
Optionally, the material layer to be patterned is a fin portion material layer, and the target pattern is a fin portion; or, the material layer to be patterned is a gate material layer, and the target pattern is a gate layer; or, the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the scheme disclosed by the embodiment of the invention, a core layer is formed on a mask material layer, after mask side walls are formed on the side walls of the core layer, partial etching treatment is carried out on partial mask side walls, partial mask side walls of any side wall of the core layer are removed, partial side walls of the core layer are exposed, so that the mask material layer is patterned by taking the remaining core layer and the mask side walls as masks, the mask material layer is formed, and then the material layer to be patterned is patterned by taking the mask layer as a mask to form a target pattern; the mask side wall on the side wall of the core layer part is removed in an etching mode, so that the appearance quality of the mask side wall and the appearance quality of the corner of the core layer are good, the quality of a target graph is improved, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
At present, the performance of semiconductor structures is still to be improved.
The performance of a semiconductor structure is desired to be improved in combination with a method of forming the semiconductor structure. Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, which includes a substrate (not shown) and a fin portion 10 protruding from the substrate, a gate oxide layer 20, a gate material layer 30 covering the gate oxide layer 20, and a mask material layer 40 covering the gate material layer 30 are formed on the substrate 10, and the substrate includes a first region 10a and a second region 10 b.
The masking material layer 40 is used to form a gate layer, and a width of the gate layer formed in the first region 10a is smaller than a width of the gate layer formed in the second region 10 b.
With continued reference to fig. 1, a core layer 50 is formed on the masking material layer 40 in the first region 10 a.
Referring to fig. 2, mask spacers 60 are formed on sidewalls of the core layer 50.
Referring to fig. 3, after forming the mask sidewall spacer 60, the core layer 50 is removed.
Referring to fig. 4, after removing the core layer 50, a photoresist layer 70 is formed on the mask material layer 40 of the second region 10 b.
Referring to fig. 5, the mask material layer 40 is etched to form a mask layer 45 by using the mask sidewall spacers 60 (shown in fig. 4) and the photoresist layer 70 (shown in fig. 4) as masks; after the mask layer 45 is formed, the mask side wall 60 and the photoresist layer 70 are removed; and after removing the mask side walls 60 and the photoresist layer 70, etching the gate material layer 30 by taking the mask layer 45 as a mask to form a gate layer 35.
As shown in fig. 6, fig. 6 is a top view of the semiconductor structure formed by the above method, and only the fin 10 and the gate layer 35 are shown for convenience of illustration.
The gate layer 35 formed in the second region 10b includes a gate layer wide section 32 and a gate layer narrow section 31 in an extending direction thereof, and the width of the gate layer wide section 32 is greater than that of the gate layer narrow section 31.
Accordingly, in the step of forming the photoresist layer 70 on the masking material layer 40 in the second region 10b, the topography of the photoresist layer 70 matches the topography of the gate layer 35 formed in the second region 10 b. However, the photoresist layer 70 is formed by a photolithography process, and due to the limitation of the photolithography process, a corner of the pattern is easily rounded, so that after the gate layer 35 is formed, the gate layer 35 of the second region 10b also has a corner (as shown by a dashed circle in fig. 6), thereby easily causing a performance degradation of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern; forming a core layer on the mask material layer; forming a mask side wall on the side wall of the core layer; etching part of the mask side wall to remove part of the mask side wall on any side wall of the core layer and expose part of the side wall of the core layer; etching part of the mask side wall, and then patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer; and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern.
In the scheme disclosed by the embodiment of the invention, the mask side wall on the partial side wall of the core layer is removed in an etching mode, so that the appearance quality of the mask side wall and the corner of the core layer is better, which is beneficial to improving the quality of a target pattern, thereby improving the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 7 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, a substrate 100 is provided, a material layer 120 to be patterned and a mask material layer 140 covering the material layer 120 to be patterned are formed on the substrate 100, and the material layer 120 to be patterned is used for forming a target pattern.
In this embodiment, taking the formation method for forming a fin field effect transistor as an example, the base includes a substrate and a fin portion protruding from the substrate. In other embodiments, the base is a substrate.
Specifically, the substrate 100 includes a first region 100a and a second region 100b, and a width of a target pattern formed in the first region 100a is smaller than a width of the target pattern formed in the second region 100 b. In other embodiments, the substrate may also be used to form target patterns of the same width.
In this embodiment, the material layer to be patterned 120 is a gate material layer, and the material layer to be patterned 120 is used for preparing a gate layer. That is, the target pattern is a gate layer.
As an example, the material of the material layer to be patterned 120 is polysilicon.
Therefore, a gate oxide layer 110 is also formed between the substrate 100 and the material layer 120 to be patterned. As an example, the material of the gate oxide layer 110 is silicon oxide.
The masking material layer 140 is used to prepare a subsequent patterned masking layer. Wherein the hard mask layer is used as a mask for subsequently patterning the material layer to be patterned 120.
In this embodiment, the material of the mask material layer 140 is silicon nitride. In other embodiments, the material of the masking material layer may also be silicon oxide. In other embodiments, the material of the mask material layer may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
For this reason, in this embodiment, a buffer layer 130 is further formed between the mask material layer 140 and the material layer to be patterned 120.
The lattice constant of the material of the buffer layer 130 is between the lattice constant of the material of the mask material layer 140 and the lattice constant of the material layer 120 to be patterned, thereby reducing the stress of the material of the mask material layer 140 and the material layer 120 to be patterned. In this embodiment, the buffer layer 130 is made of silicon oxide.
In other embodiments, the material layer to be patterned is a fin material layer, and the target pattern is a fin. In this case, the base is a substrate, and the base and the material layer to be patterned are an integral structure, or the material layer to be patterned is epitaxially grown on the base.
In other embodiments, the forming method may also be applied to back end of line (BEOL) processes, the material layer to be patterned is an inter-metal dielectric layer, and the formed target pattern is an interconnect opening formed in the inter-metal dielectric layer.
With continued reference to fig. 7, a core layer 200 is formed on the masking material layer 140.
The core layer 200 is used to provide a process foundation for the subsequent formation of the mask sidewall.
It should be noted that the core layer 200 is also removed subsequently, so the material etching selectivity of the core layer 200 and the mask material layer 140 is greater than 50:1, and the material of the core layer 200 is a material that is easy to be removed, thereby reducing the damage to the mask material layer 140 caused by the subsequent process of removing the core layer 200.
For this purpose, in this embodiment, the material of the core layer 200 may be amorphous silicon. In other embodiments, the material of the core layer may also be amorphous germanium.
In this embodiment, the core layer 200 is formed on the mask material layer 140 of the first region 100a and the second region 100 b.
In this embodiment, the width of the target pattern formed in the first region 100a is smaller than the width of the target pattern formed in the second region 100b, so that the core layer 200 is formed in the first region 100a to form the target pattern in the first region 100a by the SADP process.
Accordingly, the core layer 200 width w1 of the first region 100a is less than the core layer 200 width w2 of the second region 100 b. The extending direction of the core layer 200 is a first direction (not shown), and the direction parallel to the surface of the substrate 100 and perpendicular to the first direction is a second direction (not shown), where the width refers to the dimension of the core layer 200 in the second direction.
In this embodiment, the core layer 200 is formed, so that target patterns with different widths and sizes are formed by the same process, and the process compatibility is higher, which is beneficial to reducing the process complexity.
Referring to fig. 8, mask spacers 210 are formed on sidewalls of the core layer 200.
The mask sidewall spacers 210 are used as a mask for subsequent patterning of the mask material layer 140.
Specifically, the step of forming the mask sidewall spacers 210 includes: forming a side wall material layer conformally covering the core layer 200 and the mask material layer 140; the side wall material layers on the top of the core layer 200 and the mask material layer 140 are removed, and the side wall material layers on the side walls of the core layer 200 are reserved as the mask side walls 210.
In this embodiment, in order to improve the thickness uniformity of the side wall material layer, and thus improve the width uniformity of the mask side wall 210 in the second direction, an atomic layer deposition process is used to form the side wall material layer; and the control difficulty of the thickness of the side wall material layer is favorably reduced by adopting the atomic layer deposition process. In other embodiments, the sidewall material layer may also be formed by a chemical vapor deposition process.
In this embodiment, an anisotropic maskless dry etching (blanket dry etch) process is adopted to selectively etch the sidewall material layer along the normal direction of the surface of the substrate 100, so as to retain the sidewall material layer on the sidewall of the core layer 200, thereby forming the mask sidewall 210.
It should be noted that the core layer 200 of the first region 100a is also removed subsequently, and therefore, in order to reduce the loss of the process for removing the core layer 200 to the mask sidewall spacer 210, the etching selectivity ratio of the core layer 200 to the mask sidewall spacer 210 is greater than 10: 1.
Moreover, etching treatment is further performed on part of the mask side wall 210, so that when the mask side wall 210 is etched, the etching selection ratio of the mask side wall 210 to the mask material layer 140 is greater than 10:1, and thus, the damage of the process for etching the mask side wall 210 to the mask material layer 140 is reduced.
In this embodiment, the mask sidewall 210 is made of silicon oxide. In other embodiments, the material of the mask sidewall may also be silicon nitride. In other embodiments, the material of the mask sidewall may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. The material of the mask material layer 140 is different from that of the mask sidewall 210.
In this embodiment, the width of the mask sidewall spacers 210 along the second direction is determined according to the width of a target pattern subsequently formed in the first region 100 a.
Referring to fig. 9 in combination, after forming the mask sidewall spacer 210 on the sidewall of the core layer 200, the forming method further includes: the core layer 200 of the first region 100a is removed.
In this embodiment, in order to increase the removal rate of the core layer 200, a dry etching process is used to remove the core layer 200 in the first region 100 a.
Specifically, the step of removing the core layer 200 of the first region 100a includes: forming a first shielding layer 300 on the mask material layer 140 of the second region 100b, wherein the first shielding layer 300 covers the core layer 200 and the mask sidewall 219; the core layer 200 of the first region 100a is removed using the first shielding layer 300 as a mask.
In this embodiment, the first shielding layer 300 is made of photoresist. By selecting the photoresist, the first shielding layer 300 can be formed at a predetermined position by directly patterning the photoresist using a photolithography process, which is simple. In other embodiments, the first shielding layer may also be a stacked structure, for example: including a bottom anti-reflective coating (BARC) and a photoresist layer overlying the BARC.
In this embodiment, when the core layer 200 of the first region 100a is removed, the core layer 200 of the second region 100b is retained, so that the core layer 200 of the second region 100b can be used as a mask for patterning the mask material layer 140 in a subsequent process, thereby forming a target pattern with a larger width in the second region 100 b.
Referring to fig. 10 and 11 together, fig. 10 is a top view, and fig. 11 is a cross-sectional view taken along line A1a2 of fig. 10, after removing the core layer 200 of the first region 100a, the first barrier layer 300 is removed.
The first masking layer 300 is removed to prepare for the subsequent etching process of the mask sidewall 210 of the second region 100 b.
In this embodiment, the first masking layer 300 is made of photoresist, and therefore, an ashing process is used to remove the first masking layer 300.
Referring to fig. 12 and 13 in combination, fig. 12 is a top view, and fig. 13 is a cross-sectional view taken along line A1a2 of fig. 12, and an etching process is performed on a portion of the mask sidewall 210 to remove a portion of the mask sidewall 210 on either side of the core layer 200, exposing a portion of the sidewall of the core layer 200.
Here, for convenience of illustration, fig. 12 only illustrates the core layer 200 and the mask sidewall spacers 210.
In this embodiment, in the step of performing the etching process on the part of the mask sidewall 210, the etching process is performed on the part of the mask sidewall 210 of the second region 100 b.
By performing the etching process on part of the mask sidewall 210 of the second region 100b, the topography of the target pattern subsequently formed in the second region 100b can meet the design requirement.
Specifically, the step of performing the etching process on the partial mask sidewall 210 includes: forming a second shielding layer (not shown) on the mask material layer 140, wherein the second shielding layer covers the top of the core layer 200 and the mask side wall 210, and the second shielding layer exposes the mask side wall 210 to be etched on the side wall of the core layer 200; and removing the exposed mask sidewall 210 by using the second shielding layer as a mask.
In this embodiment, the second shielding layer is made of photoresist. By selecting the photoresist, the second shielding layer can be formed at a preset position by directly utilizing a photoetching process for patterning, and the process is simple. In other embodiments, the second shielding layer may also be a stacked structure, for example: comprising a bottom anti-reflective coating and a photoresist layer covering the bottom anti-reflective coating.
In this embodiment, an anisotropic dry etching process is used to etch the mask sidewall 210 exposed by the second shielding layer. The anisotropic dry etching process has anisotropic etching characteristics, so that a straight etching profile can be obtained, and the appearance quality of a subsequently formed target pattern at a corner is improved.
In this embodiment, during the etching process of the partial mask sidewalls 210 of the second region 100b, one or more mask sidewalls 210 of the first region 100a are also cut in the extending direction (i.e., the first direction) of the mask sidewalls 210.
By performing the cutting process on one or more mask sidewalls 210 of the first region 100a, the layout of the target pattern of the first region 100a meets the design requirement.
Correspondingly, in the step of forming the second shielding layer, the mask sidewall 210 to be etched in the first region 100a is also exposed by the second shielding layer.
In this embodiment, in the same step, the etching process is performed on the second region 100b and a part of the mask sidewall 210 of the first region 100a, so that the same photomask can be used without increasing the process cost.
In other embodiments, the mask sidewall of the first region may not be etched according to the process requirement.
In this embodiment, after removing the exposed mask sidewall spacers 210, the method further includes: and removing the second shielding layer.
Specifically, the second shielding layer is made of photoresist, and thus, the first shielding layer 300 is removed by an ashing process.
In this embodiment, after the core layer 200 in the first region 100a is removed, the etching process is performed on a portion of the mask sidewall spacers 210. In other embodiments, the core layer in the first region may also be removed after etching a portion of the mask sidewall spacers 210, as long as the core layer in the first region is removed before patterning the mask material layer.
Referring to fig. 14 and 15 in combination, fig. 14 is a top view, fig. 15 is a cross-sectional view of fig. 14 along a cut line A1a2, after etching a portion of the mask sidewall spacer 210, patterning the mask material layer 140 by using the remaining core layer 200 and the mask sidewall spacer 210 as a mask to form a mask layer 145; and patterning the material layer to be patterned 120 by taking the mask layer 145 as a mask to form a target pattern 125.
Fig. 14 shows only the target figure 125 for convenience of illustration.
In this embodiment, the remaining core layer 200 and the mask sidewall 210 are used as the mask patterning mask material layer 140, and the patterns corresponding to the core layer 200 and the mask sidewall 210 are transferred to the mask material layer 140 to form the mask layer 145, so that the patterns are further transferred to the material layer to be patterned 120 through the mask layer 145 to form the target pattern 125.
In this embodiment, after the mask layer 145 is formed, the core layer 200 and the mask sidewall spacers 210 are removed.
Specifically, in order to remove the core layer 200 and the mask side wall 210 cleanly, a wet etching process is adopted to remove the core layer 200 and the mask side wall 210.
In this embodiment, the material layer 120 to be patterned is patterned by using an anisotropic dry etching process, so as to improve the topography quality of the target pattern 125.
In this embodiment, the material layer to be patterned 120 is a gate material layer, and thus the target pattern 125 is a gate layer.
In the present embodiment, in the second region 100b, the target pattern 125 includes, in the extending direction thereof, a target pattern wide section 125a and a target pattern narrow section 125b, and the width of the target pattern wide section 125a is larger than the width of the target pattern narrow section 125 b.
The target pattern wide section 125a is formed by the core layer 200 (as shown in fig. 12) and the mask side walls 210 (as shown in fig. 12) located at two sides of the core layer 200, and the target pattern narrow section 125b is formed by the core layer 200 and the mask side walls 210 located at one side of the core layer 200, so that the topography quality at the corner of the target pattern wide section 125a and the target pattern narrow section 125b is better, the probability of forming a fillet at the corner is lower, and the performance of the semiconductor structure is improved.
It should be noted that a buffer layer 130 is further formed between the mask material layer 140 and the material layer to be patterned 120, and therefore, before etching the material layer to be patterned 120, the buffer layer 130 is further etched.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 12 and 13 in combination, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. Fig. 12 is a top view, fig. 13 is a cross-sectional view taken along a line A1a2 in fig. 12, and fig. 12 only shows the core layer 200 and the mask sidewall 210 for convenience of illustration.
The semiconductor structure includes: a substrate 100, wherein a material layer 120 to be patterned and a mask material layer 140 covering the material layer 120 to be patterned are formed on the substrate 100, and the material layer 120 to be patterned is used for forming a target pattern; a core layer 200 on the mask material layer 140; the mask side wall 210 is positioned on the side wall of the core layer 200, and the mask side wall 210 exposes partial side walls on any side of the core layer 200; the core layer 200 and the mask sidewall spacers 210 are used as a mask for patterning the mask material layer 140.
The substrate is used for providing a process foundation for forming a target pattern. In this embodiment, taking the semiconductor structure as a fin field effect transistor as an example, the substrate includes a substrate and a fin portion protruding from the substrate. In other embodiments, the base is a substrate.
Specifically, the substrate 100 includes a first region 100a and a second region 100b, and a width of a target pattern formed in the first region 100a is smaller than a width of the target pattern formed in the second region 100 b. In other embodiments, the substrate may also be used to form target patterns of the same width.
In this embodiment, the material layer to be patterned 120 is a gate material layer, and the material layer to be patterned 120 is used for preparing a gate layer. That is, the target pattern is a gate layer.
As an example, the material of the material layer to be patterned 120 is polysilicon.
Therefore, a gate oxide layer 110 is also formed between the substrate 100 and the material layer 120 to be patterned. As an example, the material of the gate oxide layer 110 is silicon oxide.
The masking material layer 140 is used to prepare a subsequent patterned masking layer. Wherein the hard mask layer is used as a mask for subsequently patterning the material layer to be patterned 120.
In this embodiment, the material of the mask material layer 140 is silicon nitride. In other embodiments, the material of the masking material layer may also be silicon oxide. In other embodiments, the material of the mask material layer may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride.
For this reason, in this embodiment, a buffer layer 130 is further formed between the mask material layer 140 and the material layer to be patterned 120.
The buffer layer 130 has a lattice constant between the mask material layer 140 and the material layer 120 to be patterned, thereby reducing stress of the mask material layer 140 and the material layer 120 to be patterned. In this embodiment, the buffer layer 130 is made of silicon oxide.
In other embodiments, the material layer to be patterned is a fin material layer, and the target pattern is a fin. In this case, the base is a substrate, and the base and the material layer to be patterned are an integral structure, or the material layer to be patterned is epitaxially grown on the base.
In other embodiments, the forming method may also be applied to back end of line (BEOL) processes, the material layer to be patterned is an inter-metal dielectric layer, and the formed target pattern is an interconnect opening formed in the inter-metal dielectric layer.
The core layer 200 is used to provide a process foundation for forming the mask sidewall spacers 210. In the second region 100b, the core layer 200 and the mask sidewall spacers 210 on the sidewalls thereof collectively serve as a mask when patterning the mask material layer 140.
It should be noted that the core layer 200 is also removed subsequently, so the material etching selectivity of the core layer 200 to the mask material layer 140 is greater than 50:1, and the material of the core layer 200 is a material that is easy to be removed, thereby reducing the damage to the mask material layer 140 caused by the subsequent process of removing the core layer 200.
For this purpose, in this embodiment, the material of the core layer 200 may be amorphous silicon. In other embodiments, the material of the core layer may also be amorphous germanium.
In this embodiment, the core layer 200 is only located on the mask material layer 140 of the second region 100 b.
In this embodiment, the mask sidewall spacers 210 are located on the sidewalls of the core layer 200, and the mask sidewall spacers 210 expose partial sidewalls of any side of the core layer 200.
By exposing the mask side wall 210 to partial side walls on either side of the core layer 200, and after transferring the pattern formed by the core layer 200 and the mask side wall 210 to the material layer to be patterned 120 of the second region 100b, the formed target pattern can include a target pattern wide section and a target pattern narrow section in the extending direction thereof, and the width of the target pattern wide section is greater than that of the target pattern narrow section, so as to meet the design requirement.
In this embodiment, the mask sidewall spacers 210 are further located on the mask material layer 140 of the first region 100a, and the first region 100a is used as a mask for patterning the mask material layer 140 of the first region 100a subsequently.
The mask sidewall spacer 210 of the first region 100a is formed by using an SADP process, in the process of forming the semiconductor structure, the core layer 200 is further formed on the mask material layer 140 of the first region 100a, the mask sidewall spacer 210 is formed on the sidewall of the core layer 200, and after the mask sidewall spacer 210 is formed, the core layer 200 of the first region 100a is removed.
Therefore, in order to reduce the loss of the mask sidewall 210 due to the process of removing the core layer 200, the etching selectivity ratio of the core layer 200 to the mask sidewall 210 is greater than 10: 1. Moreover, when etching part of the mask sidewall 210, the etching selection ratio of the mask sidewall 210 to the mask material layer 140 is greater than 10:1, so that the damage of the process for etching the mask sidewall 210 to the mask material layer 140 is reduced.
In this embodiment, the mask sidewall 210 is made of silicon oxide. In other embodiments, the material of the mask sidewall may also be silicon nitride. In other embodiments, the material of the mask sidewall may also be silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. The material of the mask material layer 140 is different from that of the mask sidewall 210.
In this embodiment, the width of the mask sidewall spacers 210 along the second direction is determined according to the width of the target pattern formed in the first region 100 a.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing first embodiment, which is not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern;
forming a core layer on the mask material layer;
forming a mask side wall on the side wall of the core layer;
etching part of the mask side wall to remove part of the mask side wall on any side wall of the core layer and expose part of the side wall of the core layer;
etching part of the mask side wall, and then patterning the mask material layer by taking the residual core layer and the mask side wall as masks to form a mask layer;
and patterning the material layer to be patterned by taking the mask layer as a mask to form a target pattern.
2. The method of claim 1, wherein the step of providing the substrate comprises a first region and a second region, wherein a width of a target pattern formed in the first region is smaller than a width of a target pattern formed in the second region;
forming a core layer on the mask material layer, the core layer being located on the mask material layer of the first region and the second region;
in the step of etching part of the mask side wall, etching part of the mask side wall in the second region;
before patterning the mask material layer by using the remaining core layer and the mask side wall as masks, the forming method further includes: removing the core layer of the first region.
3. The method for forming a semiconductor structure according to claim 2, wherein after the mask sidewall is formed, the core layer in the first region is removed before etching a part of the mask sidewall;
or, after etching treatment is carried out on part of the mask side wall, the core layer in the first region is removed.
4. The method of forming a semiconductor structure of claim 2, wherein the step of removing the core layer of the first region comprises: forming a first shielding layer on the mask material layer of the second region, wherein the first shielding layer covers the core layer and the mask side wall;
removing the core layer in the first region by taking the first shielding layer as a mask;
and removing the first shielding layer after removing the core layer of the first area.
5. The method for forming a semiconductor structure according to any one of claims 1 to 3, wherein the step of performing an etching process on a portion of the mask sidewall spacers comprises: forming a second shielding layer on the mask material layer, wherein the second shielding layer covers the top of the core layer and the top of the mask side wall, and the second shielding layer exposes the mask side wall to be etched on the core layer side wall;
taking the second shielding layer as a mask, and removing the exposed mask side wall;
and removing the second shielding layer after the exposed mask side wall is removed.
6. The method for forming the semiconductor structure according to claim 2, wherein during the etching process of the mask sidewall spacers in the second region, the mask sidewall spacer in the first region is further subjected to a cutting process in an extending direction of the mask sidewall spacer.
7. The method for forming a semiconductor structure according to any one of claims 1 to 3, wherein an anisotropic dry etching process is used to etch a portion of the mask sidewall.
8. The method of claim 1, wherein the step of forming mask spacers on the sidewalls of the core layer comprises: forming a side wall material layer which conformally covers the core layer and the mask material layer;
and removing the side wall material layers on the top of the core layer and the mask material layer, and reserving the side wall material layers on the side walls of the core layer as mask side walls.
9. The method of claim 2, wherein in the step of forming a core layer on the mask material layer, the core layer width of the first region is smaller than the core layer width of the second region.
10. The method according to claim 1, wherein the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polysilicon, ODL material, DARC material or BARC material, and the material of the mask sidewall spacer is silicon oxide or silicon nitride, wherein the material of the mask material layer is different from the material of the mask sidewall spacer.
11. The method for forming a semiconductor structure according to claim 4, wherein a material of the first shielding layer comprises a photoresist.
12. The method for forming a semiconductor structure according to claim 5, wherein a material of the second shielding layer comprises a photoresist.
13. The method of claim 1, wherein the material layer to be patterned is a fin material layer, and the target pattern is a fin;
or, the material layer to be patterned is a gate material layer, and the target pattern is a gate layer;
or, the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
14. A semiconductor structure, comprising:
the patterning device comprises a substrate, wherein a material layer to be patterned and a mask material layer covering the material layer to be patterned are formed on the substrate, and the material layer to be patterned is used for forming a target pattern;
a core layer on the mask material layer;
the mask side wall is positioned on the side wall of the core layer and exposes partial side walls on any side of the core layer;
the core layer and the mask side wall are used as a mask for patterning the mask material layer.
15. The semiconductor structure of claim 14, wherein the substrate comprises a first region and a second region, and wherein a target pattern width formed in the first region is smaller than a target pattern width formed in the second region;
the core layer is positioned on the mask material layer of the second area;
the mask side wall is also positioned on the mask material layer of the first area.
16. The semiconductor structure of claim 14, wherein the material of the mask material layer is silicon nitride or silicon oxide, the material of the core layer is amorphous silicon, amorphous germanium, polysilicon, ODL material, DARC material or BARC material, and the material of the mask sidewall is silicon oxide or silicon nitride, wherein the material of the mask material layer and the material of the mask sidewall are different.
17. The semiconductor structure of claim 14, wherein the material layer to be patterned is a fin material layer, and the target pattern is a fin;
or, the material layer to be patterned is a gate material layer, and the target pattern is a gate layer;
or, the material layer to be patterned is an inter-metal dielectric layer, and the target pattern is an interconnection opening formed in the inter-metal dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911259681.2A CN112951724A (en) | 2019-12-10 | 2019-12-10 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911259681.2A CN112951724A (en) | 2019-12-10 | 2019-12-10 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112951724A true CN112951724A (en) | 2021-06-11 |
Family
ID=76225655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911259681.2A Pending CN112951724A (en) | 2019-12-10 | 2019-12-10 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112951724A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130234301A1 (en) * | 2012-03-11 | 2013-09-12 | Chih-Jung Wang | Patterned structure of semiconductor device and fabricating method thereof |
| US20180076034A1 (en) * | 2016-09-09 | 2018-03-15 | International Business Machines Corporation | Multi-angled deposition and masking for custom spacer trim and selected spacer removal |
| CN109786226A (en) * | 2017-11-15 | 2019-05-21 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| US20190206725A1 (en) * | 2018-01-01 | 2019-07-04 | International Business Machines Corporation | Multi-patterning techniques for fabricating an array of metal lines with different widths |
-
2019
- 2019-12-10 CN CN201911259681.2A patent/CN112951724A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130234301A1 (en) * | 2012-03-11 | 2013-09-12 | Chih-Jung Wang | Patterned structure of semiconductor device and fabricating method thereof |
| US20180076034A1 (en) * | 2016-09-09 | 2018-03-15 | International Business Machines Corporation | Multi-angled deposition and masking for custom spacer trim and selected spacer removal |
| CN109786226A (en) * | 2017-11-15 | 2019-05-21 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| US20190206725A1 (en) * | 2018-01-01 | 2019-07-04 | International Business Machines Corporation | Multi-patterning techniques for fabricating an array of metal lines with different widths |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110739210B (en) | Semiconductor structure and forming method thereof | |
| TWI356446B (en) | Methods to reduce the critical dimension of semico | |
| CN111370299B (en) | Semiconductor structure and forming method thereof | |
| TW201839852A (en) | Method of forming semiconductor device | |
| TW202018764A (en) | Methods for forming integrated circuit structure | |
| WO2022095419A1 (en) | Semiconductor device preparation method | |
| CN108447820B (en) | Apparatus for multiple patterning with non-chamfered vias and method of forming non-chamfered vias | |
| EP3618103A1 (en) | A patterning method | |
| CN111199880B (en) | Manufacturing method of semiconductor device and semiconductor device | |
| CN109559978B (en) | Semiconductor structure and forming method thereof | |
| CN114334619A (en) | Method for forming semiconductor structure | |
| US11037788B2 (en) | Integration of device regions | |
| CN110690117B (en) | Semiconductor structure and forming method thereof | |
| CN111640659B (en) | Semiconductor device and method of forming the same | |
| US20220130672A1 (en) | Semiconductor structure formation method and mask | |
| KR20070113604A (en) | Method for forming micro pattern of semiconductor device | |
| CN111009461B (en) | Method for manufacturing semiconductor device | |
| CN112951724A (en) | Semiconductor structure and forming method thereof | |
| CN111640666B (en) | Semiconductor device and method of forming the same | |
| CN114639604A (en) | Method for forming semiconductor structure | |
| CN114388352A (en) | Semiconductor structure and forming method thereof | |
| CN112018034A (en) | Semiconductor structure and forming method thereof | |
| CN112908836B (en) | Semiconductor structure and forming method thereof | |
| CN113327843B (en) | Method for forming semiconductor structure | |
| CN111489960B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |