CN109559978B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN109559978B
CN109559978B CN201710889671.1A CN201710889671A CN109559978B CN 109559978 B CN109559978 B CN 109559978B CN 201710889671 A CN201710889671 A CN 201710889671A CN 109559978 B CN109559978 B CN 109559978B
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forming
initial
layers
area
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CN109559978A (en
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陈卓凡
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

The invention provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: forming an initial functional layer on the first area and the second area substrate; forming an initial mask layer on the initial functional layer; forming a plurality of discrete first graphic layers on the first area initial mask layer, and forming second graphic layers on the removal area initial mask layer and the retention area initial mask layer respectively, wherein the size of the first graphic layers along the first direction is a first size, the size of the second graphic layers along the first direction is a second size, the second size is equal to the first size, and the distance between every two adjacent first graphic layers is equal to the distance between every two adjacent second graphic layers; and carrying out pattern transfer treatment to form a plurality of mask layers. The forming method can improve the performance of the formed semiconductor structure and simplify the process flow.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are developed toward high density and high integration. In order to reduce the size of the semiconductor device and improve the integration of the semiconductor device, multiple patterning processes, including a double patterning process, a triple patterning process, and a quadruple patterning process, have been developed in the prior art.
The double patterning process can effectively reduce the difficulty of manufacturing small-size patterns and has important application in forming small-size patterns. The double patterning process includes a self-aligned double exposure (SADP) technique, a Double Etch Double Patterning (DEDP) technique, and a single etch double patterning technique.
With the improvement of the integration level of semiconductor devices, when the density of patterns in different areas on the same chip is different, the performance of a semiconductor structure formed by a double patterning process is poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the formed semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area, the second area comprises a removal area and a retention area which are mutually separated and alternately arranged, and the arrangement direction of the removal area and the retention area is a first direction; forming an initial functional layer on the first area and the second area substrate; forming an initial mask layer on the initial functional layer; forming a plurality of discrete first graphic layers on the first area initial mask layer, and forming second graphic layers on the removal area initial mask layer and the retention area initial mask layer respectively, wherein the size of the first graphic layers along the first direction is a first size, the size of the second graphic layers along the first direction is a second size, the second size is equal to the first size, and the distance between every two adjacent first graphic layers is equal to the distance between every two adjacent second graphic layers; forming a widening layer covering the side wall of the second graphic layer of the reserved area; etching the initial mask layer by taking the widening layer, the first graph layer and the second graph layer as masks to form a mask layer; etching the initial functional layer by taking the mask layer as a mask to form a functional layer; and removing the functional layer in the removal area.
Optionally, the step of forming the first graphic layer and the second graphic layer includes: respectively forming a plurality of discrete core layers on the first region initial mask layer and the second region initial mask layer, wherein the distance between the core layers of the adjacent first regions is equal to the distance between the core layers of the adjacent second regions, the dimension of the core layers of the first regions along the first direction is a third dimension, the dimension of the core layers of the second regions along the first direction is a fourth dimension, and the third dimension is equal to the fourth dimension; forming an initial pattern layer on the top and the side wall of the core layer and the initial mask layer; carrying out anisotropic etching on the initial pattern layer, removing the initial mask layer and the initial pattern layer on the top of the core layer, forming a plurality of discrete first pattern layers in the first area, and forming a second pattern layer in the removal area and the reserved area; after the anisotropic etching, the core layer is removed.
Optionally, before forming the core layer, the method further includes: forming a stop layer on the initial mask layer, wherein the material of the stop layer is different from that of the core layer; after the mask layer is formed, the method further comprises the following steps: and removing the stop layer on the mask layer.
Optionally, the step of forming the widening layer includes: forming a first flat layer on the initial mask layer, the first graphic layer and the second graphic layer, wherein the surface of the first flat layer is higher than the tops of the first graphic layer and the second graphic layer; forming a first patterned photoresist on the first flat layer, wherein the first patterned photoresist completely covers the top of the second pattern layer of the reserved area, and the size of the first photoresist is larger than that of the second pattern layer of the reserved area along the first direction; and etching the first flat layer by taking the first photoresist as a mask to form the widening layer.
Optionally, the material of the first planarization layer is an organic dielectric material.
Optionally, the step of forming the widening layer includes: forming an initial widening layer covering the side walls of the first graphic layer and the second graphic layer, wherein the initial widening layer is made of a photoresist material; and carrying out exposure treatment on the initial widening layer, and removing the initial widening layer of the first area to form a widening layer.
Optionally, before removing the removal area functional layer, the method further includes: and forming a protective layer on the first area substrate and the second area substrate, wherein the protective layer covers the side wall of the functional layer and exposes the top of the functional layer in the removal area.
Optionally, the step of forming the protective layer includes: forming an initial protective layer on the first area substrate and the second area substrate, wherein the initial protective layer covers the side wall and the top of the functional layer; and carrying out first flattening treatment on the initial protective layer, and removing the initial protective layer on the functional layer to form a protective layer.
Optionally, after removing the removal area functional layer, the method further includes: and removing the protective layer.
Optionally, after removing the protective layer, the method further includes: forming an initial dielectric layer on the substrate, wherein the initial dielectric layer covers the side wall and the top of the functional layer; performing second planarization treatment on the initial dielectric layer, and removing the initial dielectric layer on the top of the functional layer to form a dielectric layer; removing the functional layer and forming a first opening in the dielectric layer; and forming a gate structure in the first opening.
Optionally, the initial protection layer is made of silicon oxide or titanium oxide; the process of forming the initial protective layer includes a fluid chemical vapor deposition process.
Optionally, after removing the removal region functional layer, forming a trench in the protective layer; the forming method further includes: an isolation layer is formed in the trench.
Optionally, the first area includes a functional area and a blank area; the forming method further includes: removing the functional layer in the blank area; and removing the blank area functional layer and the removal area functional layer by the same process.
Optionally, a first side wall is arranged between the adjacent first pattern layers, the first side wall is in contact with the adjacent first pattern layers, and the first side wall and the adjacent first pattern layers form an annular structure; a second side wall is arranged between the adjacent second graphic layers, the second side wall is in contact with the adjacent second graphic layers, and the second side wall and the adjacent second graphic layers form an annular structure; the step of etching the initial mask layer further takes the first side wall and the second side wall as masks, respectively forms a first connecting layer in the first area, and forms a second connecting layer in the second area, wherein two ends of the first connecting layer are respectively contacted with the adjacent first pattern layers, and two ends of the second connecting layer are respectively contacted with the adjacent second pattern layers; before etching the initial functional layer, the method further comprises: and removing the first connecting layer and the second connecting layer.
Optionally, the mask layer is in a long strip shape, and a direction perpendicular to the extending direction of the mask layer is a second direction; before forming the functional layer, the method further comprises the following steps: carrying out patterning processing on the mask layer, and forming a second opening in the mask layer, wherein the second opening penetrates through the mask layer in a second direction, and the second direction is perpendicular to the extending direction of the mask layer; removing the first and second connection layers, and the step of patterning includes: and etching the mask layer, the first connecting layer and the second connecting layer, removing the first connecting layer and the second connecting layer, and forming a second opening in the mask layer, wherein the second opening penetrates through the mask layer in the second direction.
Optionally, the number of the functional layers in the removal region is single or multiple.
Optionally, the functional layer is made of polysilicon, poly-germanium, poly-silicon-germanium, aluminum, tungsten, or copper-aluminum.
Optionally, the distance between the centers of the functional layers in the adjacent first areas is 50 nm-60 nm; the distance between the centers of the functional layers in the adjacent second areas is 100 nm-120 nm; the size of the first area functional layer along the first direction is 6 nm-8 nm; the size of the reserved area functional layer along the first direction is 12 nm-16 nm.
Optionally, the process parameters for etching the initial functional layer by using the mask layer as a mask include: the etching gas comprises CF4、CHF3、CH2F2、CH3F、SF6、HBr、Cl2、O2、N2The flow rate of the etching gas is 10sccm to 500sccm, the diluent gas comprises He and Ar, the flow rate of the He is 100sccm to 1000sccm, and the flow rate of the Ar is 100sccm to 1000 sccm; the power of the radio frequency source is 200-2000 watts; the bias voltage drop is 100V-1000V; the etching time is 20 s-60 s.
The technical scheme of the invention provides a semiconductor structure formed by the forming method of the semiconductor structure.
The technical scheme of the invention also provides a semiconductor structure formed by the forming method.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the technical scheme of the invention, the initial mask layer of the first area is provided with a first graphic layer, the initial mask layers of the removal area and the retention area are provided with second graphic layers, the second size is equal to the first size, and the distance between the adjacent first graphic layers is equal to the distance between the adjacent second graphic layers, so that the graphic densities of the first graphic layers and the second graphic layers are the same. And after the initial mask layer is etched by taking the widening layer, the first graph layer and the second graph layer as masks, the formed first area mask layer and the second area mask layer have the same graph density. Therefore, in the process of etching the initial functional layer, the etching rates of the initial functional layers of the first area and the second area are similar, and the substrate of the second area is not easily exposed before the initial functional layer of the first area is exposed out of the substrate, so that when the initial functional layer of the first area is exposed out of the substrate, the substrate of the second area is not easily etched, and the loss of the substrate of the second area can be reduced. And secondly, before the initial mask layer is etched, forming a widening layer covering the side wall of the second pattern layer of the reserved area, wherein the widening layer can ensure that the width of the functional layer of the reserved area meets the design requirement, so that the functional layer of the reserved area has the performance of the design requirement. In addition, the first distance is equal to the second distance, the distance between the adjacent first graph layers is the same as the distance between the adjacent second graph layers, the first graph layers and the second graph layers can be formed through the same process, so that the process flow can be simplified, the process cost can be saved, and the first graph layers and the second graph layers can be formed through the same photomask, so that the process cost can be saved.
Further, since the distance between the core layers of the adjacent first regions is the same as the distance between the core layers of the adjacent second regions, and the distance between the centers of the core layers of the adjacent first regions is equal to the distance between the centers of the core layers of the adjacent second regions, the core layers of the first regions and the second regions can be formed through the same process, which can simplify the process flow. In addition, the first-region core layer and the second-region core layer may be formed using the same mask. Therefore, the forming method can save the photomask and reduce the process cost.
Further, because the distance between the core layers of the first region and the second region is equal, and the width of the core layers of the first region and the second region is equal, the removal rate of the initial pattern layer of the first region and the removal rate of the initial pattern layer of the second region are the same in the process of removing the initial pattern layer on the initial mask layer by etching. Therefore, in the process of removing the initial pattern layer on the initial mask layer, the second region stop layer is not easily damaged, so that the thicknesses of the first region and the second region stop layer can be the same. Because the thicknesses of the stop layers of the first area and the second area are equal, the stop layers of the first area and the second area can be removed simultaneously in the process of removing the stop layers, so that the initial mask layer of the second area is not easy to etch, the loss of the mask layer of the second area can be reduced, the thicknesses of the mask layers of the first area and the second area are equal, and further the subsequent process is not easy to influence. The forming method can improve the performance of the formed semiconductor structure.
Further, before removing the removal region functional layer, a protective layer is formed on the substrate. In the process of removing the removal region functional layers, the protective layer can protect the substrate between the functional layers, so that the loss of the substrate between the functional layers is reduced, and the performance of the formed semiconductor structure can be improved.
Further, the initial protection layer is formed by a fluid chemical vapor deposition process. The initial protective layer formed by the fluid chemical vapor deposition process has good filling performance, and can fully fill gaps between the functional layers, so that the substrate between the functional layers can be fully protected, and the performance of the formed semiconductor structure is improved.
Further, the first area includes a blank area. The blank area and the removal area functional layer are removed through the same process, so that the process flow can be simplified, and the cost is saved.
Drawings
FIGS. 1-6 are schematic structural diagrams illustrating steps of forming a semiconductor structure by a double patterning process;
fig. 7 to 24 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The formation method of the semiconductor structure has many problems, such as: the performance of the formed semiconductor structure is poor.
Now, with the formation method of the semiconductor structure, the reason for the poor performance of the formed semiconductor structure is analyzed:
providing a substrate comprising a first region and a second region; forming a dummy gate layer on the first and second region substrates; forming a plurality of discrete first pattern layers on the dummy gate layer; forming a second pattern layer on the second area dummy gate layer; the distance between the centers of the adjacent second graphic layers is more than or equal to twice the distance between the adjacent first graphic layers; and etching the pseudo gate layer by taking the first graph layer and the second graph layer as masks to form a pseudo gate.
In order to meet design requirements, the distance between the centers of the adjacent second pattern layers is larger than the distance between the centers of the adjacent first pattern layers, so that the depth-to-width ratio of gaps between the second pattern layers is smaller, and the etching rate of the dummy gate layer in the second area is higher in the process of etching the dummy gate layer. When the dummy gate layer in the first region exposes the substrate, the substrate in the second region is exposed, so that when the dummy gate layer in the first region exposes the substrate in the first region, the substrate in the second region is easily etched, which results in large loss of the substrate in the second region, thereby affecting the performance of the formed semiconductor structure.
In order to damage the substrate, the semiconductor technology proposes a method as shown in fig. 1 to 6.
Fig. 1 to 6 are schematic structural diagrams of steps of forming a semiconductor structure through a double patterning process.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region a and a second region B; forming a dummy gate layer 110 on the first and second region a and B substrates 200; forming an initial mask layer 101 on the dummy gate layer 110; forming a stop layer 120 on the initial mask layer 101; forming a plurality of discrete core layers 102 on the first regioa stop layer 120; a sidewall layer 130 is formed on the top and sidewall surfaces of the core layer 102, and the first region a stop layer 120.
Referring to fig. 2, the side wall layer 130 is anisotropically etched to remove the side wall layer 130 on the core layer 102 and the stop layer 120, so as to form a side wall 131; after forming the sidewalls 131, the core layer 102 is removed (as shown in fig. 1).
Referring to fig. 3, after the core layer 102 is removed; forming a first flat layer 132 on the stop layer 120, wherein the first flat layer 132 covers the sidewalls and the top of the sidewalls 131; a patterned first photoresist 143 is formed on the first planarization layer 132 of the second region B.
Referring to fig. 4, the stop layer 120 (shown in fig. 3) is etched by using the first photoresist 143 and the sidewalls 131 (see fig. 3) as masks to form a pattern layer 121; forming a second flat layer 150 on the initial mask layer 101, wherein the second flat layer 150 covers the top and the side wall of the pattern layer 121; forming a patterned second photoresist 141 on the second region B second planarization layer 150; the middle point of the central connecting line of the pattern layer 121 adjacent to the second region B is located on the central line of the second photoresist 141.
Referring to fig. 5, the initial mask layer 101 is etched by using the pattern layer 121 (shown in fig. 4) and the second photoresist 141 (shown in fig. 4) as masks to form a mask layer 104; and etching the dummy gate layer 110 by using the mask layer 104 as a mask to form a dummy gate, where the dummy gate includes a first dummy gate 111 located in the first region a, a second dummy gate 112 located in the second region B, and a third dummy gate 113, and the second dummy gate 112 and the third dummy gate 113 are alternately arranged.
Referring to fig. 6, the third dummy gate 113 is removed (as shown in fig. 5)
In order to meet the design requirement, the distance between the centers of the second dummy gates 112 in the second region B is about 2 times the distance between the centers of the first dummy gates 111 in the first region a, and then the distance between the centers of the first dummy gates 111 is equal to the distance between the centers of the second dummy gates 112 and the third dummy gates 113, so that the distance between the centers of the first region a mask layer 104 (shown in fig. 5) is equal to the distance between the centers of the second region B mask layer 104. In the process of etching the dummy gate layer 110, the pattern density of the first region a and the second region B mask layer 104 is the same. The pattern density of the first-region a and second-region B masking layer 104 has less influence on the difference in etch rate between the first-region a and second-region B dummy gate layer 110 (shown in fig. 4). Therefore, in the process of etching the dummy gate layer 110, the forming method can reduce the loss of the substrate 100 in the second region B caused by the difference of the pattern density of the mask layer 104.
However, since the distance between the centers of the second dummy gates 112 of the second region B is about 2 times the distance between the centers of the first dummy gates 111 of the first region a, and the width between the first dummy gates 111 of the first region a is different from the width of the second dummy gates 112 of the second region B, the distance between the second dummy gates 112 and the third dummy gates 113 is smaller than the distance between the adjacent first dummy gates 111. Since the distance between the second dummy gate 112 and the third dummy gate 113 is small and smaller than the exposure precision, it is difficult to form the first photoresist 143 and the second photoresist 143 by one exposure, and the first photoresist 143 and the second photoresist 141 need to be formed by two exposures, thereby requiring two photomasks, which increases the number of photomasks and increases the growth cost. Secondly, since the widths of the second photoresist 141 and the sidewall 131 are different, and the widths of the first photoresist 143 and the sidewall 131 are different, the sidewall 131, the first photoresist and the second photoresist need to be formed through different processes. In the process of performing anisotropic etching on the sidewall layer 130, since the second region B does not have the core layer 102, during the process of etching the sidewall layer 130, the etching gas is easily in contact with the sidewall layer 130 of the second region B, so that the etching rate of the sidewall layer 130 of the second region B is greater than that of the sidewall layer 130 of the first region a, and thus when the sidewall layer 130 on the first region stop layer 120 is exposed out of the stop layer 120, the stop layer 120 of the second region B is easily etched, so that the thickness of the second region B stop layer 120 is smaller than that of the first region a stop layer 120. In the process of etching the stop layer 120 to form the pattern layer 121, the loss of the second region B initial mask layer 101 is large, so that after the pattern layer 121 is formed, the thickness of the second region B initial mask layer 101 is smaller than that of the first region a initial mask layer 101. In the process of etching the initial mask layer 101 to form the mask layer 104, the loss of the second region B dummy gate layer 100 is large, so that after the mask layer 104 is formed, the thickness of the second region B dummy gate layer 110 is smaller than that of the first region a dummy gate layer 110. Finally, during the process of etching the dummy gate layer 110 to form a dummy gate, the second region B substrate 100 is still easily damaged, thereby resulting in poor performance of the formed semiconductor structure.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a plurality of discrete first graphic layers on the initial mask layer in the first area, and forming second graphic layers on the initial mask layer in the removal area and the reserved area respectively, wherein the arrangement direction of the second graphic layers is the same as the first direction, the size of the first graphic layers along the first direction is a first size, the size of the second graphic layers along the first direction is a second size, the second size is equal to the first size, and the distance between adjacent first graphic layers is equal to the distance between adjacent second graphic layers. The forming method can improve the performance of the formed semiconductor structure and simplify the process flow.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 24 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 7, a substrate 200 is provided, the substrate 200 includes a first region M and a second region N, the second region N includes a removal region N2 and a retention region N1 which are separated from each other and alternately arranged, and an arrangement direction of the removal region N2 and the retention region N1 is a first direction.
In this embodiment, the substrate 200 includes: the device comprises a substrate and a fin part positioned on the substrate. In other embodiments, the substrate may also be a planar substrate, such as a semiconductor substrate, e.g., a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the substrate and the fin portion are made of silicon. In other embodiments, the material of the substrate and the fin portion is germanium or silicon germanium.
In this embodiment, the first region M includes a functional region M1 and a blank region M2.
In this embodiment, the functional area M1 and the blank area M2 are arranged along the first direction. In other embodiments, the arrangement direction of the functional regions and the blank regions may be perpendicular to the first direction, or have an acute angle with the first direction.
In this embodiment, the functional layer of the functional region M1 needs to be reserved, so as to form a dummy gate of the semiconductor device. The functional layer of the blank space M2 needs to be removed later.
In other embodiments, the first area may not include the blank area.
With continued reference to fig. 7, an initial functional layer 210 is formed on the first and second regions M and N of the substrate 200.
In this embodiment, the initial functional layer 210 is used to form a dummy gate in a gate last process, and the material of the initial functional layer 210 is a semiconductor material, such as polysilicon, poly-germanium, or poly-silicon-germanium. In other embodiments, the initial functional layer is used to form metal interconnect lines. The material of the initial functional layer is aluminum, tungsten or copper aluminum.
In this embodiment, the step of forming the initial functional layer 210 includes: chemical vapor deposition process. In other embodiments, the material of the initial functional layer may also be aluminum, tungsten, or copper aluminum, and the process of forming the initial functional layer includes an electroplating process, or an organic metal chemical vapor deposition process, or a physical vapor deposition process.
With continued reference to fig. 7, an initial mask layer 201 is formed on the initial functional layer 210.
The initial mask layer 201 is used for the subsequent formation of a mask layer.
In this embodiment, the initial mask layer 201 is made of silicon nitride. In other embodiments, the material of the initial mask layer may be silicon oxide or silicon oxynitride.
In this embodiment, the forming method further includes: a stop layer 202 is formed on the initial mask layer 201.
The stop layer 202 is used to act as an etch stop during subsequent etching of the initial pattern layer 270.
The stop layer 202 and the initial mask layer 201 are made of different materials, so that the removal rate of the initial mask layer 201 is low in the subsequent process of removing the stop layer 202, the subsequent functional layer is fully protected, and the loss of the functional layer is reduced.
In this embodiment, the material of the stop layer 202 is silicon oxide. In other embodiments, the material of the stop layer may also be silicon nitride or silicon oxynitride.
Subsequently, a plurality of discrete first pattern layers are respectively formed on the first area M initial mask layer 201, and second pattern layers are respectively formed on the removal area N2 and the retention area N1 initial mask layer 201, wherein the size of the first pattern layers along the first direction is a first size, the size of the second pattern layers along the first direction is a second size, the second size is equal to the first size, and the distance between adjacent first pattern layers is the same as the distance between adjacent second pattern layers.
It should be noted that the first area M has a first pattern layer, the removal area N2 and the reserved area N1 have second pattern layers on the mask layer 204, the first size is equal to the second size, and the distance between adjacent first pattern layers is equal to the distance between adjacent second pattern layers, so that the pattern densities of the first pattern layer and the second pattern layer are the same. And after the initial mask layer is etched by taking the widening layer, the first graph layer and the second graph layer as masks, the pattern density of the formed first region M mask layer is the same as that of the second region N mask layer. Therefore, in the process of etching the initial functional layer 210, the etching rates of the initial functional layer 210 of the first region M and the second region N are similar, and before the first region M initial functional layer 210 exposes the substrate 200, the second region N substrate 200 is not easily exposed, so that when the first region M initial functional layer 210 exposes the substrate 200, the second region N substrate 200 is not easily etched, and thus the loss of the second region N substrate 200 can be reduced. Before the initial mask layer 201 is etched, a widening layer covering the side wall of the second pattern layer in the reserved area N1 is formed. The widening layer can ensure that the width of the functional layer of the reserved zone N1 meets the design requirement, so that the functional layer of the subsequent reserved zone N1 has the performance required by the design. In addition, the first graph layer and the second graph layer can be formed through the same process, so that the process flow can be simplified, and the process cost can be saved. Secondly, the first graph layer and the second graph layer can be formed through the same photomask, so that the process cost can be saved.
In this embodiment, the steps of forming the first graphic layer and the second graphic layer are as shown in fig. 8 and 9.
Referring to fig. 8, a plurality of discrete core layers 203 are formed on the first and second initial mask layers 201, respectively, wherein a distance between the core layers 203 of adjacent first regions M is the same as a distance between the core layers 203 of adjacent second regions N, a dimension of the core layers 203 of the first regions M along the first direction is a third dimension, a dimension of the core layers 203 of the second regions N along the first direction is a fourth dimension, and the third dimension is equal to the fourth dimension.
In this embodiment, the core layer 203 is located on the stop layer 202.
The step of forming the core layer 203 includes: forming an initial core layer on the stop layer 202; forming a patterned fourth photoresist on the initial core layer; and etching the initial core layer by taking the fourth photoresist as a mask to form a core layer 203.
The step of forming the patterned fourth photoresist comprises: providing a first photomask, wherein the first photomask is provided with a mask pattern; forming a fourth initial photoresist on the initial core layer 203; and carrying out exposure treatment on the fourth initial photoresist through the first photomask to form fourth photoresist.
It should be noted that, if the widths of the mask patterns in the first photomask are different or the distances between adjacent mask patterns are different, the distortion in the fourth photoresist caused by the interference and scattering of light is large during the exposure process, which easily causes the dimension of the formed fourth photoresist to be difficult to control, and further easily affects the performance of the formed semiconductor structure. Therefore, the size and pitch of the mask patterns in the first reticle are the same.
Since the pitch between the core layers 203 of the adjacent first regions M is the same as the pitch between the core layers 203 of the adjacent second regions N, and the distance between the centers of the core layers 203 of the adjacent first regions M is equal to the distance between the centers of the core layers 203 of the adjacent second regions N, the first regions M and the second regions N can be formed through the same process, which can simplify the process flow. In addition, the first region M core layer 203 and the second region N core layer 203 may be formed by the same mask. Therefore, the forming method can save the photomask and reduce the process cost.
In this embodiment, the material of the core layer 203 is amorphous carbon. In other embodiments, the material of the core layer may also be amorphous silicon or amorphous germanium.
The width of the core layers 203 and the spacing between adjacent core layers 203 may affect the spacing between subsequently formed graphics layers. In this embodiment, the distances between the first pattern layers to be formed subsequently are equal, the distances between the second pattern layers are equal, and are equal to the distances between the first pattern layers, and then the distance between the core layers 203 is equal to the sum of the width of the core layer 203 and the double thickness of the initial pattern layers to be formed subsequently.
If the width of the core layer 203 and the spacing between adjacent core layers 203 are too large or too small, the spacing between the subsequently formed first pattern layers 271 and the spacing between the second pattern layers 272 are too large or too small, which may easily affect the performance of the formed semiconductor structure. Specifically, in this embodiment, the width of the core layer 203 is 44nm to 68 nm; the spacing between adjacent core layers 203 is 56nm to 68 nm.
With continued reference to fig. 8, an initial graphics layer 270 is formed on the top and sidewalls of the core layer 203, as well as on the initial mask layer 201.
The initial graphics layer 270 is used for subsequently forming a first graphics layer and a second graphics layer.
In this embodiment, the material of the initial pattern layer 270 is silicon nitride. In other embodiments, the material of the initial pattern layer may also be silicon oxide or silicon oxynitride.
The thickness of the initial pattern layer 270 may affect the width of a subsequently formed mask layer, and further affect the width of a subsequently formed first region M functional layer. The thickness of the initial pattern layer 270 is too large or too small, which easily causes the width of a functional layer to be formed later to be too large or too small, and further easily affects the performance of the formed semiconductor structure. In this embodiment, the thickness of the initial pattern layer 270 is 6nm to 8 nm.
The process of forming the initial pattern layer 270 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 9, the initial pattern layer 270 is anisotropically etched to remove the initial pattern layer 270 on the initial mask layer 201 and on the top of the core layer 203 (as shown in fig. 11), form a plurality of discrete first pattern layers 271 in the first region M, and form second pattern layers 272 in the removal region N1 and the retention region N2, respectively.
The first pattern layer 271 and the second pattern layer 272 are used as a mask for a subsequent etching initial mask layer to form the mask layer 204.
It should be noted that, since the distances between the core layers 203 of the first region M and the second region N are equal, and the thicknesses of the core layers 203 of the first region M and the second region N are equal, the etching rates of the initial pattern layers 270 of the first region M and the second region N are the same in the process of etching the initial pattern layers 270. Therefore, in the process of etching the initial pattern layer 270, the second region N stop layer 202 is not easily damaged, so that the thicknesses of the first region M and the second region N stop layer 202 can be the same, and further the subsequent process is not easily affected. The forming method can improve the performance of the formed semiconductor structure.
The anisotropic etching has a lateral etching rate less than a longitudinal etching rate, and can remove the initial pattern layer 270 on the initial mask layer 201 and on the top of the core layer 203.
In this embodiment, the anisotropic etching process includes an anisotropic dry etching process.
The thicknesses of the first pattern layer 271 and the second pattern layer 272 are determined by the thickness of the initial pattern layer 270, and the thicknesses of the first pattern layer 271 and the second pattern layer 272 are equal to the thickness of the initial pattern layer 270, specifically, the thicknesses of the first pattern layer 271 and the second pattern layer 272 are 6nm to 8 nm.
It should be noted that, since the initial pattern layer 270 (shown in fig. 11) is formed on the four sidewalls and the top of the core layer 203 (shown in fig. 11) and the initial mask layer 201 (shown in fig. 11). The anisotropic etching is used for removing the initial pattern layers 270 on the top of the core layer 203 and the initial mask layer 201, the initial pattern layers 270 on the surfaces of the four side walls of the core layer 203 are reserved, a plurality of discrete first pattern layers 271 are formed in the first region M, a first side wall is arranged between every two adjacent first pattern layers 271 and is in contact with the adjacent first pattern layers 271, the first side walls and the adjacent first pattern layers 271 form a ring structure, a second side wall is arranged between every two adjacent second pattern layers 272 and is in contact with the adjacent second pattern layers 272, and the second side walls and the adjacent second pattern layers 272 form a ring structure.
In this embodiment, the number of the second graphic layers 272 in the removal area N2 is one. In other embodiments, the number of the second graphic layers 272 of the removal region N2 may be multiple, and the arrangement direction of the second graphic layers 272 of the multiple removal regions N2 is the same as the first direction.
With continued reference to fig. 9, after the anisotropic etch, the core layer 203 is removed (as shown in fig. 11).
The process of removing the core layer 203 includes: a dry etching process or a wet etching process.
A subsequent formation of a widening layer covers the sidewalls of the mask layer 204 in the reserved area N1.
In this embodiment, the step of forming the widening layer is as shown in fig. 10 to 12.
Referring to fig. 10, a first planarization layer 220 is formed on the initial mask layer 201, the first pattern layer 271 and the second pattern layer 272, and the surface of the first planarization layer 220 is higher than the tops of the first pattern layer 271 and the second pattern layer 272.
The first flat layer 220 is used for forming a widening layer in the subsequent process, and the surface of the first flat layer 220 is relatively flat, so that light scattering can be reduced, and further, the influence of scattered light on the first photoresist can be reduced in the subsequent process of forming the first photoresist.
The material of the first planarization layer 220 is different from the material of the stop layer 202, so that the loss of the stop layer 202 in the process of etching the first planarization layer 220 can be reduced.
The material of the first planarization layer 220 is an organic dielectric material, and in other embodiments, the material of the planarization layer may also be a bottom anti-reflective material.
In this embodiment, the process of forming the first planarization layer 220 includes a spin coating process.
Referring to fig. 11, a first anti-reflective coating 221 is formed on the first planarization layer 220.
The first anti-reflective coating 221 is used to absorb light reflected under the first anti-reflective coating 221, so as to reduce the influence of the reflected light on the first photoresist 222 during the subsequent formation of the first photoresist 222.
The material of the first anti-reflective coating 221 is an organic polymer.
The process of forming the first anti-reflective coating 221 includes a spin coating process.
With continued reference to fig. 11, a patterned first photoresist 222 is formed on the first planarization layer 220, the patterned first photoresist 222 completely covers the top of the reserved region N1 second pattern layer 271, and the dimension of the first photoresist 222 in the first direction is greater than the dimension of the reserved region N1 second pattern layer 272 in the first direction.
The first photoresist 222 is used for a mask for subsequently etching the first planarization layer 220.
In this embodiment, the first photoresist 222 is located on the first anti-reflective coating 221.
The step of forming the first photoresist 222 includes: forming a first initial photoresist on the first anti-reflective coating layer 221; the first initial photoresist is exposed to form a first photoresist 222.
Referring to fig. 12, the first planarization layer 220 (shown in fig. 11) is etched using the first photoresist 222 as a mask to form a wide layer 212.
The widening layer 212 is used for controlling the width of the subsequently formed reserved N1 mask layer 204, so as to control the width of the subsequently formed reserved N1 functional layer, and further enable the reserved N1 functional layer to have the performance required by design.
The process of etching the first planarization layer 220 includes an anisotropic dry etching process. The anisotropic dry etching has good directionality and good line width control, and the width of the formed widening layer 212 is easy to control, so that the width of the subsequently formed mask layer can be accurately controlled. In other embodiments, the process of etching the first planarization layer includes an isotropic dry etching process or a wet etching process.
It should be noted that, in other embodiments, the step of forming the widening layer includes: forming an initial widening layer covering the side walls of the first graphic layer and the second graphic layer, wherein the initial widening layer is made of a photoresist material; and exposing the initial widening layer, and removing the initial widening layer on the surface of the side wall of the first graph layer to form a widening layer.
Referring to fig. 13, the initial mask layer 201 (shown in fig. 12) is etched using the width layer 212 (shown in fig. 12), the first pattern layer 271 (shown in fig. 12) and the second pattern layer 272 (shown in fig. 12) as masks to form a mask layer 204.
The mask layer 204 serves as a mask for subsequent etching of the initial functional layer 210.
Since the widening layer 212 is located on the sidewall surface of the second pattern layer 272, after the initial mask layer 201 is etched by using the widening layer 212, the first pattern layer 271 and the second pattern layer 272 as masks, the width of the mask layer in the reserved area N2 is greater than the width of the second pattern layer 272.
In this embodiment, the initial mask layer 201 has a stop layer 202 thereon. Before etching the initial mask layer 201, the method further includes: and etching the stop layer 221 by using the widening layer 212, the first pattern layer 271 and the second pattern layer 272 as masks to expose the initial mask layer 201.
In this embodiment, the process of etching the initial mask layer 201 and the stop layer 202 includes an anisotropic dry etching process. The anisotropic dry etching has good directionality and good line width control, and the width of the formed mask layer 204 is easy to control, so that the width of a subsequently formed functional layer can be accurately controlled. In other embodiments, the process of etching the initial mask layer includes an isotropic dry etching process or a wet etching process.
The mask layer 204 is in a strip shape, and a direction perpendicular to the extending direction of the mask layer 204 is a second direction. In this embodiment, the second direction is parallel to the first direction.
It should be noted that, since the initial pattern layer 270 (shown in fig. 8) is formed on the four sidewalls and the top of the core layer 203 (shown in fig. 8) and the initial mask layer 201 (shown in fig. 8). The anisotropic etching is performed to remove the top of the core layer 203 and the initial pattern layers 270 on the initial mask layer 201, and the initial pattern layers 270 on the four side wall surfaces of the core layer 203 are retained, so that a plurality of discrete first pattern layers 271 are formed in the first region M, a first side wall is arranged between every two adjacent first pattern layers 271, the first side wall is in contact with the adjacent first pattern layers 271, the first side wall and the adjacent first pattern layers 271 form an annular structure, a second side wall is arranged between every two adjacent second pattern layers 272, the second side wall is in contact with the adjacent second pattern layers 272, and the second side wall and the adjacent second pattern layers 272 form an annular structure.
The etching step performed on the initial mask layer 201 further uses the first side wall and the second side wall as masks, and forms a first connection layer 311 in the first region M (as shown in fig. 15) and a second connection layer 312 in the second region N (as shown in fig. 15), where two ends of the first connection layer 311 are respectively in contact with the adjacent first pattern layers 271, and two ends of the second connection layer 312 are respectively in contact with the adjacent second pattern layers 272.
Referring to fig. 14, after forming the mask layer 204, the stop layer 202 on the mask layer 204 is removed (as shown in fig. 13).
It should be noted that, since the thicknesses of the first M and second N stop layers 202 are equal, and the densities of the first M mask layer 204 and the second N mask layer 204 are the same, in the process of removing the stop layer 202 on the mask layer 204, the removal rates of the stop layers 202 in the first M and second N regions are the same, so that by controlling the removal time and the removal rate, the second N stop layer 202 can be removed while the first M stop layer 202 is removed. Therefore, the forming method can reduce the loss of the second region N mask layer 204, so that the thicknesses of the first region M and the second region N mask layer 204 are the same.
In this embodiment, the process of removing the stop layer 202 includes chemical mechanical polishing.
And subsequently, patterning the mask layer 204 to form a second opening in the mask layer 204, wherein the second opening penetrates through the mask layer 204 in the second direction, the second direction is perpendicular to the extending direction of the mask layer 204, and the first connection layer 311 and the second connection layer 312 are removed.
The removal of the first connection layer 311 and the second connection layer 312 serves to separate the mask layers 204 from each other, thereby allowing a discrete dummy gate to be subsequently formed.
In this embodiment, the patterning process is further used to control the length of the mask layer 204, so that the mask layer 204 has a designed length.
In this embodiment, the steps of removing the first connection layer and the second connection layer and the patterning process are as shown in fig. 15 to 18.
Referring to fig. 15 and 16, fig. 16 is a cross-sectional view taken along cutting line 1-2 of fig. 15, wherein a second planarization layer 261 is formed on the initial functional layer 210 and the mask layer 204; forming a second antireflection coating 205 on the second flat layer 261; a patterned second photoresist (not shown) is formed on the second anti-reflective coating layer 205.
The surface of the second planarization layer 261 is relatively flat, so that scattering of light can be reduced, and further, the influence of the scattered light on the second photoresist can be reduced in the process of forming the second photoresist.
The step of forming the second photoresist comprises: providing a second photomask 300, wherein the second photomask 300 is provided with a photomask graph 301; forming a second initial photoresist on the second anti-reflective coating layer 205; and exposing the second initial photoresist through the second photomask 300 to form a second photoresist.
The mask pattern is used to define the locations and dimensions of the removed first connection layer 311, second connection layer 312, and mask layer 204.
The material of the second planarization layer 261 is an organic dielectric material. The process of forming the second planarization layer 261 includes a spin coating process.
The process of forming the second antireflection coating 205 includes a spin coating process; the process of forming the second initial photoresist includes a spin-on process.
Referring to fig. 17 and 18, fig. 18 is a cross-sectional view of fig. 17 along a cutting line 3-4, the mask layer 204, the first connection layer 311, and the second connection layer 312 are etched by using the second photoresist as a mask, the first connection layer 311 and the second connection layer 312 are removed, and a second opening is formed in the mask layer 204, wherein the second opening penetrates through the mask layer 204 in the first direction.
The removal of the connecting layer 310 serves to separate the mask layers 204 from each other, thereby allowing the subsequent formation of discrete dummy gates. The second opening is used to control the length of the mask layer 204, so that the mask layer 204 has a designed length.
The process for etching the mask layer 204 and the connection layer 310 includes a dry etching process or a wet etching process.
Referring to fig. 19, the initial functional layer 210 is etched using the mask layer 204 as a mask to form a functional layer 211.
In this embodiment, the functional layer 211 is used as a dummy gate. In other embodiments, the functional layer may also be used as an interconnection line, and the material of the functional layer is metal.
In this embodiment, the process of etching the initial functional layer 210 by using the mask layer 204 as a mask includes a dry etching process. The dry etching process has good line width control, and can control the width of the formed functional layer 211.
By controlling the dry etching process parameters, the etching rate of the initial functional layer 210 in the transverse and longitudinal directions is controlled, thereby realizing the control of the width of the functional layer 211.
In this embodiment, the longitudinal etching rate is made to approach zero, so that the width of the formed functional layer 211 can be adjusted by controlling the etching time, thereby improving the accuracy of the width of the formed functional layer 211. Specifically, the lateral etching rate and the longitudinal etching rate can be controlled by controlling the lateral power and the longitudinal power of the dry etching.
In this embodiment, the process parameters for etching the initial functional layer 210 include: the etching gas comprises CF4、CHF3、CH2F2、CH3F、SF6、HBr、Cl2、O2、N2The flow rate of the etching gas is 10sccm to 500sccm, the diluent gas comprises He and Ar, the flow rate of the He is 100sccm to 1000sccm, and the flow rate of the Ar is 100sccm to 1000 sccm; the power of the radio frequency source is 200-2000W; the bias voltage drop is 100V-1000V; the etching time is 20 s-60 s.
It should be noted that, in this embodiment, the densities of the first region M and the second region N mask layer 204 are the same, and the etching rates of the first region M and the second region N initial functional layer 210 are the same. In addition, the first M and second N mask layers 204 have the same thickness. Therefore, the second region N substrate 200 can be exposed while the first region M substrate 200 is just exposed, so that when the first region M initial functional layer 210 is exposed, the second region N substrate 200 can be prevented from being damaged due to over-etching, the loss of the second region N substrate 200 can be reduced, and the performance of the formed semiconductor structure can be improved.
Referring to fig. 20, a protective layer 250 is formed on the substrate 200, wherein the protective layer 250 covers the sidewalls of the functional layer 211 and exposes the top of the functional layer 211 in the reserved region N1.
The protective layer 250 is used to protect the substrate 200, so that the substrate 200 can be protected during the subsequent process of removing the functional layer 211 in the removal region N2, and the loss of the substrate 200 is reduced.
The material of the protective layer 250 is silicon oxide or titanium oxide.
The step of forming the protective layer 250 includes: forming an initial protective layer on the first and second regions M and N of the substrate 200, the initial protective layer covering sidewalls and the top of the functional layer 211; and performing first planarization treatment on the initial protective layer, and removing the initial protective layer on the functional layer 211 to form a protective layer 250.
In this embodiment, the process of forming the initial protection layer includes a fluid chemical vapor deposition process. The precursors of the fluid chemical vapor deposition process are fluids that can substantially fill the gaps between the functional layers 211. Therefore, the initial protection layer formed by the fluid chemical vapor deposition process has good filling performance and can provide sufficient protection for the substrate 200.
The first planarization process comprises a chemical mechanical polishing process.
In this embodiment, the blank M2 functional layer 211 is subsequently removed, so that the protective layer 250 also exposes the top of the blank M2 mask layer 204.
The forming method further includes: forming a third anti-reflective coating 241 on the protection layer 250 and the mask layer 204; forming a patterned third photoresist 242 on the third anti-reflective coating 241; the third photoresist 242 exposes the removal region N2 and the blank region M2 anti-reflection coating 241.
In the process of forming the third photoresist 242, the third anti-reflective coating 241 is used to absorb the light reflected by the substrate 200, and reduce the influence of the reflected light on the third photoresist 242.
The third photoresist 242 is used to protect the functional layer 211 of the functional region M1 and the reserved region N1.
Referring to fig. 21, the functional layer 211 in the removal region N2 is removed.
In this embodiment, after the protective layer 250 is formed, the functional layer 211 in the removal region N2 is removed. During the process of removing the functional layers 211 in the removal region N2, the protective layer 250 can protect the substrate 200 between adjacent functional layers 211, reduce the loss of the substrate 200, and thus improve the performance of the formed semiconductor structure.
In this embodiment, the forming method further includes: the blank area M2 functional layer 211 is removed.
In this embodiment, the functional layer 211 in the blank region M2 and the removal region N2 are removed by the same process. The blank region M2 and the functional layer 211 of the removal region N2 are removed by the same process, so that the process flow can be simplified, and the process cost can be reduced.
In this embodiment, the functional layer 211 and the mask layer 204 are etched by using the third photoresist 242 as a mask, the mask layer 204 in the blank region M2 and the removal region N2, and the functional layer 211 in the blank region M2 and the removal region N2 are removed, and a trench 251 is formed in the protective layer 250.
Referring to fig. 22, after the functional layer 211 of the removal region N2 is removed, the protective layer 250 is removed.
In this embodiment, the process of removing the protection layer 250 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 23, after removing the protective layer 250, a dielectric layer 252 is formed on the substrate 200.
The dielectric layer 252 is used to achieve electrical isolation between the functional layers 211.
The dielectric layer 252 is made of silicon oxide, silicon nitride, silicon oxynitride or a low-k (k is less than 3.9) dielectric material.
The step of forming the dielectric layer 252 includes: forming an initial dielectric layer on the substrate 200, wherein the initial dielectric layer covers the side wall and the top of the functional layer 211; and performing second planarization treatment on the initial dielectric layer, and removing the initial dielectric layer on the top of the functional layer 211 to form a dielectric layer 252.
The process for forming the initial dielectric layer comprises a fluid chemical vapor deposition process or a high aspect ratio deposition process.
The second planarization process includes a chemical mechanical polishing process.
It should be noted that, in other embodiments, the protective layer may not be removed. And forming a groove in the protective layer after removing the blank area and the removal area functional layer. The forming method further includes: and forming an isolation layer in the groove, wherein the isolation layer and the protective layer form a dielectric layer. The isolation layer and the protection layer are made of silicon oxide, silicon nitride or silicon oxynitride or low-k dielectric materials.
Referring to fig. 24, the functional layer 211 (shown in fig. 23) is removed to form a first opening in the dielectric layer 252; a gate structure 260 is formed in the first opening.
It should be noted that the thicknesses of the mask layer 204 in the first region M and the second region N are the same, and the thicknesses of the functional layer 211 in the first region M and the second region N are the same. In the process of forming the first opening, the functional layers 211 of the first region M and the second region N can be removed simultaneously, so that the substrate 200 of the second region N is not easy to be etched, the loss of the substrate 200 can be reduced, and the performance of the formed semiconductor structure can be improved.
The gate structure 260 includes: the gate dielectric layer covers the bottom and the side wall of the first opening; and the grid electrode is positioned on the grid dielectric layer.
The gate dielectric layer is made of a high-k (k is greater than 3.9) dielectric material, for example: for example: HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
The material of the grid is metal, such as: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
The present invention also provides a semiconductor structure formed by the method of formation shown in fig. 7-24.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, the second area comprises a removal area and a retention area which are mutually separated and alternately arranged, and the arrangement direction of the removal area and the retention area is a first direction;
forming an initial functional layer on the first area and the second area substrate;
forming an initial mask layer on the initial functional layer;
forming a plurality of discrete first graphic layers on the first area initial mask layer, and forming second graphic layers on the removal area initial mask layer and the retention area initial mask layer respectively, wherein the size of the first graphic layers along the first direction is a first size, the size of the second graphic layers along the first direction is a second size, the second size is equal to the first size, and the distance between every two adjacent first graphic layers is equal to the distance between every two adjacent second graphic layers;
forming a widening layer covering the side wall of the second graphic layer of the reserved area;
etching the initial mask layer by taking the widening layer, the first graph layer and the second graph layer as masks to form a mask layer;
etching the initial functional layer by taking the mask layer as a mask to form a functional layer;
and removing the functional layer in the removal area.
2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the first and second patterned layers comprises: respectively forming a plurality of discrete core layers on the first region initial mask layer and the second region initial mask layer, wherein the distance between the core layers of the adjacent first regions is equal to the distance between the core layers of the adjacent second regions, the dimension of the core layers of the first regions along the first direction is a third dimension, the dimension of the core layers of the second regions along the first direction is a fourth dimension, and the third dimension is equal to the fourth dimension; forming an initial pattern layer on the top and the side wall of the core layer and the initial mask layer; carrying out anisotropic etching on the initial pattern layer, removing the initial mask layer and the initial pattern layer on the top of the core layer, forming a plurality of discrete first pattern layers in the first area, and forming a second pattern layer in the removal area and the reserved area; after the anisotropic etching, the core layer is removed.
3. The method of forming a semiconductor structure of claim 2, wherein forming the core layer further comprises, prior to: forming a stop layer on the initial mask layer, wherein the material of the stop layer is different from that of the core layer; after the mask layer is formed, the method further comprises the following steps: and removing the stop layer on the mask layer.
4. The method of forming a semiconductor structure of claim 1, wherein forming the topology layer comprises: forming a first flat layer on the initial mask layer, the first graphic layer and the second graphic layer, wherein the surface of the first flat layer is higher than the tops of the first graphic layer and the second graphic layer; forming a first patterned photoresist on the first flat layer, wherein the first patterned photoresist completely covers the top of the second pattern layer of the reserved area, and the size of the first photoresist is larger than that of the second pattern layer of the reserved area along the first direction; and etching the first flat layer by taking the first photoresist as a mask to form the widening layer.
5. The method of claim 4, wherein the material of the first planarization layer is an organic dielectric material.
6. The method of forming a semiconductor structure of claim 1, wherein forming the topology layer comprises: forming an initial widening layer covering the side walls of the first graphic layer and the second graphic layer, wherein the initial widening layer is made of a photoresist material; and carrying out exposure treatment on the initial widening layer, and removing the initial widening layer of the first area to form a widening layer.
7. The method of forming a semiconductor structure of claim 1, wherein prior to removing said depletion region functional layer, further comprising: and forming a protective layer on the first area substrate and the second area substrate, wherein the protective layer covers the side wall of the functional layer and exposes the top of the functional layer in the removal area.
8. The method of forming a semiconductor structure of claim 7, wherein forming the protective layer comprises: forming an initial protective layer on the first area substrate and the second area substrate, wherein the initial protective layer covers the side wall and the top of the functional layer; and carrying out first flattening treatment on the initial protective layer, and removing the initial protective layer on the functional layer to form a protective layer.
9. The method of forming a semiconductor structure of claim 7, further comprising, after removing said depletion region functional layer: and removing the protective layer.
10. The method of forming a semiconductor structure of claim 9, further comprising, after removing the protective layer: forming an initial dielectric layer on the substrate, wherein the initial dielectric layer covers the side wall and the top of the functional layer; performing second planarization treatment on the initial dielectric layer, and removing the initial dielectric layer on the top of the functional layer to form a dielectric layer; removing the functional layer and forming a first opening in the dielectric layer; and forming a gate structure in the first opening.
11. The method of forming a semiconductor structure according to claim 9, wherein a material of the initial protective layer is silicon oxide or titanium oxide; the process of forming the initial protective layer includes a fluid chemical vapor deposition process.
12. The method of forming a semiconductor structure of claim 9, wherein after removing the removal region functional layer, forming a trench in the protective layer;
the forming method further includes: an isolation layer is formed in the trench.
13. The method of forming a semiconductor structure according to claim 1, wherein the first region includes a functional region and a blank region; the forming method further includes: removing the functional layer in the blank area; and removing the blank area functional layer and the removal area functional layer by the same process.
14. The method for forming the semiconductor structure according to claim 1, wherein a first sidewall is provided between adjacent first pattern layers, the first sidewall is in contact with the adjacent first pattern layers, and the first sidewall and the adjacent first pattern layers form a ring structure; a second side wall is arranged between the adjacent second graphic layers, the second side wall is in contact with the adjacent second graphic layers, and the second side wall and the adjacent second graphic layers form an annular structure; the step of etching the initial mask layer further takes the first side wall and the second side wall as masks, respectively forms a first connecting layer in the first area, and forms a second connecting layer in the second area, wherein two ends of the first connecting layer are respectively contacted with the adjacent first pattern layers, and two ends of the second connecting layer are respectively contacted with the adjacent second pattern layers;
before etching the initial functional layer, the method further comprises: and removing the first connecting layer and the second connecting layer.
15. The method of claim 14, wherein the mask layer is elongated and the direction perpendicular to the mask layer is a second direction; before forming the functional layer, the forming method further includes: carrying out patterning processing on the mask layer, and forming a second opening in the mask layer, wherein the second opening penetrates through the mask layer in a second direction, and the second direction is perpendicular to the extending direction of the mask layer;
removing the first and second connection layers, and the step of patterning includes: and etching the mask layer, the first connecting layer and the second connecting layer, removing the first connecting layer and the second connecting layer, and forming a second opening in the mask layer, wherein the second opening penetrates through the mask layer in the second direction.
16. The method of forming a semiconductor structure according to claim 1, wherein the number of functional layers in the removal region is one or more.
17. The method of claim 1, wherein the functional layer is formed from a material selected from the group consisting of polysilicon, poly-germanium, poly-silicon-germanium, aluminum, tungsten, and copper-aluminum.
18. The method of forming a semiconductor structure according to claim 1, wherein a distance between centers of the functional layers in adjacent first regions is 50nm to 60 nm; the distance between the centers of the functional layers in the adjacent second areas is 100 nm-120 nm; the size of the first area functional layer along the first direction is 6 nm-8 nm; the size of the reserved area functional layer along the first direction is 12 nm-16 nm.
19. The method for forming a semiconductor structure according to claim 1, wherein the process parameters for etching the initial functional layer with the mask layer as a mask include: the etching gas comprises CF4、CHF3、CH2F2、CH3F、SF6、HBr、Cl2、O2、N2The flow rate of the etching gas is 10sccm to 500sccm, the diluent gas comprises He and Ar, the flow rate of the He is 100sccm to 1000sccm, and the flow rate of the Ar is 100sccm to 1000 sccm; the power of the radio frequency source is 200-2000 watts; the bias voltage drop is 100V-1000V; the etching time is 20 s-60 s.
20. A semiconductor structure formed by the method of forming a semiconductor structure of any one of claims 1 through 19.
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