CN113764274A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113764274A
CN113764274A CN202010492479.0A CN202010492479A CN113764274A CN 113764274 A CN113764274 A CN 113764274A CN 202010492479 A CN202010492479 A CN 202010492479A CN 113764274 A CN113764274 A CN 113764274A
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layer
pattern
forming
sacrificial layer
sacrificial
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张冬平
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer

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Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: providing a semiconductor substrate, wherein a first mask layer is formed on the semiconductor substrate; forming first sacrificial layer patterns which are separated and have at least two widths on the first mask layer; forming a first side wall on the side wall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a first side wall which is separated and has at least two intervals; transferring the pattern of the first side wall to the first mask layer to form a patterned first mask layer, and removing the first side wall; and etching part of the semiconductor substrate by taking the patterned first mask layer as a mask to form the fin part with at least two intervals. The forming method can obtain the fin parts which are distributed non-uniformly.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As the size of the Fin semiconductor structure is reduced to 14nm or less, the Fin pitch (Fin pitch) is shortened by a Self-Aligned Double Patterning (SADP) process or a Self-Aligned quad Patterning (SAQP) process to increase the density of the device. However, for some special designs, such as Static Random-Access Memory (SRAM), non-uniform fin spacing is required to achieve the process window.
At present, the non-uniform fin spacing can be obtained by a side wall merging method, but the method has many process problems, for example, the number of layers of required mask layers is large, the process is complex, the phenomenon of insufficient side wall merging easily occurs, Line Edge Roughness (LER) is affected when the mask layers are removed, and it is difficult to control the Line width and the Line spacing simultaneously.
Disclosure of Invention
The technical problem to be solved by the present application is to provide a method for forming a semiconductor structure, wherein a fin portion is formed on the semiconductor structure and is non-uniformly distributed.
In order to solve the above technical problem, the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein a first mask layer is formed on the semiconductor substrate; forming first sacrificial layer patterns which are separated and have at least two widths on the first mask layer; forming a first side wall on the side wall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a first side wall which is separated and has at least two intervals; transferring the pattern of the first side wall to the first mask layer to form a patterned first mask layer, and removing the first side wall; and etching part of the semiconductor substrate by taking the patterned first mask layer as a mask to form the fin part with at least two intervals.
In an embodiment of the present application, the process of forming the first sacrificial layer pattern which is separated and has at least two widths on the first mask layer includes: sequentially forming a first sacrificial layer, a second mask layer, a second sacrificial layer and a protective layer only covering the first area on the first mask layer; forming a second patterned photoresist layer on the second sacrificial layer and the protective layer, wherein the pattern of the second photoresist layer in the first region is different from the pattern of the second photoresist layer in other regions; transferring the pattern of the second photoresist layer to the second sacrificial layer and the protective layer of the first region to form a patterned second sacrificial layer and a patterned protective layer; forming a second side wall on the side wall of the patterned second sacrificial layer; removing the second sacrificial layers of other regions, forming a second sacrificial layer pattern consisting of the second side wall, the second sacrificial layer of the first region and the protective layer in the first region, and forming a second sacrificial layer pattern consisting of the second side wall in other regions; transferring the second sacrificial layer pattern to the second mask layer and the first sacrificial layer to form a second mask layer pattern and a first sacrificial layer pattern; and removing the second sacrificial layer pattern and the second mask layer pattern.
In an embodiment of the present application, the process of forming the protective layer covering only the first region includes: forming a protective layer material on the surface of the second sacrificial layer; forming a patterned first photoresist layer on the protective layer material, the first photoresist layer covering only the protective layer material of the first region; transferring the pattern of the first photoresist layer to the protective layer material, removing the first photoresist layer, and forming a protective layer only covering the first area.
In an embodiment of the present application, a material of the protective layer includes at least one of silicon oxide, silicon nitride, polysilicon, and amorphous silicon.
In an embodiment of the present application, the process of forming the patterned second photoresist layer on the second sacrificial layer and the protective layer includes: sequentially forming a photoetching auxiliary layer and a photoresist on the surfaces of the second sacrificial layer and the protective layer; and forming a patterned second photoresist layer after exposing and developing the photoresist.
In an embodiment of the present application, the process of transferring the pattern of the second photoresist layer to the second sacrificial layer and the protective layer of the first region to form the patterned second sacrificial layer and the protective layer includes: etching the photoetching auxiliary layer, the protective layer and the second sacrificial layer by taking the patterned second photoresist layer as a mask, and transferring the pattern of the second photoresist layer to the second sacrificial layer and the protective layer of the first region; and removing the second photoresist layer and the photoetching auxiliary layer.
In an embodiment of the present application, the lithography auxiliary layer includes at least one of an organic dielectric material layer, an anti-reflection layer, a deep ultraviolet light absorbing silicon oxide layer, an amorphous carbon layer, a silicon oxide layer, or a phosphosilicate glass layer.
In an embodiment of the present application, a material of the second sidewall spacer includes at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In an embodiment of the present application, the thickness of the second sidewall is 10nm to 25 nm.
In an embodiment of the present application, the first mask layer includes at least one insulating layer.
In an embodiment of the present application, the material of the insulating layer includes at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Compared with the prior art, the technical scheme of the application has the following beneficial effects:
the first sacrificial layer patterns which are separated and have at least two widths are used as masks, the semiconductor substrate is etched, fin parts with different pitches can be obtained, namely, non-uniform fin pitches are formed, and the requirements of the SRAM on a process window are met.
Further, by forming the protective layer on the surface of the second sacrificial layer in the first region and not forming the protective layer on the surfaces of the second sacrificial layers in other regions, when the second sacrificial layer is removed in a subsequent process, only the second sacrificial layer in the other regions is removed without affecting the second sacrificial layer in the first region, so that the patterns of the second sacrificial layers formed in the first region and the other regions are different. The different second sacrificial layer patterns are transferred to the first sacrificial layer at one time, the first sacrificial layer patterns formed in the first region and the other regions are different, the distance between the first side walls formed by the two layers of the first sacrificial layer patterns is different, and then the first side walls are used as masks, so that the distances between the fin parts formed by etching the semiconductor substrate are different inevitably and are in non-uniform distribution.
According to the forming method, the fin parts in non-uniform distribution can be obtained through fewer mask layers, the number of the used mask layers is reduced, the influence of a mask layer removing process on LER is obviously reduced, the precision of a semiconductor process is further improved, and the process steps are simplified. Meanwhile, the problem of insufficient side wall combination when the non-uniform fin parts are formed by side wall combination in the prior art is solved, and the product yield is improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 3 to 14 are schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
As shown in fig. 1, some semiconductor devices require special designs to meet the requirements of process fabrication, such as SRAM that requires the introduction of non-uniform fin pitch to achieve the process window. The method commonly used to form non-uniform fins is sidewall merging, but some problems exist. Depositing a side wall material layer 11 on the surface and the side wall of the formed sacrificial layer pattern 10, then removing the side wall material layer on the surface of the sacrificial layer pattern, leaving the side wall material layers on the two sides of the sacrificial layer pattern to form a side wall 12, and then removing the sacrificial layer pattern 10 by taking the side wall 12 as a mask. In the place with larger fin spacing, the adjacent side walls need to be combined, and the problem of insufficient side wall combination (shown by dotted lines in the figure) can occur. Meanwhile, the number of mask layers required by the process of forming the non-uniform fin spacing is large, and LER is affected when the multiple mask layers are removed, so that the precision of the semiconductor process is affected.
Based on this, the present disclosure provides a method for forming a semiconductor structure, in which a discrete first sacrificial layer pattern having at least two widths is formed, and then a semiconductor substrate is etched using the first sacrificial layer pattern having different widths as a mask, so that fin portions having different pitches can be obtained, that is, non-uniform fin pitches are formed.
Referring to fig. 2, a method for forming a semiconductor structure according to an embodiment of the present disclosure includes:
step S1, providing a semiconductor substrate on which a first mask layer is formed;
step S2, forming a first sacrificial layer pattern which is discrete and has at least two widths on the first mask layer;
step S3, forming a first sidewall on the sidewall of the first sacrificial layer pattern, and removing the first sacrificial layer pattern to form a discrete first sidewall having at least two spacings;
step S4, transferring the pattern of the first sidewall to the first mask layer to form a patterned first mask layer, and removing the first sidewall;
step S5, using the patterned first mask layer as a mask, etching a portion of the semiconductor substrate to form a fin portion having at least two pitches.
Referring to fig. 3, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a first mask layer 110 formed thereon. The semiconductor substrate 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and further includes a multilayer structure composed of the material layers or silicon-on-insulator (SOI), stacked-on-insulator (SSOI), or the like. In the embodiment of the present application, the constituent material of the semiconductor substrate 100 is single crystal silicon or silicon on insulator.
Taking the SRAM structure as an example, the semiconductor substrate 100 may include an SRAM100a with non-uniform fin distribution, an SRAM100b with non-uniform fin distribution, and a fin uniform distribution region 100 c. Hereinafter, the "first region" is a region including the SRAM100a and the part of the SRAM100b, and the "other regions" are regions other than the first region, including the fin uniform distribution region 100c and the part of the SRAM100 b.
The first mask layer 110 is a single-layer or stacked-layer structure, and in some embodiments, the first mask layer 110 includes at least one insulating layer, and a material of the insulating layer may include at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, boron nitride, or boron carbonitride. In this embodiment, the first mask layer 110 is a stacked structure, and the stacked structure can improve the control capability of the subsequent etching process, thereby being beneficial to improving the control precision of the subsequent etching process and preventing the over-etching phenomenon, so that the size and the morphology of the subsequently formed fin portion meet the process requirements. The stacked structure includes a first silicon oxide layer 111, a silicon nitride layer 112, and a second silicon oxide layer 113. Wherein the thickness of the first silicon oxide layer may be 1nm to 10nm, the thickness of the silicon nitride layer 112 may be 15nm to 40nm, and the thickness of the second silicon oxide layer 113 may be 20nm to 60 nm.
Then, a first sacrificial layer pattern 120 which is separated and has at least two widths is formed on the first mask layer 110. The material of the first sacrificial layer pattern 120 is different from the material of the first mask layer 110, and the material of the first sacrificial layer pattern 120 is different from the material of the semiconductor substrate 100, so that when the first sacrificial layer pattern 120 is removed, the loss of the first mask layer 110 and the semiconductor substrate 100 can be reduced. In this embodiment, the first sacrificial layer pattern 120 is made of polysilicon. In other embodiments, the first sacrificial layer pattern 120 may also be amorphous carbon or photoresist.
Referring to fig. 4, a first sacrificial layer 130, a second mask layer 140, a second sacrificial layer 150, and a protective layer material 160 are sequentially formed on the first mask layer 110. The thickness of the second sacrificial layer 150 may be 60nm to 150nm, the thickness of the second mask layer 140 may be 20nm to 50nm, and the thickness of the first sacrificial layer 130 may be 60nm to 150 nm.
A patterned first photoresist layer 170 is formed on the protective layer material 160, and the first photoresist layer 170 covers only the protective layer material 160 of the first region. The first photoresist layer 170 may be obtained by exposure and development.
Referring to fig. 5, the first photoresist layer 170 is used as a mask to etch the protection layer material 160, the pattern of the first photoresist layer 170 is transferred to the protection layer material 160, the first photoresist layer 170 is removed, and the protection layer 180 covering only the first region is formed, in some embodiments, the material of the protection layer 180 may include at least one of silicon oxide, silicon nitride, polysilicon, and amorphous silicon, the thickness of the protection layer 180 may be 2nm to 10nm, a process for etching the protection layer material 160 may be dry etching, and process parameters of the dry etching may be adjusted according to actual process conditions. At this time, the protective layer 180 is formed on the surface of the second sacrificial layer 150 in the first region, the protective layer 180 is not formed on the surface of the second sacrificial layer 150 in the other region, and the protective layer 180 only covers the first region.
The protection layer 180 is formed in the first region, the protection layer 180 is not formed in other regions, and when the second sacrificial layer 150 is subsequently removed, only the second sacrificial layer 150 on other regions can be removed without affecting the second sacrificial layer 150 in the first region, so that different second sacrificial layer patterns can be formed in the first region and other regions, the different second sacrificial layer patterns are transferred to the first sacrificial layer to form a first sacrificial layer pattern, and the first sacrificial layer pattern can be transferred to the semiconductor substrate 100 through one transfer to form the fin portions with different fin pitches. Thus, forming the protective layer 180 to cover only the first region lays the foundation for forming different fin pitches.
Referring to fig. 6, a patterned second photoresist layer 190 is formed on the second sacrificial layer 150 and the protective layer 180, the pattern of the second photoresist layer 190 in the first region is different from the pattern of the second photoresist layer 190 in other regions, that is, the width of the second photoresist layer 190 in the first region is different from the width of the second photoresist layer 190 in other regions, and other regions may have the second photoresist layer 190 with one width or at least two widths, which are designed according to actual process requirements. The pattern of the second photoresist layer 190 affects a second sacrificial layer pattern formed by a subsequent process.
The width of the second photoresist layer 190 in the first region and the two widths included in the second photoresist layer 190 in the other regions are determined by the finally formed fin pitch and the actual design requirement, and are not limited herein.
The second photoresist layer 190 may be formed by sequentially forming a photoresist auxiliary layer 200 and a photoresist on the surfaces of the second sacrificial layer 150 and the protection layer 180, and exposing and developing the photoresist to form the second photoresist layer 190.
In some embodiments, the lithography assistant layer 200 may include at least one of an organic dielectric material layer, an anti-reflection layer, a deep ultraviolet light absorbing silicon oxide layer, an amorphous carbon layer, a silicon oxide layer, or a phosphosilicate glass layer. In this embodiment, the lithography auxiliary layer 200 includes a bottom anti-reflection layer and a silicon oxide layer.
Referring to fig. 6 and 7, the photoresist auxiliary layer 200, the protective layer 180 and the second sacrificial layer 150 are etched using the patterned second photoresist layer 190 as a mask, the pattern of the second photoresist layer 190 is transferred to the second sacrificial layer 150 and the protective layer 180 of the first region, and then the second photoresist layer 190 and the photoresist auxiliary layer 200 are removed to form the patterned second sacrificial layer 150 and the protective layer 180. Wherein the protective layer 180 is on the second sacrificial layer 150 in the first region, and the protective layer 180 is not on the second sacrificial layer 150 in other regions.
Referring to fig. 8, sidewall spacer materials are deposited on the surfaces of the first sacrificial layer 140 and the protective layer 180, the sidewalls of the patterned second sacrificial layer 150 in the first region, and the surfaces and sidewalls of the patterned second sacrificial layer 150 in other regions. And then etching the sidewall material to leave only the sidewall material of the sidewall of the patterned second sacrificial layer 150, thereby forming a second sidewall 210. In some embodiments, the material of the second sidewall spacers may include at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride. The width of the second sidewall 210 determines the width of the first sacrificial layer pattern in other regions formed by the subsequent process, and is designed according to the actual process. The width of the second sidewall spacers 210 depends on the size of the fin pitch, and in some embodiments, may be 5nm to 20 nm.
Referring to fig. 9, the second sacrificial layer 150 is removed from the other regions, forming a second sacrificial layer pattern 220. For example, the second sacrificial layer 150 in other regions may be removed by a dry etching process, and specific dry process parameters are adjusted according to actual process conditions, which is not limited herein. Since the protective layer 180 is formed on the second sacrificial layer 150 of the first region, it is not removed. Thus, the second sacrificial layer pattern 220 in the first region is different from the second sacrificial layer patterns 220 in other regions, the second sacrificial layer pattern 220 in the first region is composed of the second sidewall 210, the second sacrificial layer 150 in the first region, and the protective layer 180, and the second sacrificial layer patterns 220 in other regions are composed of only the second sidewall 210. The different second sacrificial layer patterns 220 may form different first sacrificial layer patterns in a subsequent process.
Referring to fig. 9 and 10, the second sacrificial layer pattern 220 is transferred to the second mask layer 140 and the first sacrificial layer 130, forming a second mask layer pattern 230 and a first sacrificial layer pattern 120. Specifically, in the first region, the second side wall 210, the second sacrificial layer 150 in the first region, and the protective layer 180 are used as masks to etch the second mask layer 140 and the first sacrificial layer 130 in the first region, and in other regions, the second side wall is used as a mask to etch the second mask layer 140 and the first sacrificial layer 130 in other regions, so that the second mask layer pattern 230 and the first sacrificial layer pattern 120 in the first region are the same as the second sacrificial layer pattern 220 in the first region, and the second mask layer pattern 230 and the first sacrificial layer pattern 120 in other regions are the same as the second sacrificial layer pattern 220 in other regions. The process method for etching the second mask layer 140 and the first sacrificial layer 130 may be a dry etching process, and specific dry etching process parameters are adjusted according to actual process conditions, which are not limited herein.
Referring to fig. 11, the second sacrificial layer pattern 220 and the second mask layer pattern 230 are removed. Since the width of the first sacrificial layer pattern 120 in the first region is equal to the width of the second sacrificial layer pattern 220 in the first region, that is, the width of the first sacrificial layer pattern 120 in the first region is equal to the sum of the width of the second sacrificial layer 150 and twice the thickness of the second sidewall 210. And the width of the first sacrificial layer pattern 120 of the other region is equal to the width of the second sacrificial layer pattern 220 of the other region, that is, the width of the first sacrificial layer pattern 120 of the other region is equal to the thickness of the second sidewall 210. Accordingly, the first sacrificial layer pattern 120 is formed on the first mask layer 110 to be discrete and to have at least two widths. The width of the first sacrificial layer pattern 120 represents a fin pitch between finally formed fins, and if the width of the first sacrificial layer pattern 120 is different, the fin pitch between the formed fins is also different, thereby forming non-uniform fins required by the SRAM.
Referring to fig. 12, a sidewall material is deposited on the surface and the sidewall of the first sacrificial layer pattern 120, and the sidewall material is etched, only the sidewall material of the sidewall of the first sacrificial layer pattern 120 is left, a first sidewall 240 is formed, and the first sacrificial layer pattern 120 is removed. The material of the first side wall may include at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride. The width of the first sidewall 240 depends on the width of the finally formed fin, and in some embodiments, the width of the first sidewall 240 may be 5nm to 20 nm. Since the first sacrificial layer patterns 120 have at least two widths, the first sidewalls 240 have at least two pitches and are separately arranged.
Referring to fig. 12 and 13, the first mask layer 110 is etched by using the first sidewall 240 as a mask, the pattern of the first sidewall 240 is transferred to the first mask layer 110, a patterned first mask layer 110 is formed, and the first sidewall 240 is removed. The process for etching the first mask layer 110 may be a dry etching process, and parameters of the dry etching process are adjusted according to actual process conditions.
Referring to fig. 13 and 14, a portion of the semiconductor substrate is etched by using the patterned first mask layer 110 as a mask to form a fin 250 with at least two pitches, which meets the requirement of the SRAM on non-uniform fin distribution.
According to the method for forming the semiconductor structure, the protective layer is formed on the surface of the second sacrificial layer in the first area, the protective layer is not formed on the surfaces of the second sacrificial layers in other areas, so that when the second sacrificial layer is removed in the subsequent process, only the second sacrificial layers in other areas are removed, and the second sacrificial layer in the first area is not affected, so that the patterns of the second sacrificial layers formed in the first area and the other areas are different, when the patterns of the second sacrificial layer are transferred to the first sacrificial layer, the patterns of the first sacrificial layer formed in the first area and the patterns of the other first sacrificial layers formed in other areas are also different, therefore, the distances between the patterns of the first sacrificial layer formed on two sides are also different, and the distance between the first side walls represents the distance between the finally formed fins, so that the fins which are not uniformly distributed can be obtained. In the forming process, only two mask layers are introduced, so that the number of the used mask layers is greatly reduced, the influence of the mask layer removing process on LER is obviously reduced, the precision of the semiconductor process is improved, and the process steps are simplified. Meanwhile, the problem that the side walls are insufficiently combined when the side walls are combined to form the non-uniform fin parts is solved, and the product yield is improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (11)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a first mask layer is formed on the semiconductor substrate;
forming first sacrificial layer patterns which are separated and have at least two widths on the first mask layer;
forming a first side wall on the side wall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a first side wall which is separated and has at least two intervals;
transferring the pattern of the first side wall to the first mask layer to form a patterned first mask layer, and removing the first side wall;
and etching part of the semiconductor substrate by taking the patterned first mask layer as a mask to form the fin part with at least two intervals.
2. The method of claim 1, wherein the step of forming the first sacrificial layer pattern on the first mask layer separately and with at least two widths comprises:
sequentially forming a first sacrificial layer, a second mask layer, a second sacrificial layer and a protective layer only covering the first area on the first mask layer;
forming a second patterned photoresist layer on the second sacrificial layer and the protective layer, wherein the pattern of the second photoresist layer in the first region is different from the pattern of the second photoresist layer in other regions;
transferring the pattern of the second photoresist layer to the second sacrificial layer and the protective layer of the first region to form a patterned second sacrificial layer and a patterned protective layer;
forming a second side wall on the side wall of the patterned second sacrificial layer;
removing the second sacrificial layers of other regions, forming a second sacrificial layer pattern consisting of the second side wall, the second sacrificial layer of the first region and the protective layer in the first region, and forming a second sacrificial layer pattern consisting of the second side wall in other regions;
transferring the second sacrificial layer pattern to the second mask layer and the first sacrificial layer to form a second mask layer pattern and a first sacrificial layer pattern;
and removing the second sacrificial layer pattern and the second mask layer pattern.
3. The method of claim 2, wherein the step of forming the protective layer covering only the first region comprises:
forming a protective layer material on the surface of the second sacrificial layer;
forming a patterned first photoresist layer on the protective layer material, the first photoresist layer covering only the protective layer material of the first region;
transferring the pattern of the first photoresist layer to the protective layer material, removing the first photoresist layer, and forming a protective layer only covering the first area.
4. The method as claimed in claim 2, wherein the material of the protective layer comprises at least one of silicon oxide, silicon nitride, polysilicon, and amorphous silicon.
5. The method as claimed in claim 2, wherein the step of forming a patterned second photoresist layer on the second sacrificial layer and the protective layer comprises:
sequentially forming a photoetching auxiliary layer and a photoresist on the surfaces of the second sacrificial layer and the protective layer;
and forming a patterned second photoresist layer after exposing and developing the photoresist.
6. The method as claimed in claim 5, wherein the step of transferring the pattern of the second photoresist layer to the second sacrificial layer and the protective layer of the first region comprises:
etching the photoetching auxiliary layer, the protective layer and the second sacrificial layer by taking the patterned second photoresist layer as a mask, and transferring the pattern of the second photoresist layer to the second sacrificial layer and the protective layer of the first region;
and removing the second photoresist layer and the photoetching auxiliary layer.
7. The method as claimed in claim 5, wherein the lithography auxiliary layer comprises at least one of an organic dielectric material layer, an anti-reflection layer, a deep ultraviolet light absorbing silicon oxide layer, an amorphous carbon layer, a silicon oxide layer, or a phosphosilicate glass layer.
8. The method as claimed in claim 2, wherein the material of the second sidewall spacers comprises at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
9. The method for forming the semiconductor structure according to claim 2, wherein the thickness of the second sidewall is 10nm to 25 nm.
10. The method of claim 1, wherein the first mask layer comprises at least one insulating layer.
11. The method of claim 10, wherein a material of the insulating layer comprises at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
CN202010492479.0A 2020-06-03 2020-06-03 Semiconductor structure and forming method thereof Pending CN113764274A (en)

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Citations (4)

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US20150093899A1 (en) * 2013-09-30 2015-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Manufacturing Methods
CN109559978A (en) * 2017-09-27 2019-04-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US10304744B1 (en) * 2018-05-15 2019-05-28 International Business Machines Corporation Inverse tone direct print EUV lithography enabled by selective material deposition
CN109817527A (en) * 2017-11-21 2019-05-28 台湾积体电路制造股份有限公司 Manufacture the method and its structure of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150093899A1 (en) * 2013-09-30 2015-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Manufacturing Methods
CN109559978A (en) * 2017-09-27 2019-04-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109817527A (en) * 2017-11-21 2019-05-28 台湾积体电路制造股份有限公司 Manufacture the method and its structure of semiconductor device
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