KR20060113162A - Method of forming patterns for semiconductor device - Google Patents

Abstract

A method for forming a pattern of a semiconductor device is provided to simplify processes by forming simultaneously a periphery and a core pattern of various sizes and a cell pattern using an improved hard mask pattern. A first hard mask pattern(22a) is formed on a substrate(10) having an etch target layer(12). A sacrificial pattern is formed on the etch target layer. A spacer is formed at both sidewalls of the sacrificial pattern. A second hard mask pattern(24b) made of the spacer is then formed by selectively removing the sacrificial pattern. The etch target layer is then etched by using the first and the second hard mask pattern as a mask.

Description

Method of forming patterns for semiconductor device

1A to 1E are plan views sequentially illustrating a process of simultaneously forming a pattern of a ferry core region of a semiconductor device and a pattern of a cell region according to the present invention.

2A to 2H are cross-sectional views sequentially illustrating a process of simultaneously forming a pattern of a ferry-core region of a semiconductor device with a pattern of a cell region according to the present invention.

3A to 3H are plan views sequentially illustrating a process of forming a gate pattern according to the contents of the present invention.

4A through 4H are cross-sectional views sequentially illustrating a process of forming a gate pattern according to the present disclosure.

<Explanation of symbols for the main parts of the drawings>

10, 10 ': substrate 12: etched film

12 ', 12a': polysilicon film 13 ', 13a': tungsten silicide film

14a ': Gate pattern 22: First hard mask film

22a, 22a ': first hard mask pattern 24: second hard mask film

22 ', 24': silicon nitride film 24a, 24a ': spacer

24b, 24b ': second hardmask pattern 34, 34': sacrificial film

34a, 34a ': sacrificial patterns 42, 44, 42', 44 ', 46': photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of simultaneously forming a fine pattern outside the resolution limit of an exposure apparatus and a large pattern within the resolution limit.

As the degree of integration of semiconductor devices increases, design rules continue to decrease. As the speed of reduction of design rules is faster than the development speed of exposure equipment, patterning processes using spacer hard masks are used to form patterns smaller than the patterns within the resolution limits of the exposure equipment. In this step, a hard mask pattern made of a spacer is formed. Since the size of the hard mask pattern corresponds to the thickness of the spacer, it is possible to form a fine pattern beyond the resolution of the exposure apparatus by making the deposition thickness of the hard mask film thin. However, in the patterning process using the spacers, only patterns having the same size corresponding to the thickness of the spacers may be formed, thereby forming patterns having different sizes. Therefore, although it is advantageous to form a repeating fine pattern of the cell region, it is difficult to form patterns of various shapes and sizes of the ferry core region. In addition, even in the pattern of the cell region, it is difficult to simultaneously form a minute pattern having a constant pitch and a pattern having a different shape and size.

 It is an object of the present invention to provide a method for simultaneously forming a repeating fine pattern of a cell region and a pattern having various shapes and sizes of a ferry core region. In addition, the present invention provides a method of simultaneously forming a fine pattern that is repeated even in a pattern of the same cell region and a pattern having a different shape and size.

 In order to achieve the above object, the present invention forms a first hard mask pattern made of a first hard mask film on an etched film on a semiconductor substrate. A sacrificial pattern is formed on the etched film on which the first hard mask pattern is formed. A spacer including a second hard mask layer is formed around the first hard mask pattern and the sacrificial pattern. The sacrificial pattern may be selectively removed to form a second hard mask pattern including a spacer on the etched film. The etching target layer is etched using the first hard mask pattern and the second hard mask pattern as an etching mask to form a pattern of a semiconductor device.

The first hard mask pattern may define a pattern having various shapes and sizes of a ferry core or a cell region, and the second hard mask pattern may define a minute fine pattern of the cell region.

 An etching prevention layer may be formed between the etching target layer and the first hard mask layer to prevent the etching target layer from being etched when the first hard mask layer is etched.

According to the present invention, a repeating fine pattern of the cell region and a pattern having various shapes and sizes of the ferry core region can be simultaneously formed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the size or thickness of the film or regions in the drawings is exaggerated for clarity of the specification, elements denoted by the same reference numerals in the drawings means the same element.

1A to 1E and 2A to 2H illustrate a method of simultaneously forming a pattern having various shapes and sizes of a ferry core or cell region and a repeating fine pattern of the cell region according to the present invention. It is a top view and sectional drawing which showed the process in order.

1A is a plan view showing a photoresist pattern 42 formed to define a first hard mask pattern. As shown in FIG. 1A, the first hard mask pattern is used to define a pattern different from the repeated fine pattern among the pattern of the ferry core region and the pattern of the cell region. FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1A. FIG.

Referring to FIG. 2A, a photoresist for forming a first hard mask film 22 on the etched film 12 on the semiconductor substrate 10 and defining a first hard mask pattern on the first hard mask film 22. The pattern 42 is formed.

The etched film 12 and the first hard mask layer 22 may have different materials depending on the use of the pattern and the process plan.

For example, when forming an active pattern of a semiconductor device, a silicon nitride hard mask may be used as the first hard mask layer 22, in which case the etch layer 12 may be a pad silicon oxide or a silicon substrate. Can be. Alternatively, when the silicon nitride hard mask pattern is formed using a poly silicon hard mask, the first hard mask layer 22 may be polysilicon, and the etching target layer 12 may be silicon nitride.

In addition, in the process of forming a gate pattern, the etched film 12 may be a conductive layer such as polysilicon, tungsten silicide, tungsten, cobalt silicide, or a stacked structure thereof. In this case, the first hard mask film 22 may be formed. ) May use a silicon nitride film.

FIG. 2B is a cross-sectional view illustrating a process of forming the first hard mask pattern 22a by etching the first hard mask layer 22 using the photoresist pattern 42 as an etching mask. As described above, the first hard mask pattern 22a is a hard mask pattern for defining a pattern different from the repeated fine pattern among the pattern of the ferry core or the pattern of the cell region. For example, the first hard mask pattern 22a may be used to widen a predetermined portion of the repeated fine pattern of the cell region to have an area where a contact can be formed in a subsequent process. In order to prevent the etched film 12 from being etched when the first hard mask layer 22 for forming the first hard mask pattern 22a is etched, the etched film 12 and the first hard mask film ( It is also possible to use an anti-etching film in between.

FIG. 1B is a plan view illustrating a photoresist pattern 44 for defining a sacrificial pattern that is subjected to an intermediate process to form a second hard mask pattern. The second hard mask pattern is for defining a repeated fine pattern of a cell region and a fine pattern of a ferry core region. FIG. 2C is a cross-sectional view taken along the line II ′ of FIG. 1B. FIG.

1B and 2C, a photoresist pattern is formed on the etched film 12 on which the first hard mask pattern 22a is formed, and a sacrificial pattern is defined on the sacrificial film 34. Form 44.

The sacrificial layer 34 does not require a planarization process by using a thin film having excellent flatness such as spin on glass (SOG) silicon oxide. Since the sacrificial layer 34 is removed during the patterning process using a spacer, a layer having an etching selectivity with the first hard mask layer 22 is used.

When the first hard mask layer 22 is silicon nitride, the sacrificial layer 34 may use silicon oxide. When the first hard mask layer 22 is polysilicon, the sacrificial layer 34 may be formed of silicon nitride. Silver silicon oxide or silicon nitride can be used. When the first hard mask layer 22 is silicon oxide, the sacrificial layer 34 may use silicon nitride. However, depending on the material of the etched film 12, a restriction may be applied to the material of the first hard mask film 22 and the sacrificial film 34.

FIG. 1C is a plan view illustrating a step in which the first hard mask pattern 22a and the sacrificial pattern 34a are formed on the etched film 12. FIG. 2D is a cross-sectional view taken along the line II ′ of FIG. 1C. FIG.

Referring to FIG. 2D, the sacrificial layer 34 is etched using the photoresist pattern 44 as a mask to form a sacrificial pattern 34a. Since the first hard mask layer 22 has an etching selectivity with respect to the sacrificial layer 34, the first hard mask pattern 22a is not attacked by the etching of the sacrificial layer 34. Therefore, after the sacrificial layer 34 is etched, the first hard mask pattern 22a and the sacrificial pattern 34a exist on the etched layer 12.

The pitch 2P of the sacrificial pattern 34a shown in FIGS. 1C and 2D is twice the pitch P of the fine pattern to be formed. This is a pattern that a hard mask pattern in the form of a spacer to be formed around the sacrificial pattern 34a is actually formed, and since the spacer is formed twice as much as the sacrificial pattern 34a, the pitch of the sacrificial pattern 34a is increased. This is because the stem is cut in half.

In the active pattern forming process, when the sacrificial pattern 34a is formed using the silicon nitride as the first hard mask layer 22 and the silicon oxide as the sacrificial layer 24, the sacrificial layer 24 is partially etched to form the sacrificial pattern 34a. When etching the film 34, the etching target film 12 made of pad silicon oxide underneath is not removed. The sacrificial layer 34 remaining between the sacrificial patterns 34a may be removed when the sacrificial pattern 34a is removed after the second hard mask pattern is formed. As described above, a SiON film may be used as an anti-etching film on the pad silicon oxide.

Referring to FIG. 2E, a second hard mask layer 24 is formed on the etched layer 12 on which the first hard mask pattern 22a and the sacrificial pattern 34a are formed. The second hard mask layer 24 may be formed around the sacrificial pattern 34a to form a spacer. The second hard mask layer 24 may be formed of the same material as the first hard mask layer 22. In addition, a film having good step coverage such as thermal silicon nitride or thermal silicon oxide, undoped silicon glass (USG), atomic layer deposition (ALD) is used.

1D is a plan view illustrating a step in which spacers 24a are formed around the sacrificial pattern 34a. FIG. 2F is a cross-sectional view taken along the line II ′ of FIG. 1D. FIG.

Referring to FIGS. 1D and 2F, the first hard mask pattern 22a and the second hard mask layer 24 formed on the sacrificial pattern 34a are anisotropically etched to form the first hard mask pattern 22a. Spacers 24a are formed around the sacrificial pattern 34a. The spacer 24a formed around the sacrificial pattern 34a corresponds to the second hard mask pattern for providing a fine pattern.

FIG. 1E is a plan view illustrating a process of forming a first hard mask pattern 22a and a second hard mask pattern 24b on the etched film 12. 2G is a cross-sectional view taken along the line II ′ of FIG. 1E.

1E and 2G, the sacrificial pattern 34a may be selectively removed by dry etching or wet etching to form the first hard mask pattern 22a and the second hard mask pattern on the etched film 12. Leave (24b). As described above, the first hard mask pattern 22a defines a pattern different from the repeated fine pattern among the pattern of the ferry core or the cell region, and the second hard mask pattern 24b repeats the cell region. It is to define a fine pattern.

The pitch P of the second hard mask pattern 24b is half of the pitch 2P of the sacrificial pattern 34a removed as described above. The size of the second hard mask pattern 24b may be determined by adjusting the thickness of the second hard mask layer 24, and the space of the second hard mask pattern 24b is formed by removing the sacrificial pattern 34a. Therefore, the pitch and size of the sacrificial pattern 34a may be adjusted.

Referring to FIG. 2H, the etching target film 12 is etched using the first hard mask pattern 22a and the second hard mask pattern 24b as a mask to form the etching pattern 12a. The etched pattern 12a may be various patterns required for a semiconductor device, and an active pattern or a gate pattern may correspond to the pattern.

 3A to 3H and 4A to 4H simultaneously form gate patterns of various shapes and sizes of ferry, core, or cell regions and repeating fine gate patterns of cell regions in a gate patterning process according to the present invention. In order to explain the method, a plan view and a cross-sectional view showing the process in order.

 3A is a plan view showing a photoresist pattern 42 'formed to define a gate pattern larger than a repeating fine gate pattern among gate patterns in a cell. 4A is a cross-sectional view taken along the line II ′ of FIG. 3A.

3A and 4A, a silicon nitride film 22 'serving as a first hard mask film is formed on a gate conductive layer including a polysilicon film 12' and a tungsten silicide film 13 '. The photoresist pattern 42 'is formed on the nitride film 22'.

4B is a cross-sectional view illustrating a step of forming the first hard mask pattern 22a 'by etching the silicon nitride layer 22' using the photoresist pattern 42 'as an etching mask. As described above, the first hard mask pattern 22a ′ is a hard mask pattern for defining a gate pattern larger than the repeated fine gate pattern among the gate patterns in the cell.

3B is a plan view illustrating a photoresist pattern 44 ′ for defining a sacrificial pattern that is subjected to an intermediate process to form a second hard mask pattern. The second hard mask pattern is to define a repeating fine gate pattern of the cell region. 4C is a cross-sectional view taken along the line II ′ of FIG. 3B.

3B and 4C, a silicon oxide sacrificial layer 34 ′ is formed on the tungsten silicide layer 13 ′ on which the first hard mask pattern 22a ′ is formed, and the silicon oxide sacrificial layer 34 ′ is formed. A photoresist pattern 44 'defining a sacrificial pattern is formed thereon.

3C is a plan view illustrating a step in which the first hard mask pattern 22a 'and the sacrificial pattern 34a' are formed on the tungsten silicide layer 13 '. 4D is a cross-sectional view taken along the line II ′ of FIG. 3C.

Referring to FIG. 4D, the sacrificial pattern 34a ′ is formed by etching the silicon oxide sacrificial layer 34 ′ using the photoresist pattern 44 ′ as a mask. Then, the first hard mask pattern 22a 'and the sacrificial pattern 34a' are present on the tungsten silicide layer 13 '.

Referring to FIG. 4E, a silicon nitride layer 24 ′ as a second hard mask layer is formed on the tungsten silicide layer 13 ′ on which the first hard mask pattern 22 a ′ and the sacrificial pattern 34 a ′ are formed. do. The silicon nitride layer 24 'is used to form a spacer around the sacrificial pattern 34a'.

3D is a plan view illustrating a step in which spacers 24a 'are formed around the sacrificial pattern 34a'. 4F is a cross-sectional view taken along the line II ′ of FIG. 3D.

3D and 4F, the first hard mask pattern 22a is anisotropically etched on the first hard mask pattern 22a 'and the sacrificial pattern 34a'. And a spacer 24a 'is formed around the sacrificial pattern 34a'. The spacer 24a 'formed around the sacrificial pattern 34a' corresponds to the second hard mask pattern for providing a fine gate pattern repeated in the cell.

3E is a plan view illustrating a step of forming the first hard mask pattern 22a 'and the second hard mask pattern 24b' made of silicon nitride on the tungsten silicide layer 13 '. 4G is a cross-sectional view taken along the line II ′ of FIG. 3E.

3E and 4G, the sacrificial pattern 34a 'is selectively removed by dry etching or wet etching to form the first hard mask pattern 22a' and the first hard mask on the tungsten silicide layer 13 '. 2 Leave the hard mask pattern 24b '. As described above, the first hard mask pattern 22a 'defines a gate pattern larger than the repeated fine gate pattern among the gate patterns in the cell, and the second hard mask pattern 24b' is repeated in the cell region. To define a fine gate pattern.

3F and 4H, the tungsten silicide layer 13 ′ and the polysilicon layer 12 ′ are formed using the first hard mask pattern 22 a ′ and the second hard mask pattern 24 b ′ as masks. ) Is etched to form a gate pattern 14a 'formed by stacking the tungsten silicide layer 13a' and the polysilicon layer 12a '.

As shown in FIG. 3F, the gate pattern 14 ′ formed by the second hard mask pattern 24 a ′ is formed in a spacer manner and is connected to each other by two lines. 3G is a plan view illustrating a step of forming a photoresist mask 46 'on the gate pattern 14' so as to separate the gate patterns 14 'connected to each other.

FIG. 3H shows a gate line pattern separated by etching and removing an edge of the gate pattern 14 ′ using the photoresist mask 46 ′.

As described above, according to the present invention, when a minute gate pattern is repeated in a cell using a spacer, gate patterns having different shapes and sizes in the cell and various gate patterns of the ferry core can be simultaneously formed.

In addition, the present invention may be used not only to form a pattern of a cell and a ferry core, but also to form various patterns of other regions of an embedded device.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, A deformation | transformation and improvement are possible by the person skilled in the art within the technical idea of this invention.

 In the method for forming a pattern of a semiconductor device according to the present invention, a hard mask is formed on the etched film to define a repeated fine pattern of the cell region and a pattern having various shapes and sizes of the ferry core region. By etching the etched film using the hard mask thus formed, the ferrite core pattern and the cell pattern of various shapes and sizes can be simultaneously formed, thereby simplifying the process.

Claims (10)

 Forming a first hard mask pattern including a first hard mask layer on the etched film on the semiconductor substrate; Forming a sacrificial pattern on the etched film on which the first hard mask pattern is formed; Forming a spacer including a second hard mask layer around the first hard mask pattern and the sacrificial pattern; Selectively removing the sacrificial pattern to form a second hard mask pattern formed of the spacer on the etched film; And And etching the etching target film using the first hard mask pattern and the second hard mask pattern as an etching mask.  The method of claim 1, wherein the first hard mask pattern defines a pattern of various shapes and sizes of the ferry core or the cell region, and the second hard mask pattern defines a repeating fine pattern of the cell region. The pattern formation method of a semiconductor element.  The method of claim 1, wherein the first hard mask pattern is defined to widen a predetermined portion of a repeating fine pattern of the cell region to have an area where a contact can be formed in a subsequent process, and the second hard mask pattern is a cell A pattern forming method for a semiconductor device, comprising defining a repeating fine pattern of a region.  The method of claim 1, wherein the first hard mask pattern defines a gate pattern larger than the repeated fine gate pattern of the cell region, and the second hard mask pattern defines a repeated fine gate pattern of the cell region. The pattern formation method of a semiconductor element.  The method of claim 1, further comprising forming an etch stop layer between the etched layer and the first hard mask layer.  The method of claim 1, wherein the first hard mask layer is formed of a silicon nitride based or polysilicon based film.  The method of claim 1, wherein the sacrificial layer is formed of a silicon oxide layer.  2. The method of claim 1, wherein the second hard mask film is formed of the same film as the first hard mask film.  The method of claim 1, wherein the second hard mask film is formed of a thermal silicon nitride film having high step coverage.  The semiconductor device of claim 1, wherein the first hard mask film and the second hard mask film are formed of a thermal silicon oxide film having high step coverage, and the sacrificial film is formed of a silicon nitride based film. Pattern formation method.

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