CN109559978A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN109559978A
CN109559978A CN201710889671.1A CN201710889671A CN109559978A CN 109559978 A CN109559978 A CN 109559978A CN 201710889671 A CN201710889671 A CN 201710889671A CN 109559978 A CN109559978 A CN 109559978A
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layer
area
graph
forming method
mask
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CN109559978B (en
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陈卓凡
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

The present invention provides a kind of semiconductor structure and forming method thereof, wherein method includes: the formation initial power ergosphere on first area and second area substrate；Original mask layer is formed on the initial power ergosphere；Multiple the first discrete graph layers are formed on the first area original mask layer, second graph floor is formed in removal area and reserved area original mask floor respectively, first graph layer is first size along the size of the first direction, the second graph layer is the second size along the size of the first direction, second size is equal to first size, and the spacing between adjacent first graph layer is equal with the spacing between adjacent second graph layer；Pattern transfer processing is carried out, multiple mask layers are formed.The forming method can improve formed semiconductor structure performance, and being capable of simplification of flowsheet.

Description

Semiconductor structure and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, the direction of semiconductor devices towards high density, high integration is developed. In order to reduce the size of semiconductor devices, the integrated level of semiconductor devices is improved, the prior art has developed multiple graphical technique, Including Dual graphing technique, triple patterning process and quadruple patterning process.
Dual graphing technique can effectively reduce the difficulty of production small size figure, have in forming small size figure There is important application.Dual graphing technique includes self-alignment type double exposure (SADP) technology, secondarily etched double-pattern (DEDP) technology and single etching Dual graphing technology.
With the raising of semiconductor devices integrated level, when the density difference of different zones figure on the same chip, lead to The performance for crossing the semiconductor structure of Dual graphing technique formation is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can improve formed semiconductor The performance of structure.
To solve the above problems, technical solution of the present invention provides a kind of forming method of semiconductor structure, comprising: provide lining Bottom, the substrate include first area and second area, and the second area includes mutually discrete and alternately arranged removal area And reserved area, the orientation of the removal area and reserved area are first direction；In the first area and second area substrate Upper formation initial power ergosphere；Original mask layer is formed on the initial power ergosphere；On the first area original mask layer Multiple the first discrete graph layers are formed, form second graph floor in removal area and reserved area original mask floor respectively, it is described First graph layer is first size along the size of the first direction, and the second graph layer is along the size of the first direction Second size, second size are equal to first size, the spacing and adjacent second graph layer between adjacent first graph layer it Between spacing it is equal；Form the covering reserved area second graph layer side wall widens layer；Layer, the first graph layer are widened with described It is that exposure mask performs etching the original mask layer with second graph layer, forms mask layer；It is exposure mask to institute using the mask layer It states initial power ergosphere to perform etching, forms functional layer；Remove the functional layer in the removal area.
Optionally, the step of forming first graph layer and second graph layer includes: in the first area and second Multiple discrete core layers are respectively formed on the original mask layer of region, the spacing between the core layer of adjacent first regions with it is adjacent Spacing between second area core layer is equal, and first area core layer is third size, institute along the size of the first direction It is the 4th size that second area core layer, which is stated, along the size of the first direction, and the third size is equal to the 4th size；Institute It states at the top of core layer and forms initial graphics layer on side wall and the original mask layer；The initial graphics layer is carried out each Anisotropy etching, removes the initial graphics layer at the top of the original mask layer and the core layer, in the first area shape Second graph floor is formed at multiple the first discrete graph layers, and in the removal area and reserved area；The anisotropic etching Later, the core layer is removed.
Optionally, it is formed before the core layer, further includes: stop-layer is formed on the original mask layer, it is described to stop Only the material of layer is not identical as the material of the core layer；It is formed after the mask layer, further includes: remove on the mask layer Stop-layer.
Optionally, the step of widening described in formation layer includes: in the original mask layer, first graph layer and second The first flatness layer is formed on graph layer, the first flat layer surface is higher than at the top of first graph layer and second graph layer； Patterned first photoresist is formed on first flatness layer, the guarantor is completely covered in patterned first photoresist It stays at the top of area's second graph floor, and along first direction, the size of first photoresist is greater than second figure of reserved area The size of shape layer；First flatness layer is performed etching using first photoresist as exposure mask, layer is widened described in formation.
Optionally, the material of first flatness layer is organic dielectric material.
Optionally, the step of widening described in formation layer includes: to form covering first graph layer and second graph layer side Wall initially widens layer, and the material for initially widening layer is photoresist；It initially widens layer to described and is exposed processing, go Layer is initially widened except the first area, layer is widened in formation.
Optionally, before removal removal area functional layer, further includes: on the first area and second area substrate Protective layer is formed, the protective layer covers the functional layer side wall, and exposes at the top of removal area functional layer.
Optionally, the step of forming the protective layer includes: to be formed just on the first area and second area substrate Beginning protective layer, the initial protective layers cover the functional layer side wall and top；It is flat that first is carried out to the initial protective layers Change processing, removes the initial protective layers in the functional layer, forms protective layer.
Optionally, after removal removal area functional layer, further includes: remove the protective layer.
Optionally, after removing the protective layer, further includes: initial medium layer is formed over the substrate, it is described initial Dielectric layer covers the functional layer side wall and top；Second planarization process is carried out to the initial medium layer, removes the function Initial medium layer at the top of ergosphere forms dielectric layer；The functional layer is removed, forms the first opening in the dielectric layer； Gate structure is formed in first opening.
Optionally, the material of the initial protective layers is silica or titanium oxide；The technique for forming the initial protective layers Including fluid chemistry gas-phase deposition.
Optionally, after removing removal area functional layer, groove is formed in the protective layer；The forming method is also It include: to form separation layer in the trench.
Optionally, the first area includes functional areas and blank area；The forming method further include: remove the blank The functional layer in area；The blank area functional layer and removal area functional layer are removed by same technique.
Optionally, there is the first side wall, the first side wall is contacted with adjacent first graph layer, institute between adjacent first graph layer It states the first side wall and the first adjacent graph layer forms ring structure；Between adjacent second graph layer have the second side wall, second Side wall is contacted with adjacent second graph layer, and the second side wall and adjacent second graph layer form ring structure；To the original mask The step of layer performs etching forms the first connection in first area respectively also using first side wall and the second side wall as exposure mask Layer forms the second articulamentum in second area, and first articulamentum both ends are contacted with the first adjacent graph layer respectively, described Second articulamentum both ends are contacted with adjacent second graph layer respectively；Before being performed etching to the initial power ergosphere, further includes: Remove first articulamentum and the second articulamentum.
Optionally, the mask layer is long strip type, is second direction perpendicular to the direction that the mask layer extends；Form function Before ergosphere, further includes: processing is patterned to the mask layer, forms the second opening in the mask layer, described the Two openings run through the mask layer in this second direction, and the second direction falls in the mask layer extending direction；Removal The step of first articulamentum and the second articulamentum and the graphical treatment includes: to the mask layer, the first connection Layer and the second articulamentum perform etching, and remove first articulamentum and the second articulamentum and form second in mask layer and open Mouthful, second opening runs through the mask layer in this second direction.
Optionally, the number of functional layer is single or multiple in the removal area.
Optionally, the material of the functional layer is polysilicon, polycrystalline germanium, polycrystalline silicon germanium, aluminium, tungsten or copper aluminium.
Optionally, the distance between adjacent first regions functional layer center is 50nm~60nm；Function in adjacent second zone The distance between ergosphere center is 100nm~120nm；The first area functional layer along first direction size be 6nm~ 8nm；The reserved area functional layer is 12nm~16nm along the size of first direction.
It optionally, include: etching by the technological parameter that exposure mask performs etching the initial power ergosphere of the mask layer Gas includes CF4、CHF3、CH2F2、CH3F、SF6、HBr、Cl2、O2、N2One of or multiple combinations, etching gas flow be 10sccm~500sccm, diluent gas include He and Ar, and the flow of He is 100sccm~1000sccm, and the flow of Ar is 100sccm~1000sccm；RF source power is 200~2000 watts；Bias drop is 100V~1000V；Etch period is 20s ~60s.
Technical solution of the present invention provides a kind of semiconductor structure that the forming method by above-mentioned semiconductor structure is formed.
Technical solution of the present invention also provides a kind of semiconductor structure formed by above-mentioned forming method.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor structure that technical solution of the present invention provides, on the original mask layer of the first area With the first graph layer, second graph floor, second size are all had on the original mask floor of the removal area and reserved area Equal to first size, and the spacing between the spacing between adjacent first graph layer and adjacent second graph layer is equal, then described First graph layer is identical with the pattern density of second graph layer.It is to cover with layer, the first graph layer and the second graph layer widened After film performs etching the original mask layer, the first area mask layer of formation and the pattern density of second area mask layer It is identical.Therefore, during being performed etching to the initial power ergosphere, the Elementary Function of the first area and second area The etch rate of layer is close, and before first area initial power ergosphere exposes substrate, the second area substrate is not easy sudden and violent Expose, so that the second area substrate is not easy to be etched when first area initial power ergosphere exposes substrate, thus The loss to the second area substrate can be reduced.Secondly, forming covering institute before performing etching to the original mask layer State the layer of widening of reserved area second graph layer side wall, it is described widen layer and can guarantee that the width of the reserved area functional layer meets set Meter requires, to make performance of the reserved area functional layer with design requirement.In addition, the first distance be equal to second away from From the spacing between adjacent first graph layer is identical as the spacing between adjacent second graph layer, first graph layer and Two graph layers can be formed by same technique, so as to simplification of flowsheet, save the process cost, and first figure Layer and second graph layer can be formed by same light shield, so as to save the process cost.
Further, due between the spacing between the core layer of adjacent first regions and adjacent second zone core layer Away from identical, the distance between adjacent first regions center core layer is equal to the distance between adjacent second zone center core layer, The first area can be formed with second area core layer by same technique, being capable of simplification of flowsheet.In addition, described One region core layer can use same light shield with second area core layer and be formed.Therefore, the forming method can save light Cover reduces process costs.
Further, since the spacing of the first area and the core layer of second area is equal, and first area and second The width of region core layer is equal, during etching removes the initial graphics layer on the original mask layer, described first Region is identical with the removal rate of second area initial graphics layer.Therefore, the initial graphics on the original mask layer are being removed During layer, it is not easy to the second area stop-layer is damaged, so as to make first area and second area stop-layer Thickness is identical.Since the thickness of the first area and second area stop-layer is equal, during removing the stop-layer, The stop-layer of the first area and second area can be removed substantially simultaneously, to be not easy to make second area original mask layer quilt Etching, so as to reduce the loss of second area mask layer, keeps the thickness of first area and second area mask layer equal, into And it is not easy to influence subsequent technique.The forming method can improve the performance of formed semiconductor structure.
Further, before removing removal area functional layer, protective layer is formed over the substrate.Removing the removal During area's functional layer, the protective layer can substrate between defencive function layer, to reduce substrate between functional layer Loss, and then the performance of formed semiconductor structure can be improved.
Further, the initial protective layers are formed by fluid chemistry gas-phase deposition.Since fluid chemistry gas phase is heavy The filling capacity for the initial protective layers that product technique is formed is good, the gap between functional layer can be sufficient filling with, so as to abundant The substrate between the functional layer is protected, the performance for being formed by semiconductor structure is improved.
Further, the first area includes blank area.The blank area and the removal area are removed by same technique Functional layer, can simplification of flowsheet, save the cost.
Detailed description of the invention
Fig. 1 to Fig. 6 is a kind of structural schematic diagram that each step of semiconductor structure is formed by Dual graphing technique；
Fig. 7 to Figure 24 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the invention.
Specific embodiment
There are problems for the forming method of semiconductor structure, such as: the performance for being formed by semiconductor structure is poor.
Now in conjunction with the forming method of semiconductor structure, analysis is now formed by the poor reason of performance of semiconductor structure:
Substrate is provided, the substrate includes first area and second area；In the first area and second area substrate Upper formation dummy gate layer；Multiple the first discrete graph layers are formed in the dummy gate layer；In the second area dummy grid Second graph layer is formed on layer；The distance between adjacent second graph layer center is more than or equal to distance between adjacent first graph layer Twice；The dummy gate layer is performed etching using first graph layer and second graph layer as exposure mask, forms dummy grid.
Wherein, in order to meet design requirement, the distance between adjacent second graph layer center is greater than adjacent first graph layer The distance between center, then the depth-to-width ratio in gap is smaller between second graph layer, during etching the dummy gate layer, institute The etch rate for stating second area dummy gate layer is larger.Before the first area dummy gate layer exposes the substrate, institute It states second area substrate to be just exposed, therefore when the dummy gate layer of the first area exposes the first area substrate When, the substrate of the second area is easy to be etched, and causes second area substrate loss larger, to influence formed semiconductor The performance of structure.
For the damage of substrate, technical field of semiconductors proposes a kind of method as shown in Figures 1 to 6.
Fig. 1 to Fig. 6 is a kind of each step structural schematic diagram that semiconductor structure is formed by Dual graphing technique.
Referring to FIG. 1, providing substrate 100, the substrate 100 includes first area A and second area B；Described first Dummy gate layer 110 is formed on region A and second area B substrate 200；Original mask layer is formed in the dummy gate layer 110 101；Stop-layer 120 is formed on the original mask layer 101；It is formed on the first area A stop-layer 120 multiple discrete Core layer 102；Side is formed on 102 top of core layer and sidewall surfaces and the first area A stop-layer 120 Wall layers 130.
Referring to FIG. 2, carrying out anisotropic etching to the side wall layer 130, the core layer 102 and the stopping are removed Side wall layer 130 on layer 120 forms side wall 131；It is formed after side wall 131, removes the core layer 102 (as shown in Figure 1).
Referring to FIG. 3, after removing the core layer 102；The first flatness layer 132, institute are formed on the stop-layer 120 It states the first flatness layer 132 and covers 131 side wall of side wall and top；It is formed on the first flatness layer 132 of the second area B Patterned first photoresist 143.
Referring to FIG. 4, being exposure mask to the stopping with first photoresist 143 and the side wall 131 (please referring to Fig. 3) 120 (as shown in Figure 3) of layer perform etching, and form graph layer 121；The second flatness layer is formed on the original mask layer 101 150, second flatness layer 150 covers 121 top of graph layer and side wall；In second flatness layer of second area B 150 It is upper to form patterned second photoresist 141；The midpoint of 121 line of centres of adjacent second zone B graph layer is located at described second On 141 center line of photoresist.
Referring to FIG. 5, (as shown in Figure 4) for exposure mask with the graph layer 121 (as shown in Figure 4) and the second photoresist 141 The original mask layer 101 is performed etching, mask layer 104 is formed；It is exposure mask to the dummy gate layer with the mask layer 104 110 perform etching, and form dummy grid, and the dummy grid includes the first dummy grid 111 positioned at the first area A, are located at institute State the second dummy grid 112 and third dummy grid 113 of second area B, 113 phase of second dummy grid 112 and third dummy grid Mutually it is alternately arranged.
Referring to FIG. 6, removing the third dummy grid 113 (as shown in Figure 5)
Wherein, in order to meet design requirement, distance is about institute between 112 center of the second dummy grid of the second area B 2 times for stating the distance between 111 center of the first dummy grid of first area A, then between 111 center of the first dummy grid away from From equal to the distance between the second dummy grid 112 and 113 center of third dummy grid, therefore, the first area A mask layer 104 The distance between (as shown in Figure 5) center is equal with the distance between the second area B mask layer 104.Etching the puppet During grid layer 110, the pattern density of the first area A and second area B mask layer 104 is identical.First area A and Two region B mask layers, 104 pattern density is to first area A and second area B dummy gate layer 110 (as shown in Figure 4) etch rate Difference influences smaller.Therefore, during etching dummy gate layer 110, the forming method can reduce because of mask layer The loss of second area B substrate 100 caused by 104 pattern density difference.
However, due between 112 center of the second dummy grid of the second area B distance be about the first area A 2 times of the distance between first dummy grid, 111 center, and between the first dummy grid 111 of the first area A width with it is described The width of the second dummy grid of second area B 112 is not identical, then the spacing between the second dummy grid 112 and third dummy grid 113 compared with It is small, less than the spacing between adjacent first dummy grid 111.Due to the spacing between the second dummy grid 112 and third dummy grid 113 It is smaller, it is less than exposure accuracy, the first photoresist 143 and the second photoresist 143 is hardly formed by single exposure, needed by two Secondary exposure forms first photoresist 143 and the second photoresist 141, to need two light shields, therefore the forming method Light shield is increased, growth cost is improved.Secondly as the second photoresist 141 is not identical as the width of side wall 131, and first Photoresist 143 is not identical as the width of side wall 131, and therefore, the side wall 131 and the first photoresist, the second photoresist need to lead to Different technique is crossed to be formed.During carrying out anisotropic etching to the side wall layer 130, due to the second area B Without core layer 102, during etching side wall layer 130, etching gas is easy the side wall layer with second area B 130 contacts make the etch rate of the side wall layer 130 of the second area B be greater than the etch rate of first area A side wall layer 130, To be easy to cause when the side wall layer 130 on the first area stop-layer 120 exposes stop-layer 120, secondth area The stop-layer 120 of domain B is easy to be etched, and 120 thickness of second area B stop-layer is made to be less than the thickness of first area A stop-layer 120 Degree.Etch during the stop-layer 120 forms graph layer 121, the loss of the second area B original mask layer 101 compared with Greatly, after resulting in graph layer 121, the thickness of the second area B original mask layer 101 is less than first area A and initially covers The thickness of film layer 101.During etching the formation of original mask layer 101 mask layer 104, the second area B puppet grid The loss of pole layer 100 is larger, and after resulting in mask layer 104, the thickness of the second area B dummy gate layer 110 is less than the The thickness of one region A dummy gate layer 110.Finally during performing etching to form dummy grid to dummy gate layer 110, described Two region B substrates 100 are still easy to be damaged, and the performance so as to cause formed semiconductor structure is poor.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: in the firstth area Multiple the first discrete graph layers are formed on the original mask layer of domain, form the in removal area and reserved area original mask floor respectively The orientation of two graph layers, the second graph layer is identical as the first direction, and first graph layer is along described first The size in direction is first size, and the second graph layer is the second size, second ruler along the size of the first direction Very little to be equal to first size, the spacing between adjacent first graph layer is equal with the spacing between adjacent second graph layer.The shape Formed semiconductor structure performance can be improved at method, and being capable of simplification of flowsheet.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Fig. 7 to Figure 24 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 7, providing substrate 200, the substrate 200 includes first area M and second area N, secondth area Domain N includes mutually discrete and alternately arranged removal area N2 and reserved area N1, the arrangement side of removal the area N2 and reserved area N1 To for first direction.
In the present embodiment, the substrate 200 includes: substrate and the fin in the substrate.In other embodiments, The substrate can also be in planar substrate, such as silicon substrate, germanium substrate, silicon-Germanium substrate, silicon-on-insulator substrate or insulator The semiconductor substrates such as germanium substrate.
In the present embodiment, the material of the substrate and fin is silicon.In other embodiments, the material of the substrate and fin Material is germanium or SiGe.
In the present embodiment, the first area M includes functional areas M1 and blank area M2.
In the present embodiment, the functional areas M1 and blank area M2 are arranged along the first direction.In other embodiments, institute The orientation for stating functional areas and blank area can be pressed from both sides perpendicular to the first direction, or with the first direction with acute angle Angle.
In the present embodiment, the functional layer of the functional areas M1 needs to retain, to form the dummy grid of semiconductor devices.Institute The functional layer for stating blank area M2 subsequent needs to remove.
In other embodiments, the first area can not also include the blank area.
With continued reference to Fig. 7, initial power ergosphere 210 is formed on the first area M and second area N substrate 200.
In the present embodiment, the initial power ergosphere 210 is used to form the dummy grid in rear grid technique, then the Elementary Function The material of layer 210 is semiconductor material, such as polysilicon, polycrystalline germanium or polycrystalline silicon germanium.In other embodiments, the initial power Ergosphere is used to form metal interconnecting wires.The material of the initial power ergosphere is aluminium, tungsten or copper aluminium.
In this implementation, the step of forming initial power ergosphere 210 includes: chemical vapor deposition process.In other implementations In example, the material of the initial power ergosphere can also be aluminium, tungsten or copper aluminium, and the technique for forming the initial power ergosphere includes plating Technique or Metalorganic chemical vapor deposition technique or physical gas-phase deposition.
With continued reference to Fig. 7, original mask layer 201 is formed on the initial power ergosphere 210.
The original mask layer 201 is for being subsequently formed mask layer.
In the present embodiment, the material of the original mask layer 201 is silicon nitride.In other embodiments, described initially to cover The material of film layer can be silica or silicon oxynitride.
In the present embodiment, the forming method further include: stop-layer 202 is formed on the original mask layer 201.
The stop-layer 202 is for playing the role of etching stopping during subsequent etching initial graphics layer 270.
The stop-layer 202 is not identical as the material of the original mask layer 201, then in the subsequent removal stop-layer It is smaller to the removal rate of original mask layer 201 during 202, so that the subsequent functional layer that adequately protects, reduces functional layer Loss.
In the present embodiment, the material of the stop-layer 202 is silica.In other embodiments, the material of the stop-layer Material can also be silicon nitride or silicon oxynitride.
It is subsequent to form multiple the first discrete graph layers on the first area M original mask layer 201 respectively, exist respectively It removes and forms second graph floor on area N2 and reserved area N1 original mask floor 201, first graph layer is along the first direction Size be first size, the second graph layer along the first direction size be the second size, described second size etc. Spacing between first size, adjacent first graph layer is identical as the spacing between adjacent second graph layer.
It should be noted that having the first graph layer, the removal area N2 and reserved area N1 exposure mask on the first area M All have second graph layer on layer 204, and the first size is equal to the second size, the spacing between adjacent first graph layer with Spacing between adjacent second graph layer is equal, then first graph layer is identical with the pattern density of second graph layer.With institute Stating and widening layer, the first graph layer and second graph layer is after exposure mask performs etching the original mask layer the first of formation Region M mask layer is identical as the pattern density of second area N mask layer.Therefore, it is performed etching to the initial power ergosphere 210 During, the etch rate of the initial power ergosphere 210 of the first area M and second area N is close, at the beginning of the M of first area Before beginning functional layer 210 exposes substrate 200, the second area N substrate 200 is not easy to be exposed, thus when first When region M initial power ergosphere 210 exposes substrate 200, the second area N substrate 200 is not easy to be etched, so as to subtract The small loss to the second area N substrate 200.Before being performed etching to the original mask layer 201, is formed and cover the guarantor That stays area N1 second graph floor side wall widens floor.It is described widen layer and can guarantee that the width of the reserved area N1 functional layer is compound set Meter requires, so that making the functional layer of subsequent reserved area N1 has design requirement performance.In addition, first graph layer and the second figure Shape layer can be formed by same technique, so as to simplification of flowsheet, save the process cost.Secondly, first figure Layer and second graph layer can be formed by same light shield, so as to save the process cost.
In the present embodiment, the step of forming first graph layer and second graph layer, is as shown in Figure 8 and Figure 9.
Referring to FIG. 8, being respectively formed on the first area M and second area N original mask layer 201 multiple discrete Core layer 203, between the spacing and adjacent second zone N core layer 203 between the core layer 203 of adjacent first regions M between Away from identical, first area M core layer 203 is third size, the second area N core layer along the size of the first direction 203 along the first direction size be the 4th size, the third size be equal to the 4th size.
In the present embodiment, the core layer 203 is located on the stop-layer 202.
The step of forming core layer 203 includes: the formation incipient nucleus central layer on the stop-layer 202；Described first Patterned 4th photoresist is formed in beginning core layer；The incipient nucleus central layer is carved using the 4th photoresist as exposure mask Erosion forms core layer 203.
The step of forming patterned four photoresist includes: to provide the first light shield, is had in first light shield Mask graph；The 4th initial light photoresist is formed in the incipient nucleus central layer 203；By first light shield at the beginning of the described 4th Beginning photoresist is exposed processing, forms the 4th photoresist.
It should be noted that if the width of the mask graph in first light shield is not identical or adjacent mask figure Spacing between shape is not identical, in the exposure process, in the 4th photoresist caused by the interference and scattering of light It distorts larger, so that the size for being formed by the 4th photoresist is easy to cause to be difficult to control, and then is easy to influence to be formed partly to lead The performance of body structure.Therefore, the size of the mask graph in first light shield is identical with spacing.
Due between the spacing between the core layer 203 of adjacent first regions M and adjacent second zone N core layer 203 Spacing is identical, the distance between 203 center of adjacent first regions M core layer be equal to 203 center of adjacent second zone N core layer it Between distance, the first area M and second area N core layer 203 can be formed by same technique, can simplify technique stream Journey.In addition, the first area M core layer 203 and second area N core layer 203 can be formed by same light shield.Therefore, The forming method can save light shield, reduce process costs.
In the present embodiment, the material of the core layer 203 is indefinite form carbon.In other embodiments, the core layer Material can also be amorphous silicon or amorphous germanium.
Spacing between the width and adjacent core layer 203 of core layer 203 will affect between the graph layer being subsequently formed Spacing.In the present embodiment, the spacing between the first graph layer being subsequently formed is equal, and the spacing of second graph layer is equal, and Equal to the spacing between the first graph layer, then the spacing between the core layer 203 is equal to 203 width of core layer and is subsequently formed Initial graphics layer the sum of double thickness.
If the spacing between the width and adjacent core layer 203 of the core layer 203 is excessive or too small, it is easy to cause Spacing between the first graph layer 271 being subsequently formed and between second graph layer 272 is excessive or too small, to be easy shadow Ring the performance of formed semiconductor structure.Specifically, the width of the core layer 203 is 44nm~68nm in the present embodiment；Phase Spacing between adjacent core layer 203 is 56nm~68nm.
With continued reference to Fig. 8, formed on 203 top of core layer and side wall and the original mask layer 201 initial Graph layer 270.
The initial graphics layer 270 is for being subsequently formed the first graph layer and second graph layer.
In the present embodiment, the material of the initial graphics layer 270 is silicon nitride.In other embodiments, the initial graph The material of shape layer can also be silica or silicon oxynitride.
The thickness of the initial graphics layer 270 will affect the width for the mask layer being subsequently formed, and then influence to be subsequently formed First area M functional layer width.The thickness of the initial graphics layer 270 is excessive or too small, is easy to cause and is subsequently formed The width of functional layer is excessive or too small, and then is easy the performance for influencing to be formed by semiconductor structure.It is described first in the present embodiment Beginning graph layer 270 with a thickness of 6nm~8nm.
The technique for forming the initial graphics layer 270 includes chemical vapor deposition process, physical gas-phase deposition or original Sublayer depositing operation.
Referring to FIG. 9, carrying out anisotropic etching to the initial graphics layer 270, the original mask layer 201 is removed Initial graphics layer 270 at the top of the upper and described core layer 203 (as shown in figure 11), forms multiple points in the first area M The first vertical graph layer 271, and second graph floor 272 is formed in the removal area N1 and reserved area N2 respectively.
First graph layer 271 and second graph layer 272 are used as subsequent etching original mask layer, form mask layer 204 Exposure mask.
It should be noted that since the spacing of the core layer 203 of the first area M and second area N is equal, and first Region M and the thickness of second area N core layer 203 are equal, during etching initial graphics layer 270, described first Region M is identical with the etch rate of second area N initial graphics layer 270.Therefore, in the mistake for etching the initial graphics layer 270 Cheng Zhong, it is not easy to the second area N stop-layer 202 is damaged, so as to make first area M and second area N stop-layer 202 Thickness it is identical, and then be not easy influence subsequent technique.The forming method can improve the performance of formed semiconductor structure.
The anisotropic etching is less than longitudinal etch rate in lateral etch rate, can remove and described initially cover Initial graphics layer 270 in film layer 201 and at the top of the core layer 203.
In the present embodiment, the technique of the anisotropic etching includes anisotropic dry etch process.
The thickness of first graph layer 271 and second graph layer 272 determines by the thickness of the initial graphics layer 270, Then the thickness of first graph layer 271 and second graph layer 272 is equal with the thickness of initial graphics layer 270, specifically, described First graph layer 271 and second graph layer 272 with a thickness of 6nm~8nm.
It should be noted that since the initial graphics layer 270 (as shown in figure 11) is formed in the core layer 203 (such as Shown in Figure 11) four side walls and top and the original mask layer 201 (as shown in figure 11) on.The anisotropy is carved Etching off retains the four of the core layer 203 except the initial graphics layer 270 on 203 top of core layer and original mask layer 201 The initial graphics layer 270 of a sidewall surfaces forms multiple the first discrete graph layers 271 in the first area M, and adjacent first There is the first side wall between graph layer 271, the first side wall contacts with adjacent first graph layer 271, first side wall with it is adjacent The first graph layer 271 form ring structure, there is between adjacent second graph layer 272 second side wall, the second side wall with it is adjacent Second graph layer 272 contacts, and the second side wall and adjacent second graph layer 272 form ring structure.
It should be noted that the number for removing the second graph floor 272 of area N2 is one in the present embodiment.In other realities It applies in example, the number of the removal area N2 second graph floor 272 can be to be multiple, then multiple removal area N2 second graph floor 272 Orientation it is identical as the first direction.
With continued reference to Fig. 9, after the anisotropic etching, the core layer 203 (as shown in figure 11) is removed.
The technique for removing the core layer 203 includes: dry etch process or wet-etching technology.
Be subsequently formed covering 204 side wall of reserved area N1 mask layer widens layer.
The step of widening in the present embodiment, described in formation layer is as shown in Figure 10 to Figure 12.
Referring to FIG. 10, being formed on the original mask layer 201, first graph layer 271 and second graph layer 272 First flatness layer 220,220 surface of the first flatness layer are higher than 272 top of first graph layer 271 and second graph layer.
First flatness layer 220 widens layer for being subsequently formed, and 220 surface of the first flatness layer is flatter, from And the scattering of light can be reduced, and then scattering light can be reduced to the first photoetching during being subsequently formed the first photoresist The influence of glue.
The material of first flatness layer 220 is not identical as the material of the stop-layer 202, and it is flat can to reduce etching first Loss during smooth layer 220 to stop-layer 202.
The material of first flatness layer 220 is organic dielectric material, in other embodiments, the material of the flatness layer It can also be bottom anti-reflective material.
In the present embodiment, the technique for forming first flatness layer 220 includes spin coating proceeding.
Figure 11 is please referred to, forms the first anti-reflection coating 221 on first flatness layer 220.
First anti-reflection coating 221 is for absorbing the light reflected below the first anti-reflection coating 221, thus subsequent It is formed during the first photoresist 222, reduces influence of the reflected light to the first photoresist 222.
The material of first anti-reflection coating 221 is organic polymer.
The technique for forming first anti-reflection coating 221 includes spin coating proceeding.
1 is continued to refer to figure 1, forms patterned first photoresist 222, the figure on first flatness layer 220 The first photoresist 222 changed is completely covered at the top of the reserved area N1 second graph layer 271, and first photoresist 222 It is greater than the reserved area N1 second graph layer 272 along the size of first direction along the size of first direction.
Exposure mask of first photoresist 222 for the first flatness layer 220 described in subsequent etching.
In the present embodiment, first photoresist 222 is located in first anti-reflection coating 221.
The step of forming the first photoresist 222 includes: that first is formed in first anti-reflection coating 221 initially Photoresist；Processing is exposed to the first initial light photoresist, forms the first photoresist 222.
Please refer to Figure 12, with first photoresist 222 be exposure mask to first flatness layer 220 (as shown in figure 11) into Layer 212 is widened in row etching, formation.
The layer 212 of widening is for controlling the width for the reserved area N1 mask layer 204 being subsequently formed, thus to rear The width of the continuous reserved area N1 functional layer formed is controlled, and then makes performance of the reserved area N1 functional layer with design requirement.
The technique performed etching to first flatness layer 220 includes anisotropic dry etch process.Anisotropic dry The good directionality of method etching, and there is the control of good line width, it is easy to control the width to be formed and widen layer 212, so as to Accurately control the width for the mask layer being subsequently formed.In other embodiments, the technique first flatness layer performed etching Including isotropic dry etch technique or wet-etching technology.
It should be noted that the step of widening in other embodiments, described in formation layer includes: to form covering described first Graph layer and the initial of second graph layer side wall widen layer, and the material for initially widening layer is photoresist；To described initial It widens layer and is exposed processing, remove the first graph layer sidewall surfaces initially widens layer, and layer is widened in formation.
Figure 13 is please referred to, widens layer 212 (as shown in figure 12), the first graph layer 271 (as shown in figure 12) and with described Two graph layers 272 are (as shown in figure 12) to perform etching the original mask layer 201 (as shown in figure 12) for exposure mask, formation exposure mask Layer 204.
The mask layer 204 is used as the exposure mask of subsequent etching initial power ergosphere 210.
Since the layer 212 of widening is located at 272 sidewall surfaces of second graph layer, then layer 212, first is widened with described Graph layer 271 and second graph layer 272 are after exposure mask performs etching the original mask layer 201, and the reserved area N2 is covered The width of film layer is greater than the width of the second graph layer 272.
In the present embodiment, there is stop-layer 202 on the original mask layer 201.The original mask layer 201 is carved Before erosion, further includes: with it is described widen layer 212, the first graph layer 271 and second graph layer 272 be exposure mask to the stop-layer 221 perform etching, and expose the original mask layer 201.
In the present embodiment, the technique performed etching to the original mask layer 201 and stop-layer 202 includes anisotropic dry Method etching technics.The good directionality of anisotropic dry etching, and there is the control of good line width, it is easy to control formed exposure mask The width of layer 204, so as to accurately control the width for the functional layer being subsequently formed.In other embodiments, to described initial The technique that mask layer performs etching includes isotropic dry etch technique or wet-etching technology.
The mask layer 204 is strip, and the direction perpendicular to 204 extending direction of mask layer is second direction.This In embodiment, the second direction is parallel to the first direction.
It should be noted that (such as scheming since the initial graphics layer 270 (as shown in Figure 8) is formed in the core layer 203 Shown in 8) four side walls and top and the original mask layer 201 (as shown in Figure 8) on.The anisotropic etching is gone Except the initial graphics layer 270 on 203 top of core layer and original mask layer 201, retain four sides of the core layer 203 The initial graphics layer 270 of wall surface then forms multiple the first discrete graph layers 271, adjacent first figure in the first area M There is the first side wall between shape layer 271, the first side wall contacts with adjacent first graph layer 271, first side wall with it is adjacent First graph layer 271 forms ring structure, has the second side wall between adjacent second graph layer 272, the second side wall and adjacent the The contact of two graph layers 272, the second side wall and adjacent second graph layer 272 form ring structure.
Step is performed etching also using first side wall and the second side wall as exposure mask, respectively to the original mask layer 201 In first area, M forms the first articulamentum 311 (as shown in figure 15), forms 312 (such as Figure 15 of the second articulamentum in second area N It is shown), 311 both ends of the first articulamentum are contacted with the first adjacent graph layer 271 respectively, 312 liang of second articulamentum End is contacted with adjacent second graph layer 272 respectively.
Figure 14 is please referred to, is formed after mask layer 204, removes the stop-layer 202 on the mask layer 204 (such as Figure 13 institute Show).
It should be noted that since the thickness of the first area M and second area N stop-layer 202 are equal, and described The density of one region M mask layer 204 and second area N mask layer 204 is identical, is removing the stop-layer on the mask layer 204 During 202, the removal rate of the stop-layer 202 of the first area M and second area N is identical, to be gone by control Except time and removal rate, while capable of making to remove stop-layer 202 first area M, keep second area N stop-layer 202 lucky It is removed.Therefore, the forming method can reduce the loss to second area N mask layer 204, make the first area M and The thickness of second area N mask layer 204 is identical.
In the present embodiment, the technique for removing the stop-layer 202 includes chemically mechanical polishing.
It is subsequent that processing is patterned to the mask layer 204, the second opening is formed in the mask layer 204, it is described Second opening runs through the mask layer 204 in this second direction, and the second direction extends perpendicular to the mask layer 204 Direction removes first articulamentum 311 and the second articulamentum 312.
First articulamentum 311 and the second articulamentum 312 are removed for being separated from each other mask layer 204, thus after making It is continuous to form discrete dummy grid.
In the present embodiment, the graphical treatment is also used to control the length of the mask layer 204, makes the mask layer 204 have the length of design.
In the present embodiment, the step of removing first articulamentum and the second articulamentum and the graphical treatment, is such as Shown in Figure 15 to Figure 18.
Figure 15 and 16 are please referred to, Figure 16 is sectional view of the Figure 15 along cutting line 1-2, in the initial power ergosphere 210 and institute It states and forms the second flatness layer 261 on mask layer 204；The second anti-reflection coating 205 is formed on second flatness layer 261；? Patterned second photoresist (not shown) is formed in second anti-reflection coating 205.
Second flatness layer, 261 surface is flatter, so as to reduce the scattering of light, and then can form the second light During photoresist, reduce influence of the scattering light to the second photoresist.
The step of forming second photoresist includes: to provide the second light shield 300, has light in second light shield 300 Cover figure 301；The second initial light photoresist is formed in second anti-reflection coating 205；Pass through second light shield, 300 pairs of institutes It states the second initial light photoresist and is exposed processing, form the second photoresist.
The light mask image is used to define the position of the first articulamentum 311 of removal, the second articulamentum 312 and mask layer 204 It sets and size.
The material of second flatness layer 261 is organic dielectric material.The technique for forming second flatness layer 261 includes Spin coating proceeding.
The technique for forming second anti-reflection coating 205 includes spin coating proceeding；Form the second initial light photoresist Technique includes spin coating proceeding.
Figure 17 and Figure 18 are please referred to, Figure 18 is sectional view of the Figure 17 along cutting line 3-4, using second photoresist as exposure mask The mask layer 204, first articulamentum 311 and the second articulamentum 312 are performed etching, first articulamentum is removed 311 and second articulamentum 312, and the second opening is formed in the mask layer 204, second opening is in the first direction It is upper to run through the mask layer 204.
The articulamentum 310 is removed for being separated from each other mask layer 204, to make to be subsequently formed discrete dummy grid. Described second is open the length for controlling the mask layer 204, and the mask layer 204 is made to have the length of design.
It include that dry etch process or wet process are carved to the technique that the mask layer 204 and the articulamentum 310 perform etching Etching technique.
Figure 19 is please referred to, is that exposure mask performs etching the initial power ergosphere 210 with the mask layer 204, forms function Layer 211.
In the present embodiment, the functional layer 211 is used as dummy grid.In other embodiments, the functional layer can also be used Interconnection line is done, the material of the functional layer is metal.
It is that the technique that exposure mask performs etching the initial power ergosphere 210 includes with the mask layer 204 in the present embodiment Dry etch process.Dry etch process is controlled with good line width, can control the width for being formed by functional layer 211.
By controlling the technological parameter of dry etching, control initial power ergosphere 210 in horizontal and vertical etch rate, from And realize the control to 211 width of functional layer.
In the present embodiment, make longitudinal etch rate close to zero, thus can be to institute by control etch period The width of the functional layer 211 of formation is adjusted, to improve the precision for being formed by 211 width of functional layer.Specifically, can be with By the lateral direction power and longitudinal power control lateral etch rate and longitudinal etch rate that control dry etching.
In the present embodiment, it includes CF that the technological parameter performed etching to the initial power ergosphere 210, which includes: etching gas,4、 CHF3、CH2F2、CH3F、SF6、HBr、Cl2、O2、N2One of or multiple combinations, etching gas flow be 10sccm~ 500sccm, diluent gas include He and Ar, and the flow of He is 100sccm~1000sccm, the flow of Ar be 100sccm~ 1000sccm；RF source power is 200 watts~2000 watts；Bias drop is 100V~1000V；Etch period is 20s~60s.
It should be noted that by this present embodiment, the density phase of the first area M and second area N mask layer 204 Together, the first area M is identical with the etch rate of second area N initial power ergosphere 210.In addition, the first area M and Two region 204 thickness of N mask layer are identical.Therefore, institute can be exposed while exposing first area M substrate 200 just Second area N substrate 200 is stated, when so as to avoid first area M initial power ergosphere 210 from being exposed, to prevent institute It states second area N substrate 200 to damage because of over etching, so as to reduce the loss of second area N substrate 200, improves institute's shape At the performance of semiconductor structure.
Figure 20 is please referred to, forms protective layer 250 on the substrate 200, the protective layer 250 covers the functional layer 211 side walls, and expose 211 top of reserved area N1 functional layer.
The protective layer 250 is for protecting the substrate 200, so as in the subsequent removal removal area N2 During functional layer 211, the substrate 200 is protected, reduces the loss of substrate 200.
The material of the protective layer 250 is silica or titanium oxide.
The step of forming protective layer 250 includes: to be formed just on the first area M and second area N substrate 200 Beginning protective layer, the initial protective layers cover 211 side wall of functional layer and top；It is flat that first is carried out to the initial protective layers Smoothization processing, removes the initial protective layers in the functional layer 211, forms protective layer 250.
In the present embodiment, the technique for forming the initial protective layers includes fluid chemistry gas-phase deposition.Fluid chemistry The presoma of gas-phase deposition is fluid, can be sufficient filling with the gap between the functional layer 211.Therefore, fluid chemistry The filling capacity for the initial protective layers that gas-phase deposition is formed is good, can provide and adequately protect for substrate 200.
The technique of first planarization process includes chemical mechanical milling tech.
In the present embodiment, the subsequent removal blank area M2 functional layer 211, therefore, the protective layer 250 also exposes institute State 204 top of blank area M2 mask layer.
The forming method further include: third anti-reflection coating is formed on the protective layer 250 and the mask layer 204 241；Patterned third photoresist 242 is formed in the third anti-reflection coating 241；The exposure of third photoresist 242 The removal area N2 and blank area M2 anti-reflection coating 241 out.
During forming third photoresist 242, the third anti-reflection coating 241 is for absorbing the reflection of substrate 200 Light, reduce influence of the reflected light to third photoresist 242.
The third photoresist 242 is used to protect the functional layer 211 of the functional areas M1 and reserved area N1.
Figure 21 is please referred to, the functional layer 211 of the removal area N2 is removed.
It in the present embodiment, is formed after the protective layer 250, removes the functional layer 211 of the removal area N2.In removal institute During the functional layer 211 for stating removal area N2, the protective layer 250 can protect the substrate between successive functional layers 211 200, reduce the loss of substrate 200, so as to improve the performance of formed semiconductor structure.
In the present embodiment, the forming method further include: remove the blank area M2 functional layer 211.
In the present embodiment, the blank area M2 is removed by same technique and removes the functional layer 211 of area N2.By same Technique remove the blank area M2 and remove area N2 functional layer 211, can simplification of flowsheet, reduce process costs.
It is that exposure mask carves the functional layer 211 and mask layer 204 with the third photoresist 242 in the present embodiment Erosion removes the blank area M2 and removes the mask layer 204 of area N2 and the functional layer 211 of blank area M2 and removal area N2, Groove 251 is formed in the protective layer 250.
Figure 22 is please referred to, after the functional layer 211 for removing the removal area N2, removes the protective layer 250.
In the present embodiment, the technique for removing the protective layer 250 includes chemical vapor deposition process or physical vapour deposition (PVD) Technique.
Figure 23 is please referred to, after removing the protective layer 250, forms dielectric layer 252 on the substrate 200.
The dielectric layer 252 is for realizing the electric isolution between functional layer 211.
The material of the dielectric layer 252 is silica, silicon nitride, silicon oxynitride or low k (k is less than 3.9) dielectric material.
The step of forming dielectric layer 252 includes: formation initial medium layer, initial Jie on the substrate 200 Matter layer covers 211 side wall of functional layer and top；Second planarization process is carried out to the initial medium layer, removes the function Initial medium layer on 211 top of ergosphere, forms dielectric layer 252.
The technique for forming the initial medium layer includes fluid chemistry gas-phase deposition or high-aspect-ratio depositing operation.
The technique of second planarization process includes chemical mechanical milling tech.
It should be noted that in other embodiments, the protective layer can not also be removed.Remove the blank area and institute After stating removal area's functional layer, groove is formed in the protective layer.The forming method further include: formed in the trench Separation layer, the separation layer and the protective layer constitute dielectric layer.The material of the separation layer and the protective layer be silica, Silicon nitride or silicon oxynitride or low k dielectric materials.
Figure 24 is please referred to, the functional layer 211 (as shown in figure 23) is removed and forms first in the dielectric layer 252 and open Mouthful；Gate structure 260 is formed in first opening.
It should be noted that 204 thickness of mask layer due to the first area M and second area N is identical, and the firstth area The thickness of domain M and second area N functional layer 211 is identical.Formed described first opening during, the first area M and The functional layer 211 of second area N can be removed simultaneously, to be not easy that second area N substrate 200 is made to be etched, Jin Erneng The loss for enough reducing substrate 200, improves formed semiconductor structure performance.
The gate structure 260 includes: the gate dielectric layer for covering first open bottom and side wall；It is situated between positioned at the grid Grid on matter layer.
The material of the gate dielectric layer is high k (k is greater than 3.9) dielectric material, such as: for example: HfO2、La2O3、HfSiON、 HfAlO2、ZrO2、Al2O3Or HfSiO4。
The material of the grid is metal, such as: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
Present invention implementation also provides a kind of semiconductor structure that the forming method as shown in Fig. 7 to Figure 24 is formed.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (20)

1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes first area and second area, and the second area includes mutually discrete and alternately arranges The removal area of column and reserved area, the orientation of the removal area and reserved area are first direction；
Initial power ergosphere is formed on the first area and second area substrate；
Original mask layer is formed on the initial power ergosphere；
Multiple the first discrete graph layers are formed on the first area original mask layer, respectively at the beginning of removal area and reserved area Forming second graph layer on beginning mask layer, first graph layer is first size along the size of the first direction, described the Two graph layers are the second size along the size of the first direction, and second size is equal to first size, adjacent first figure Spacing between layer is equal with the spacing between adjacent second graph layer；
Form the covering reserved area second graph layer side wall widens layer；
It widens layer, the first graph layer and second graph layer using described the original mask layer is performed etching as exposure mask, formation is covered Film layer；
The initial power ergosphere is performed etching using the mask layer as exposure mask, forms functional layer；
Remove the functional layer in the removal area.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that form first graph layer and the The step of two graph layers includes: to be respectively formed multiple discrete cores on the first area and second area original mask layer Layer, the spacing between the core layer of adjacent first regions is equal with the spacing between the core layer of adjacent second zone, first area Core layer is third size along the size of the first direction, and the second area core layer is along the size of the first direction 4th size, the third size are equal to the 4th size；At the top of the core layer and on side wall and the original mask layer Form initial graphics layer；Anisotropic etching is carried out to the initial graphics layer, removes the original mask layer and the core Initial graphics layer at the top of central layer forms multiple the first discrete graph layers in the first area, and in the removal area and Reserved area forms second graph layer；After the anisotropic etching, the core layer is removed.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that formed before the core layer, also It include: that stop-layer is formed on the original mask layer, the material of the stop-layer is not identical as the material of the core layer；Shape After the mask layer, further includes: remove the stop-layer on the mask layer.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of being widened described in formation layer packet It includes: forming the first flatness layer, first flatness layer on the original mask layer, first graph layer and second graph layer Surface is higher than at the top of first graph layer and second graph layer；Patterned first photoetching is formed on first flatness layer Glue, patterned first photoresist are completely covered at the top of the reserved area second graph layer, and along first direction, institute The size for stating the first photoresist is greater than the size of the reserved area second graph layer；It is exposure mask to described using first photoresist First flatness layer performs etching, and layer is widened described in formation.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the material of first flatness layer is Organic dielectric material.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of being widened described in formation layer packet It includes: forming covering first graph layer and the initial of second graph layer side wall widens layer, the material for initially widening layer is Photoresist；It initially widens layer to described and is exposed processing, remove the initial of the first area and widen layer, formation is widened Layer.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that removal removal area functional layer it Before, further includes: protective layer is formed on the first area and second area substrate, the protective layer covers the functional layer side Wall, and expose at the top of removal area functional layer.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the step of forming protective layer packet It includes: forming initial protective layers on the first area and second area substrate, the initial protective layers cover the functional layer Side wall and top；First planarization process is carried out to the initial protective layers, removes the initial protective layers in the functional layer, shape At protective layer.
9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that removal removal area functional layer it Afterwards, further includes: remove the protective layer.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that after removing the protective layer, also It include: that formation initial medium layer, the initial medium layer cover the functional layer side wall and top over the substrate；To described Initial medium layer carries out the second planarization process, removes the initial medium layer at the top of the functional layer, forms dielectric layer；Removal The functional layer forms the first opening in the dielectric layer；Gate structure is formed in first opening.
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the initial protective layers For silica or titanium oxide；The technique for forming the initial protective layers includes fluid chemistry gas-phase deposition.
12. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that removal removal area functional layer Later, groove is formed in the protective layer；
The forming method further include: form separation layer in the trench.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that the first area includes function Area and blank area；The forming method further include: remove the functional layer of the blank area；The blank is removed by same technique Area's functional layer and removal area functional layer.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that have between adjacent first graph layer There is the first side wall, the first side wall is contacted with adjacent first graph layer, and first side wall and the first adjacent graph layer form ring Shape structure；There is the second side wall between adjacent second graph layer, the second side wall contacts with adjacent second graph layer, the second side wall and Adjacent second graph layer forms ring structure；The step of performing etching to the original mask layer is also with first side wall and Two side walls are exposure mask, form the first articulamentum in first area respectively, form the second articulamentum in second area, described first connects It connects layer both ends to contact with the first adjacent graph layer respectively, second articulamentum both ends connect with adjacent second graph layer respectively Touching；
Before being performed etching to the initial power ergosphere, further includes: removal first articulamentum and the second articulamentum.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the mask layer is long strip type, It is second direction perpendicular to the direction that the mask layer extends；It is formed before functional layer, the forming method further include: to described Mask layer is patterned processing, the second opening is formed in the mask layer, second opening is in this second direction Through the mask layer, the second direction falls in the mask layer extending direction；
The step of removing first articulamentum and the second articulamentum and the graphical treatment include: to the mask layer, First articulamentum and the second articulamentum perform etching, and remove first articulamentum and the second articulamentum and the shape in mask layer At the second opening, second opening runs through the mask layer in this second direction.
16. the forming method of semiconductor structure as described in claim 1, which is characterized in that functional layer in the removal area Number is single or multiple.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the functional layer is more Crystal silicon, polycrystalline germanium, polycrystalline silicon germanium, aluminium, tungsten or copper aluminium.
18. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the functional layer of adjacent first regions The distance between heart is 50nm~60nm；The distance between functional layer center is 100nm~120nm in adjacent second zone；Institute It is 6nm~8nm that first area functional layer, which is stated, along the size of first direction；The reserved area functional layer is along the size of first direction 12nm~16nm.
19. the forming method of semiconductor structure as described in claim 1, which is characterized in that using the mask layer as exposure mask pair It includes CF that the technological parameter that the initial power ergosphere performs etching, which includes: etching gas,4、CHF3、CH2F2、CH3F、SF6、HBr、 Cl2、O2、N2One of or multiple combinations, etching gas flow be 10sccm~500sccm, diluent gas includes He and Ar, The flow of He is 100sccm~1000sccm, and the flow of Ar is 100sccm~1000sccm；RF source power is 200~2000 Watt；Bias drop is 100V~1000V；Etch period is 20s~60s.
20. a kind of semiconductor junction that the forming method by claim 1 to claim 19 any one semiconductor structure is formed Structure.
CN201710889671.1A 2017-09-27 2017-09-27 Semiconductor structure and forming method thereof Active CN109559978B (en)

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CN113764274A (en) * 2020-06-03 2021-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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