CN110246895A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The embodiment of the invention provides a kind of semiconductor structure and forming method thereof, method includes forming substrate, and the substrate includes substrate, and the dielectric layer on the substrate, and opening is formed in the dielectric layer, is formed with side wall on the opening sidewalls；Part side wall is removed, remaining side coping is made to be lower than the top of the opening, forms stop-layer；The gate material layers for covering the stop-layer are formed in said opening；Removal is located at the gate material layers above the stop-layer, forms gate structure, the gate structure and the stop-layer and dielectric layer surrounds groove；Protective layer is formed in the groove.By the protective layer, hole plug can be avoided contact with and short circuit occurs for gate structure, be improved the electric property of semiconductor devices.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductors, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the continuous development of semiconductor process technology, such as the introduction of high-K gate dielectric layer, stress engineering technology, pocket ion implantation, and continuous optimization of materials and device structures, the size of semiconductor devices continues to shrink. However, when the feature size of the device is further reduced, planar transistors face huge challenges due to the more significant short-channel effect, process variation, and reduced reliability. Compared with planar transistors, FinFETs have fully depleted fins, lower dopant ion concentration fluctuations, higher carrier mobility enhancement, lower parasitic junction capacitance, and higher area usage efficiency has received extensive attention.

In the integrated circuit manufacturing process, after the semiconductor device structure is formed on the substrate, it is necessary to use multiple metallization layers to connect each semiconductor device together to form a circuit. The metallization layer includes interconnection lines and contacts formed in contact holes. Hole plugs, the contact hole plugs in the contact holes are connected to semiconductor devices, and the interconnection wires connect the contact hole plugs on different semiconductor devices to form a circuit. The contact hole plug formed on the transistor includes a contact hole on the surface of the gate, and a contact hole connecting the source and the drain. With the continuous shrinking of the integrated circuit process node, the distance between adjacent gates is gradually reduced, and it is impossible to form contact holes on the surface of the source and drain between adjacent gates by direct photolithography and etching. At this time, usually The contact hole connecting the source and the drain is formed by using a self-alignment process.

However, in the prior art, a self-alignment process is used to form a contact hole, which easily leads to a decrease in the electrical performance of the semiconductor device.

Contents of the invention

The technical problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure and optimize the electrical performance of the semiconductor device.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a base, the base includes a substrate, and a dielectric layer on the substrate, the dielectric layer is formed with an opening, A side wall is formed on the side wall of the opening; part of the side wall is removed so that the top of the remaining side wall is lower than the top of the opening to form a stop layer; a gate material layer covering the stop layer is formed in the opening and removing the gate material layer above the stop layer to form a gate structure, the gate structure forms a groove with the stop layer and the dielectric layer; forming a protection layer in the groove.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including a substrate; a gate structure located on the substrate; a side wall located on the side wall of the gate structure; a protective layer located on the gate structure. pole structure and the side wall; a dielectric layer located on the exposed substrate of the side wall and the grid structure, and the top of the dielectric layer is flush with the top of the protection layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, after the side wall is formed on the side wall of the opening, part of the side wall is removed to form a stop layer; after the gate material layer is formed in the opening, the gate material layer above the stop layer is removed to form a gate structure; the side wall formed The stop layer ensures that the gate material layer above it is removed more thoroughly, and no tentacles of the gate material layer are left, which solves the problem that the contact hole plug may be too close to or in contact with the tentacles of the left gate material layer, And a protective layer is formed in the groove surrounded by the gate structure, the stop layer and the dielectric layer, so that when the contact hole is formed by the subsequent self-alignment process, although the gate structure and the sidewall are exposed to the etching of the contact hole In the environment, the protective layer on top of it can protect it. Even if the etching rate of the protective layer is relatively high in the etching process, and a contact hole with a shape with a large top and a small bottom is formed, the protective layer still remains The isolation between the contact hole plug and the gate structure can be realized, and the problem that the distance between the contact hole plug and the gate structure is too close, or the problem of contact with the gate structure can be avoided, and the short circuit between the contact hole plug and the gate structure can be avoided. The electrical performance of the semiconductor device is improved.

In an optional solution, before removing part of the spacer to form the stop layer, a dummy gate is formed between the sidewalls, and part of the dummy gate is removed to form the sidewall stop layer. Since it is necessary to accurately determine the removed height when removing part of the sidewall to form a stop layer, by forming a dummy gate and removing part of the dummy gate, first determine the sidewall stop layer, and then use the sidewall stop layer Determine the removal height of the side wall to ensure that the removal amount of the side wall is more accurate.

In an optional solution, the gate material layer above the stop layer is removed. When forming the gate structure, the gate material layer above the stop layer is first removed to expose the stop layer. Since the gate material layer is different from the material of the sidewall, This can improve the possibility of completely removing the gate material layer above the sidewalls and expose the stop layer, so that it is easier to control the removal of the gate material layer located between the sidewalls and above the stop layer At the same time, it can also ensure more thorough removal, prevent the existence of residues, and avoid its influence on the electrical properties of semiconductor devices.

The present invention provides a semiconductor structure. The semiconductor structure includes: a protective layer located on the gate structure and the side wall; a dielectric layer located on the exposed substrate of the side wall and the gate structure. The top of the dielectric layer is flush with the top of the protective layer. When forming a contact hole plug, the protective layer on the top of the gate structure and sidewall can protect it, even if the etching rate of the protective layer is relatively high in the etching process, a shape with a large top and a small bottom is formed. In the case of a contact hole, the protective layer can still isolate the contact hole plug from the gate structure, avoiding the problem that the contact hole plug is too close to the gate structure, or in contact with the gate structure, thereby avoiding contact The hole plug is short-circuited with the gate structure, so that the electrical performance of the semiconductor device is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

1 to 5 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

6 to 16 are schematic diagrams of structures corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

It can be seen from the background art that in the prior art, a self-alignment process is used to form contact holes, which easily leads to a decrease in the electrical performance of the semiconductor device. Figures 1 to 5 are schematic diagrams of the structures corresponding to each step in a method for forming a semiconductor structure. The method for forming a semiconductor structure includes the following steps:

Referring to FIG. 1 , a base is provided, the base includes a substrate 100 and a dielectric layer 110 on the substrate 100, an opening is formed in the dielectric layer 110, and sidewalls 130 are formed on the side walls of the opening; A gate structure 120 is formed between the sidewalls 130 .

Referring to FIG. 2 , part of the thickness of the gate structure 120 is removed to form a groove 111 between the sidewalls 130 .

Referring to FIG. 3 , a protective layer 112 is formed to fill the groove 111 (as shown in FIG. 2 ), and the top of the protective layer 112 is flush with the top of the dielectric layer 110 . The passivation layer 112 is used to protect the top of the gate structure 120 during subsequent formation of contact holes.

Please refer to FIG. 2 and FIG. 4 in conjunction. However, during the process of etching the gate structure 120 with a partial thickness to form the groove 111, on the one hand, since the gate structure 120 is close to the side wall 130 The material is generally a high-K gate dielectric material, which is more difficult to etch than the material in the middle of the gate structure 120; on the other hand, its position is close to the sidewall, and the etching rate will be greatly affected Moreover, in order to control the depth of the groove 111, the gate structure 120 cannot be etched by an over-etching process. Therefore, it is easy to cause incomplete etching of the material of the gate structure 120 near the spacer wall 130 after etching, that is, the antenna A is left.

With reference to Fig. 5, when subsequently forming contact hole plug, form the pattern medium layer 140 that covers described dielectric layer 110, spacer 130 and protective layer 112 top; shown), the graphic layer has an opening (not shown) that exposes part of the graphic medium layer 140, and the opening is located in the graphic medium between adjacent sidewalls 130 of two adjacent gate structures 120. layer 140, and along the direction perpendicular to the sidewall of the gate structure 120, the width of the opening is larger than the width of the dielectric layer 110 between adjacent sidewalls 130; using the pattern layer as a mask, using self-alignment A quasi-etching process, etching the dielectric layer 110 and the patterned dielectric layer 140 to form a contact hole 150, and then forming a contact hole plug filling the contact hole 150 to realize the source and drain (not shown in the figure) and Contact hole plug connection.

However, referring to FIG. 4 and FIG. 5 in conjunction, during the process of etching the dielectric layer 110 and the patterned dielectric layer 140, the opening (not shown) of the patterned layer exposes the spacer 130 and the protective layer 112, That is, the sidewall 130 and the protective layer 112 are exposed to the etching environment; the etching process has a relatively high etching rate for the top of the sidewall 130 and the protective layer 112, which easily causes the problem that both of them will be etched. ; In this case, the formed contact hole 150 (as shown in FIG. 5 ) presents a situation that the top is large and the bottom is small. Due to the existence of the antennae A, the contact hole 150 exposes the gate structure 120 The antenna A further causes a short circuit between the contact hole plug (not shown in the figure) filled in the contact hole 150 and the gate structure 120 . Therefore, both the electrical performance and the yield of the formed semiconductor device will decrease.

In order to solve the above problem, the embodiment of the present invention removes part of the sidewall to form a stop layer; after forming a gate material layer covering the stop layer in the opening, remove the gate material layer above the stop layer to form a gate structure; the sidewall The formed stop layer eliminates the influence of the existence of the sidewall on the etching rate of the gate material layer close to the sidewall, ensures that the gate material layer above it is removed more thoroughly, and reduces the contact angle of the gate material layer. Legacy, which solves the problem that the contact hole plug may be too close to or in contact with the antennae of the legacy gate material layer, and forms a protective layer in the groove surrounded by the gate structure, stop layer and dielectric layer, so that it can be used later When the contact hole is formed by the self-alignment process, although the gate structure and sidewall are exposed to the etching environment for forming the contact hole, the protective layer on top of it can protect it, even if the etching process damages the protective layer. When the etch rate is relatively high and a contact hole with a shape with a large top and a small bottom is formed, due to the disappearance of the antennae of the gate material layer, the protective layer can still isolate the contact hole plug from the gate structure, avoiding contact holes. The distance between the plug and the gate structure is too close, or the problem of contact with the gate structure can avoid the short circuit between the contact hole plug and the gate structure, and improve the electrical performance of the semiconductor device.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

6 to 16 are schematic diagrams of structures corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

With reference to FIGS. 6 to 9 , a base is formed, the base includes a substrate 200 (as shown in FIG. 6 ), a dielectric layer 210 on the substrate 200, and an opening 211 is formed in the dielectric layer 210 ( As shown in Figure 9), a side wall 230 (as shown in Figure 6 ) is formed on the side wall of the opening 211, and then part of the side wall 230 is removed, so that the top of the remaining side wall 230 is lower than the opening 211 on top, forming a stop layer.

In one embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate 200 can also be germanium, silicon germanium, silicon carbide, silicon arsenide, gallium arsenide or potassium indium, and the substrate 200 can also be a silicon-on-insulator substrate. base or germanium-on-insulator substrate.

In another embodiment, the base includes a substrate 200 and fins (not shown in the figure) on the substrate 200, the dielectric layer 210 covers the substrate 200 and the fins, and the opening 211 opens In the dielectric layer 210 and across the fin, a sidewall 230 is formed on the sidewall of the opening 211, across the fin, and covers the top surface and the sidewall surface of the fin.

Specifically, the material of the fin is the same as that of the substrate, and in this embodiment, the material of the fin is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide, and potassium indium.

The specific steps of forming the fins may be: providing an initial substrate, forming a patterned fin hard mask layer on the surface of the initial substrate, using the fin hard mask layer as an etching mask to etch the The initial substrate after etching is used as the substrate 200, and the protrusions on the surface of the substrate 200 are used as fins; the hard mask layer of the fins is removed.

The material of the sidewall 230 is different from that of the dielectric layer 210 , and the sidewall 230 can not only protect the gate structure, but also serve as an etching mask for subsequent formation of contact holes by a self-aligned etching process.

The material of the dielectric layer 210 is insulating material. In this embodiment, the material of the dielectric layer 210 is silicon oxide. In other embodiments, the material of the dielectric layer 210 may also be silicon nitride or silicon oxynitride.

In this embodiment, the material of the sidewall 230 is silicon nitride. In other embodiments, the material of the sidewall 230 may also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride.

The steps of forming the stop layer will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 6 , a dummy gate 220 is formed between the sidewalls 230 . The dummy gate 220 may occupy a spatial position for a subsequently formed gate structure.

Specifically, the step of forming the dummy gate 220 includes: forming a dummy gate material layer between the sidewalls 230, above the sidewall 230 and above the dielectric layer 210, and performing a planarization process on the dummy gate material layer to form a dummy gate 220 , making the surface of the dummy gate 220 flat, and the top of the dummy gate 220 being flush with the sidewall 230 . In this embodiment, the material of the dummy gate 220 can be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon, forming a dummy gate material layer The process can be a chemical vapor deposition process, for example: a plasma enhanced chemical vapor deposition process or a low pressure chemical vapor deposition process, etc. The planarization process can specifically use a chemical mechanical polishing process. In other embodiments, other materials or processes can also be used The dummy gate 220 is formed. .

Referring to FIG. 7 , part of the dummy gate 220 is removed so that the top of the remaining dummy gate 220 is lower than the top of the spacer 230 to form a sidewall stop layer.

Specifically, the process of removing part of the dummy gate 220 may be an etching process, for example: a dry etching process, a wet etching process, or a combination of dry etching and wet etching, but the dry etching process The control of etching depth is more accurate.

Then, remove the spacer 230 above the sidewall stop layer (ie the remaining dummy gate 220), so that the top of the remaining spacer 230 is lower than the top of the opening 211 (as shown in FIG. 9 ), forming a stopper layer , please refer to Figure 8 for details.

The sidewall stop layer is used as the stop layer for processing the sidewall 230 to define the etching stop position for removing part of the sidewall, so as to avoid inaccurate etching control of the sidewall 230 . Certainly, the specific etching process may also be a dry etching process, a wet etching process, or a combination of dry etching and wet etching.

Finally, the sidewall stop layer (that is, the remaining dummy gate 220 ) is removed to form a structure as shown in FIG. 9 . Specifically, the sidewall stop layer can be removed through an etching process.

Remove part of the sidewall 230 through the above steps, and when forming the stop layer, form the dummy gate 220 and remove part of the dummy gate 220 to obtain the sidewall stop layer, and then use the sidewall stop layer to determine the removal height of the sidewall 230 , which ensures a more accurate removal height of the sidewall 230 and also makes the formation of the subsequent gate structure more accurate.

Of course, the stop layer can also be obtained by directly removing the sidewall 230 or by other methods.

After removing part of the sidewall 230 and forming the stop layer, a gate material layer is formed in the opening 211 (as shown in FIG. 9 ). Please refer to FIGS. The detailed steps of a specific embodiment of forming a gate material layer in ) are shown.

Specifically, the step of forming the gate material layer includes: forming a gate dielectric film 240 (as shown in FIG. ); form a gate electrode film 250 (as shown in FIG. 11 ) that fills the opening 211 (as shown in FIG. 9 ), and the gate electrode film 250 covers the top of the gate dielectric film 240; remove The gate dielectric film 240 and the gate electrode film 250 of the layer 210 form the gate dielectric layer 241 (as shown in FIG. 12 ) at the bottom of the opening 211 and the stop layer, and cover the gate dielectric layer 241 and fill the The gate electrode layer 251 of the opening 211 (as shown in FIG. 12 ).

In this embodiment, the material of the gate dielectric layer 241 is silicon oxide or a high-K gate dielectric material, and the high-K gate dielectric material includes hafnium oxide, zirconium oxide, aluminum oxide, or silicon hafnium oxide; the gate electrode layer 251 can be It includes a work function material layer and a gate metal material layer on the work function material layer, and the material of the gate metal material layer is at least one of Al, Cu, W, Ti, Ta, Co, Ag and Au.

Please refer to FIG. 13 , FIG. 14 and FIG. 16 in conjunction. After forming the gate material layer, remove the gate material layer above the stop layer to form the gate structure, which may specifically include: removing the top of the spacer 230 a gate material layer; removing the gate material layer located between the stop layers and above the stop layer to form the gate structure.

After the gate structure is obtained, the gate structure, the stop layer and the dielectric layer 210 enclose a groove 252 (as shown in FIG. 14 ), and the groove 252 provides a space for the subsequent formation of a protective layer.

It should be noted that the depth of the groove 252 should neither be too small nor too large. If the depth of the groove 252 is too small, the thickness of the protective layer 260 subsequently formed in the groove 252 is also small, and it is difficult for the protective layer 260 to play a role in the subsequent etching process for forming a contact hole. The effect of reducing the loss of the side wall 230; if the depth of the groove 252 is too large, it is easy to cause the aspect ratio of the groove 252 to be too large, which easily leads to the subsequent formation of the protective layer 260 in the groove 252 ( As shown in FIG. 16 ), the gap-filling capability of the protective layer material is poor. For this reason, in the present embodiment, the depth of described groove 252 is to

Removing the gate material layer located on the top of the stop layer by an etching process, which may specifically be: a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process, and In the etching process, the stop layer is used to first remove the gate material layer above the stop layer. Since the gate material layer is different from the material of the side wall, the possibility of completely removing the gate material layer above the side wall can be improved. And expose the stop layer to ensure the etching degree of the gate material layer. Specifically, an over-etching process can be used to ensure the complete etching of the gate material layer and prevent problems such as antennae left behind.

Of course, in order to ensure that the sidewall 230 will not be damaged when the gate material layer is etched using the over-etching process, the etching selectivity ratio between the gate material layer and the sidewall 230 may be: 100: 1-1000:1.

After the gate material layer on the top of the stop layer (remaining spacer 230) is etched, the gate material layer between and above the stop layer is etched, so that When removing the gate material layer between the walls and above the stop layer, it is easier to control the thickness of the removal, and it can also ensure more thorough removal, prevent the existence of residues, and avoid its influence on the electrical properties of semiconductor devices. The etching process can be: dry etching process, wet etching process or a combination of dry etching process and wet etching process. Of course, in order to ensure the controllability of the depth during the etching process, you can choose ion bulk dry etching process. The etching gas used in the plasma dry etching process is a fluorine-based gas, specifically one or more of CHF ₃ , C ₂ F ₆ , CF ₄ and the like.

Please refer to FIG. 15 and FIG. 16 in combination, a protective layer 260 is formed in the groove 252 (as shown in FIG. 14 ).

Specifically, the step of forming the protective layer 260 in the groove 252 includes: forming a protective film 261 that fills the groove 252 , removing the protective film higher than the dielectric layer 210 , forming a layer located in the groove 252 The protective layer 260 in.

In this embodiment, the material of the protective layer 260 is the same as that of the sidewall 230, so that after the groove 252 is filled, the protective layer 260 above the stop layer and the stop layer (remaining sidewall 230) constitute a Overall, protection for the gate structure is formed.

In this embodiment, the passivation layer 260 and the sidewall 230 are made of silicon nitride. In other embodiments, it may be silicon oxide, silicon oxynitride, silicon carbide, or silicon oxycarbide.

It should be noted that, in this embodiment, a chemical mechanical polishing process is used to remove the protective film 261 higher than the dielectric layer 210 . In other embodiments, a wet etching process or a dry etching process may also be used.

Continuing to refer to FIG. 16 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including:

a substrate 200; a gate structure located on the substrate 200; a sidewall 230 located on the sidewall of the gate structure; a protective layer 260 located on the gate structure and the sidewall 230; and The dielectric layer 210 is located on the substrate 200 where the sidewall 230 and the gate structure are exposed, and the top of the dielectric layer 210 is flush with the top of the protection layer 260 .

In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate 200 can also be germanium, silicon germanium, silicon carbide, silicon arsenide, gallium arsenide or potassium indium, and the substrate 200 can also be a silicon-on-insulator substrate. base or germanium-on-insulator substrate.

In another embodiment, the base includes a substrate 200, a fin (not shown) on the substrate 200, spans the fin, and covers the top surface and the sidewall of the fin. The gate structure and sidewalls on the surface, the protective layer 260 on the gate structure and sidewalls 230, the dielectric layer 210 covering the substrate 200 exposed by the gate structure and sidewalls and the fins, and the top of the dielectric layer 210 Flush with the top of the protective layer 260.

Specifically, the material of the fin is the same as that of the substrate, and in this embodiment, the material of the fin is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide, and potassium indium.

The material of the sidewall 230 is different from that of the dielectric layer 210, and the sidewall 230 can not only protect the gate structure, but also serve as an etching mask for subsequent formation of contact holes by using a self-aligned etching process. .

The material of the dielectric layer 210 is insulating material. In this embodiment, the material of the dielectric layer 210 is silicon oxide. In other embodiments, the material of the dielectric layer 210 may also be silicon nitride or silicon oxynitride.

In this embodiment, the material of the sidewall 230 is silicon nitride. In other embodiments, the material of the side wall 230 may also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride.

In this embodiment, the material of the protective layer 260 is the same as that of the sidewall 230 , so that the protective layer 260 above the sidewall 230 and the sidewall 230 are integrally formed to protect the gate structure.

In this embodiment, the passivation layer 260 and the sidewall 230 are made of silicon nitride. In other embodiments, it may be silicon oxide, silicon oxynitride, silicon carbide, or silicon oxycarbide.

In this embodiment, the gate structure includes a gate dielectric layer 241 and a gate electrode layer 251. The material of the gate dielectric layer 241 is silicon oxide or a high-K gate dielectric material, and the high-K gate dielectric material includes hafnium oxide, zirconium oxide, oxide Aluminum or silicon hafnium oxide, etc.; the gate electrode layer 251 may include a work function material layer and a gate metal material layer on the work function material layer, and the material of the gate metal material layer is Al, Cu, W, Ti , Ta, Co, Ag and Au at least one.

It should be noted that the thickness of the protective layer 260 should not be too small, nor should it be too large. If the thickness of the protective layer 260 is too small, it is difficult for the protective layer 260 to reduce the loss of the sidewall 230 in the subsequent etching process for forming the contact hole; if the thickness of the protective layer 260 is too large, The gap-filling capability of forming the passivation layer 260 is poor. Therefore, in this embodiment, the thickness of the protective layer 260 is to

In the semiconductor structure provided by the embodiment of the present invention, since the protective layer is provided on the top of the sidewall 230 and the gate structure, when the contact hole plug is formed, the protective layer 260 on the top of the gate structure and the sidewall 230 can Play a protective role, even if the etch rate of the protective layer 260 is relatively high in the etching process, forming a contact hole in a shape with a large top and a small bottom, the protective layer 260 can still realize the contact hole plug and gate structure The isolation can avoid the problem that the distance between the contact hole plug and the gate structure is too close, or the problem of contact with the gate structure can be avoided, and the short circuit between the contact hole plug and the gate structure can be avoided, and the electrical performance of the semiconductor device can be improved.

Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of forming method of semiconductor structure characterized by comprising

Substrate is formed, the substrate includes substrate, and the dielectric layer on the substrate, is formed with out in the dielectric layer Mouthful, side wall is formed on the opening sidewalls；

Part side wall is removed, remaining side coping is made to be lower than the top of the opening, forms stop-layer；

The gate material layers for covering the stop-layer are formed in said opening；

Removal is located at the gate material layers above the stop-layer, forms gate structure, the gate structure and the stop-layer Groove is surrounded with dielectric layer；

Protective layer is formed in the groove.

2. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the step of forming the substrate, Dummy grid is formed between the side wall；

Part side wall is removed, remaining side coping is made to be lower than the top of the opening, forming stop-layer includes: that removal part is pseudo- Grid makes the top of remaining dummy grid lower than the side coping, forms side wall stop-layer；Removal is located at the side wall and stops The side wall of layer top, makes remaining side coping be lower than the top of the opening, forms stop-layer；

Remove the side wall stop-layer.

3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the work of the removal part dummy grid Skill is dry etch process.

4. the forming method of semiconductor structure as described in claim 1, which is characterized in that form covering institute in said opening The step of stating the gate material layers of stop-layer include:

Form the gate dielectric film of the conformal covering open bottom, the stop-layer and the dielectric layer；

The gate electrode film for filling the full opening is formed, the gate electrode film covers at the top of the gate dielectric film；

Removal is higher than the gate dielectric film and gate electrode film of the dielectric layer, is formed and is located at the open bottom and the stop-layer Gate dielectric layer, and the covering gate dielectric layer and the gate electrode layer for filling the full opening.

5. the forming method of semiconductor structure as described in claim 1, which is characterized in that removal is located above the stop-layer Gate material layers, formed gate structure the step of, comprising:

Removal is located at the gate material layers at the top of the stop-layer；

Removal is located at after the gate material layers at the top of the stop-layer, and removal is between the stop-layer and is located at described stop The only gate material layers above layer form the gate structure.

6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that removal is located at the top of the stop-layer The technique of gate material layers include over etching technique.

7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the gate material layers are stopped with described The only etching selection ratio of layer are as follows: 100:1-1000:1.

8. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that removal is located above the stop-layer Gate material layers, formed gate structure technique be plasma dry etch process.

9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the plasma dry etch work The etching gas of skill is fluorine base gas.

10. the forming method of semiconductor structure as described in claim 1, which is characterized in that form protection in the groove Layer the step of include:

Form the protective film for filling the full groove；

Removal is higher than the protective film of the dielectric layer, forms the protective layer being located in the groove.

11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that removal is higher than the dielectric layer The technique of protective film is chemical mechanical grinding.

12. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the gate electrode layer includes work content Number material layer and the gate metal material layer in the workfunction material.

13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the gate metal material layer Material includes at least one of Al, Cu, W, Ti, Ta, Co, Ag and Au.

14. such as the forming method of the described in any item semiconductor structures of claim 1-13, which is characterized in that the depth of the groove Degree isExtremely

15. as the described in any item semiconductor structures of claim 1-13 forming method, which is characterized in that the protective layer and The material of the side wall is identical.

16. such as the forming method of the described in any item semiconductor structures of claim 1-13, which is characterized in that the protective layer Material is silicon nitride.

17. a kind of semiconductor structure characterized by comprising

Substrate；

Gate structure is located on the substrate；

Side wall, on the side wall of the gate structure；

Protective layer is located on the gate structure and the side wall；

Dielectric layer, on the substrate that the side wall and gate structure expose, the top of the dielectric layer and the protective layer Top flushes.

18. semiconductor structure as claimed in claim 17, which is characterized in that the protective layer with a thickness ofExtremely

19. semiconductor structure as claimed in claim 17, which is characterized in that the material of the material of the protective layer and the side wall Expect identical.

20. semiconductor structure as claimed in claim 17, which is characterized in that the material of the protective layer is silicon nitride.