CN113113485B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN113113485B CN113113485B CN202010032452.3A CN202010032452A CN113113485B CN 113113485 B CN113113485 B CN 113113485B CN 202010032452 A CN202010032452 A CN 202010032452A CN 113113485 B CN113113485 B CN 113113485B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 20
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- 238000001312 dry etching Methods 0.000 claims description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, and forming a source-drain doping layer on the substrate; forming a dielectric layer on the source-drain doped layer; sequentially etching the dielectric layer, the source-drain doping layer positioned at the bottom of the dielectric layer and the substrate with partial thickness positioned at the bottom of the source-drain doping layer to form a contact hole; forming a protective layer on the bottom of the contact hole and the side wall of the contact hole; forming a sacrificial layer on the protective layer at the bottom of the contact hole, wherein the sacrificial layer covers part of the protective layer on the side wall of the contact hole; removing the protective layer uncovered by the sacrificial layer; removing the sacrificial layer; on one hand, the invention can reduce the contact resistance between the source-drain doping layer and the conducting layer positioned on the source-drain doping layer in the subsequent process, improve the electrical property of the semiconductor device, reduce the heat effect of the semiconductor device in the using process, simultaneously avoid the electric leakage problem between the silicification layer and the substrate, and improve the reliability and the quality of the formed semiconductor device property.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the barrier layer covers a part of the side wall of the fin part, and the surface of the barrier layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the barrier layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, the performance of the semiconductor structure formed by the prior art is poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which can improve the performance of the semiconductor device.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, and forming a source-drain doping layer on the substrate; forming a dielectric layer on the source-drain doped layer; sequentially etching the dielectric layer, the source-drain doping layer positioned at the bottom of the dielectric layer and the substrate with partial thickness positioned at the bottom of the source-drain doping layer to form a contact hole; forming a protective layer on the bottom of the contact hole and the side wall of the contact hole; forming a sacrificial layer on the protective layer at the bottom of the contact hole, wherein the sacrificial layer covers part of the protective layer on the side wall of the contact hole; removing the protective layer uncovered by the sacrificial layer; and removing the sacrificial layer.
Optionally, the thickness of the protective layer is 2nm to 8nm.
Optionally, the protective layer is made of silicon nitride, silicon oxynitride, or silicon carbonitride.
Optionally, the process of forming the protective layer is a chemical vapor deposition process or an atomic layer deposition process.
Optionally, the aspect ratio of the contact hole is 5.
Optionally, the process for forming the contact hole is a dry etching process or a wet etching process.
Optionally, the substrate is further provided with a fin portion structure and a dummy gate structure crossing the fin portion structure, the source-drain doping layer is located in the fin portion structure on two sides of the dummy gate structure, the dielectric layer covers a side wall of the dummy gate structure, and the top surface of the dielectric layer is flush with the top surface of the dummy gate structure.
Optionally, the fin structure includes a first fin layer and a second fin layer, before the source-drain doping layer is formed, a portion of the bottom of the dummy gate structure is etched to form a first fin layer, and an inner sidewall is formed on a sidewall of the first fin layer.
Optionally, after removing the sacrificial layer, the method further includes: forming a silicide layer on the protective layer; and forming a conductive layer on the silicification layer, wherein the contact hole is filled with the conductive layer.
Accordingly, the present invention also provides a semiconductor device comprising: a substrate; the source-drain doping layer is positioned on the substrate; the dielectric layer is positioned on the source-drain doping layer; the contact holes are positioned in the dielectric layer, the source-drain doped layer at the bottom of the dielectric layer and the substrate at the bottom of the source-drain doped layer; and the protective layer is positioned at the bottom and part of the side wall of the contact hole.
Optionally, the thickness of the protective layer ranges from 2nm to 8nm.
Optionally, the depth ratio of the contact hole is 5.
Optionally, the protective layer is made of silicon nitride, silicon oxynitride, or silicon carbonitride.
Optionally, the substrate further includes a fin structure and a dummy gate structure crossing the fin structure, the source-drain doping layer is located in the fin structure on both sides of the dummy gate structure, the dielectric layer covers a sidewall of the dummy gate structure, and a top surface of the dielectric layer is flush with a top surface of the dummy gate structure.
Optionally, the fin structure includes a plurality of first fin modification layers overlapped along a normal direction of the surface of the substrate, and a second fin modification layer located between two adjacent first fin modification layers.
Optionally, the method further includes: and the inner side walls are positioned on the side walls of the first correction fin part layers, and are positioned between the adjacent second fin part layers and between the substrate and the second fin part layers.
Optionally, the method further includes: a silicide layer on the protective layer.
Optionally, the method further includes: and the conducting layer is positioned on the silicification layer and is filled in the contact hole.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
after the contact hole is formed, the protective layer is formed on the bottom and part of the side wall of the contact hole, on one hand, by forming the contact hole with deeper depth, when the conductive layer is formed in the contact hole subsequently, the contact area between the conductive layer and the source drain doping layer is increased, the contact resistance between the source drain doping layer and the conductive layer on the source drain doping layer is reduced, the electrical property of the semiconductor device is improved, the heat effect of the semiconductor device in the using process is reduced, meanwhile, the protective layer is formed on the bottom and part of the side wall of the contact hole, when the silicification layer is formed on the protective layer subsequently, the problem of electric leakage between the silicification layer and the substrate is avoided, and the reliability and the quality of the performance of the formed semiconductor device are improved.
Drawings
Fig. 1 to 5 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment;
fig. 6 to 19 are schematic structural views of a process of forming a semiconductor device in the first embodiment of the present invention;
fig. 20 to 24 are schematic structural views of a process of forming a semiconductor device in a second embodiment of the present invention.
Detailed Description
The performance of the semiconductor device is poor, and the following description will be made with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a fin 101, and a dummy gate structure 102 is formed on the substrate 100 and crosses the fin 101.
Referring to fig. 2, the fin 101 on both sides of the dummy gate structure 102 is etched, and a groove 103 is formed in the fin 101.
Referring to fig. 3, source and drain doped layers 104 are formed in the recess 103.
Referring to fig. 4, a dielectric layer 105 is formed on the source-drain doping layer 104 and the sidewall of the dummy gate structure 102, and a top surface of the dielectric layer 105 is flush with a top surface of the dummy gate structure 102.
Referring to fig. 5, the dielectric layer 105 is etched until the source-drain doping layer 104 is exposed, a contact hole (not shown in the figure) is formed, a silicide layer 106 is formed at the bottom of the contact hole, a metal layer 107 is formed on the silicide layer 106, the contact hole is filled with the metal layer 107, and the top surface of the contact hole is flush with the top surface of the dummy gate structure 102.
The inventor finds that: the semiconductor device formed by the forming method has the advantages that on one hand, the contact resistance between the source drain doping layer and the metal layer is too large, the semiconductor device is easy to generate heat, and the electrical performance of the semiconductor device is influenced; on the other hand, the phenomenon of electric leakage is easy to occur between the silicide layer and the substrate, and the use of the semiconductor device is limited.
The inventor researches and discovers that: the dielectric layer, the source-drain doping layer positioned at the bottom of the dielectric layer and the substrate with partial thickness positioned at the bottom of the source-drain doping layer are etched in sequence to form a contact hole with deeper depth, so that contact resistance between the metal layer and the source-drain doping layer is reduced in the subsequent process, a protective layer is formed at the bottom of the contact hole, and after a silicification layer is formed on the protective layer, the silicification layer is isolated from the substrate, so that electric leakage between the substrate and the silicification layer is avoided, the electrical property and the quality of a semiconductor device are improved, and the application range of the semiconductor device is favorably expanded.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 19 are schematic structural views of a process of forming a semiconductor device in the first embodiment of the present invention.
First embodiment
Referring to fig. 6 to 7, a substrate 200 is provided.
Fig. 7 isbase:Sub>A cross-sectional view of fig. 6 taken along linebase:Sub>A-base:Sub>A.
In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the material of the substrate 200 may also be single-crystal silicon germanium, a semiconductor-on-insulator structure including an insulator and a semiconductor material layer on the insulator, wherein the semiconductor material layer includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, and the like.
In this embodiment, the substrate 200 further has a fin structure thereon.
In this embodiment, the fin structure includes a plurality of first fin layers 201 and a second fin layer 202 located between two adjacent first fin layers 201.
In this embodiment, the first fin layers 201 are overlapped along the normal direction of the surface of the substrate 200, and the second fin layers 202 are located between the adjacent first fin layers 201 along the normal direction of the surface of the substrate 200.
The forming method of the fin structure comprises the following steps: forming a fin material film (not shown) on the substrate 200, wherein the fin material film comprises a plurality of layers of first fin films (not shown) overlapped along the surface normal direction of the substrate 200 and a second fin film (not shown) positioned in two adjacent layers of the first fin films; forming a patterned layer (not shown) on the fin material film; and etching the fin material film and the substrate with partial thickness by using the patterned layer as a mask to form the fin structure, wherein the fin structure comprises a plurality of first fin layers 201 overlapped along the normal direction of the surface of the substrate and a second fin layer 202 positioned between the two adjacent first fin layers 201.
The material of the first fin portion layer 201 is different from that of the second fin portion layer 202, and the purpose of the material is to remove the first fin portion layer 201 when a gate structure is formed subsequently, so that the material of the first fin portion layer 201 and the material of the second fin portion layer 202 which are made of different materials has a larger etching selection ratio, and the damage to the second fin portion layer 202 in the process of removing the first fin portion layer 201 is reduced.
In this embodiment, the material of the first fin layer 201 is monocrystalline silicon, and the material of the second fin layer 202 is monocrystalline silicon germanium; in other embodiments, the material of the first fin layer is single crystal silicon germanium, and the material of the second fin layer is single crystal silicon.
The material of the first fin layer 201 is different from that of the second fin layer 202, and another purpose is that the first fin layer 201 needs to be removed when a gate structure is formed subsequently, so that the gate structure surrounding the second fin layer 202 can be formed, the effective width of the gate structure is maximized, and the control capability of the gate structure is improved.
In this embodiment, the substrate 200 further has a dummy gate structure crossing the fin structure, and the dummy gate structure covers part of the sidewall and part of the top surface of the fin structure.
In this embodiment, before forming the dummy gate structure, forming an isolation layer 218 on the substrate 200, where the isolation layer 218 covers a portion of the sidewall of the fin structure.
In this embodiment, the top surface of the isolation layer 218 is flush with the bottom surface of the first fin layer 201.
The dummy gate structure includes: the structure comprises a gate dielectric layer 203 positioned on the fin structure, a dummy gate layer 204 positioned on the gate dielectric layer 203, and a hard mask layer 205 positioned on the dummy gate layer 204.
In this embodiment, a sidewall spacer 206 is formed on the sidewall of the dummy gate structure, that is, the sidewall spacer 206 is formed on the sidewalls of the dummy gate layer 204 and the hard mask layer 205.
In other embodiments, the sidewall spacers 206 may not be formed on the sidewalls of the dummy gate structures.
In this embodiment, the dummy gate layer 204 is made of polysilicon; in other embodiments, the material of the dummy gate layer 204 may also be amorphous silicon.
In this embodiment, the hard mask layer 205 is made of silicon nitride; in other embodiments, the material of the protective layer may also use silicon oxide.
The forming method of the side wall 206 includes: forming a side wall material layer (not shown) on the top surface of the gate dielectric layer 203, the side wall of the dummy gate layer 204, the side wall of the hard mask layer 205 and the top surface; and etching back the side wall material layer until the hard mask layer 205 and the top surface of the gate dielectric layer 203 are exposed, thereby forming the side wall 206.
The forming process of the side wall material layer is one or a combination of a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
The material of the sidewall spacers 206 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the sidewall spacers 206 are used to define the position of the subsequent source/drain doping layer.
Forming a source-drain doped layer on the substrate 200, please refer to fig. 8 to 11 for a specific forming process.
Referring to fig. 8, the fin structure on both sides of the sidewall 206 is etched, and a groove 207 is formed in the fin structure.
In this embodiment, the groove 207 serves to provide a space for the source-drain doped layer to be formed subsequently.
The process for etching the fin structure comprises the following steps: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the bottom of the groove 207 exposes the substrate 200.
In this embodiment, the process for etching the fin structure is an anisotropic dry etching process, and the parameters of the dry etching process include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
Referring to fig. 9, a portion of the first fin layer 201 at the bottom of the dummy gate structure is etched to form a first modified fin layer 208, and fin recesses 209 are formed on two sides of the first modified fin layer 208.
In this embodiment, the fin recess 209 is formed to provide space for the subsequent formation of the inner sidewalls.
In this embodiment, the process of removing the first fin layer 201 with a partial thickness is a wet etching process. The etching solution for wet etching has a good selection ratio to monocrystalline silicon and monocrystalline germanium-silicon, and can ensure that the morphology of the monocrystalline germanium-silicon is not influenced while the monocrystalline silicon is removed. The parameters of the wet etching process comprise: the etching solution is a tetramethylammonium hydroxide solution, the temperature is 20-80 ℃, and the volume percentage of the tetramethylammonium hydroxide solution is 10-80%.
Referring to fig. 10, inner sidewalls 210 are formed on the sidewalls of the first modified fin layer 208.
In this embodiment, the inner sidewall spacers 210 are made of silicon nitride; in other embodiments, the material of the inner sidewall spacers 210 is silicon oxide, silicon carbide, or silicon oxycarbide.
In this embodiment, the inner sidewall 210 is formed to isolate the work function layer and the source-drain doped layer in the gate structure, increase the distance between the two layers, and reduce the parasitic capacitance between the two layers, thereby improving the performance and quality of the finally formed semiconductor device.
In this embodiment, the inner sidewall 210 is formed in the fin recess 209, the fin recess 209 is filled with the inner sidewall 210, and a sidewall of the inner sidewall 210 is flush with a sidewall of the second fin layer 202.
In this embodiment, the step of forming the inner sidewall 210 includes: forming initial inner sidewall layers on the sidewalls and the bottom of the groove 207, the sidewalls of the first modified fin layer 208, and the sidewalls and the top surface of the dummy gate structure; the initial inner sidewall layer is etched back until the bottom surface of the groove 207, the top surface of the hard mask layer 205 and the sidewalls of the sidewalls 206 are exposed, thereby forming the inner sidewalls 210.
The process for back etching the initial inner side wall layer comprises an anisotropic dry etching process or an anisotropic wet etching process; in this embodiment, the process of etching back the initial barrier layer 210 uses an anisotropic dry etching process, and the anisotropic dry etching process is involved inThe method comprises the following steps: the etching gas comprises CF 4 And CH 2 F 2 Wherein CF 4 The flow rate of the catalyst is 50sccm to 500sccm, CH 2 F 2 The flow rate of (2) is 30-100 sccm.
Referring to fig. 11, a source-drain doped layer 211 is formed in the recess 207.
In this embodiment, the forming process of forming the source-drain doping layer 211 includes an epitaxial growth process; the process of doping the source and drain ions in the source and drain doping layer 211 includes an in-situ doping process.
When the semiconductor device is a P-type device, the source-drain doping layer 211 is made of the following materials: silicon, germanium, or silicon germanium; the source and drain ions are P-type ions and comprise boron ions and BF 2- Ions or indium ions; when the semiconductor device is an N-type device, the source-drain doping layer 211 is made of the following materials: silicon, gallium arsenide, or indium gallium arsenide; the source and drain ions are N-type ions and comprise phosphorus ions or arsenic ions.
Referring to fig. 12, a dielectric layer 212 is formed on the source/drain doping layer 211.
In this embodiment, the dielectric layer 212 is made of silicon oxide; in other embodiments, the material of the dielectric layer 212 may also be silicon nitride, silicon carbide, silicon oxynitride, or the like.
In this embodiment, the dielectric layer 212 covers the source-drain doping layer 211 and the sidewall of the dummy gate structure, and exposes the top surface of the dummy gate structure.
The forming method of the dielectric layer 212 comprises the following steps: forming an initial dielectric layer (not shown) on the source-drain doping layer 211 and the dummy gate structure, wherein the initial dielectric layer covers the top surface and the sidewall surface of the dummy gate structure; and flattening the initial dielectric layer until the surface of the hard mask layer 205 at the top of the pseudo gate structure is exposed, and forming the dielectric layer 212.
In this embodiment, the process of forming the dielectric layer 212 is a chemical vapor deposition process; in other embodiments, the dielectric layer 212 may be formed by a physical vapor deposition process.
In this embodiment, the top surface of the dielectric layer 212 is flush with the top surface of the dummy gate structure, i.e., flush with the top surface of the hard mask layer 205.
Referring to fig. 13, the dielectric layer 212, the source-drain doping layer 211 located at the bottom of the dielectric layer 212, and the substrate 200 located at the bottom of the source-drain doping layer 211 and having a partial thickness are sequentially etched to form the contact hole 213.
In this embodiment, the process of forming the contact hole 213 is a dry etching process; in other embodiments, a wet etching process may also be employed.
In this embodiment, the aspect ratio of the contact hole 213 is 5; when the aspect ratio of the contact hole 213 is smaller than 5, the feature size of the contact hole 213 is too large, which may result in too large parasitic capacitance from the contact hole 213 to a subsequently formed gate structure and may easily form a short circuit with the gate structure); when the aspect ratio of the contact hole 213 is greater than 60, the metal layer is difficult to fill when filling the metal layer in the contact hole 213, which increases the process difficulty.
In this embodiment, the contact hole 213 extends into the substrate 200 at the bottom of the source-drain doping layer 211, so that the formed contact hole 213 has a deeper depth, and thus when a silicide layer and a conductive layer are formed in the contact hole 213 in the following process, because the contact area between the source-drain doping layer 211 and the conductive layer is increased, the contact resistance between the source-drain doping layer 211 and the conductive layer is reduced, the thermal effect of the semiconductor device in the use process is reduced, and the use performance of the semiconductor device is enhanced.
Referring to fig. 14, a passivation layer 214 is formed on the bottom of the contact hole 213 and the sidewall of the contact hole 213.
In this embodiment, the protection layer 214 extends to the top surface of the dielectric layer 212 and the top surface of the hard mask layer 205.
In this embodiment, the material of the protection layer 214 is silicon nitride; in other embodiments, the material of the protection layer 214 may also be silicon oxynitride, silicon carbonitride, or the like.
In this embodiment, the process of forming the protection layer 214 is an atomic layer deposition process; in other embodiments, the protective layer 214 may be formed by a chemical vapor deposition process.
In this embodiment, the protective layer 214 is formed by using an atomic layer vapor deposition process, so that the formed protective layer 214 has good step coverage capability, and the formed protective layer 214 has good compactness and uniform thickness.
In this embodiment, the thickness of the protection layer 214 is 2nm to 8nm; when the thickness of the protection layer 214 is less than 2nm, the protection layer 214 cannot effectively control and prevent the leakage current between the metal contact hole and the substrate; when the thickness of the protective layer 214 is greater than 8nm, this reduces the amount of conductive layer that can be filled in the contact hole 213, resulting in higher resistance.
In this embodiment, the thickness of the protective layer 214 is in a direction extending along the normal direction of the surface of the substrate 200.
Referring to fig. 15, a sacrificial layer 215 is formed on the protection layer 214 at the bottom of the contact hole 213, and the sacrificial layer 215 covers a portion of the protection layer 214 on the sidewall of the contact hole 213.
In this embodiment, the material of the sacrificial layer 215 is a bottom anti-reflective coating material.
In this embodiment, the sacrificial layer 215 is formed by a spin coating process.
In this embodiment, the top surface of the sacrificial layer 215 is lower than or equal to the bottom surface of the second fin layer 202 at the bottom layer.
Referring to fig. 16, the protection layer 214 uncovered by the sacrificial layer 215 is removed.
In this embodiment, the method for removing the uncovered protective layer 214 by etching is a dry etching process; in other embodiments, a wet etching process may be used to remove the protection layer 214.
In this embodiment, since the protection layer 214 on the bottom and part of the sidewall of the contact hole 213 is covered by the sacrificial layer 215, it is not etched away in the etching process, which provides a preparation for subsequently isolating the substrate 200 from the silicide layer, and prevents the leakage phenomenon between the silicide layer and the substrate.
Referring to fig. 17, the sacrificial layer 215 is removed.
In this embodiment, the process of removing the sacrificial layer 215 is an ashing process; in other embodiments, the sacrificial layer 215 may be removed by an etching process.
In this embodiment, the material of the sacrificial layer 215 is a bottom anti-reflective coating material, so that when the sacrificial layer 215 is removed, the protective layer 214 at the bottom is not damaged.
Referring to fig. 18, a silicide layer 216 is formed on the protection layer 214 at the bottom of the contact hole 213.
Before the conductive layer is formed in the contact hole 213, a silicide layer is formed at the bottom of the contact hole 213, so that the lower series resistance, the delay of the contact resistance and the operation speed of the circuit can be improved.
In this embodiment, before forming the silicide layer, the protective layer 214 is formed on the bottom and a part of the sidewall of the contact hole 213, and the protective layer 214 is used to isolate the substrate 200 from the silicide layer formed subsequently, thereby effectively preventing the leakage between the substrate 200 and the silicide layer and improving the reliability of the performance of the semiconductor device.
Referring to fig. 19, the contact hole 213 is filled with a conductive layer 217.
In this embodiment, the conductive layer 217 is made of tungsten; in other embodiments, the material of the conductive layer 217 may also be copper, titanium, or the like.
In this embodiment, the conductive layer 217 is used to electrically connect the transistor to an overlying metal layer.
Accordingly, the present invention also provides a semiconductor device comprising: a substrate 200; the fin structure is positioned on the substrate 200 and comprises a plurality of first correction fin layers 208 which are overlapped along the surface normal direction of the substrate 200 and a second fin layer 202 positioned between two adjacent first correction fin layers 208; a dummy gate structure on the substrate and spanning the fin structure, the dummy gate structure comprising: a gate dielectric layer 203 located on the fin structure, a dummy gate layer 204 located on the gate dielectric layer 203, a hard mask layer 205 located on the dummy gate layer 204, and a sidewall 206 located on the sidewall of the dummy gate layer 204 and the hard mask layer 205; the groove 207 is positioned in the fin portion structures on two sides of the dummy gate structure, and the bottom of the groove is exposed out of the substrate 200; fin recesses 209 on both sides of the first modified fin layer 208; inner sidewalls 210 located on both sides of the first modified fin portion layer 208 and filling the fin portion grooves 209; the source-drain doping layer 211 is positioned on the substrate 200; a dielectric layer 212, which is located on the source-drain doping layer 211 and has a top surface flush with the top surface of the hard mask layer 205; the contact holes 213 are positioned in the dielectric layer 212, the source-drain doping layer 211 at the bottom of the dielectric layer 212 and the substrate 200 at the bottom of the source-drain doping layer 211; a protective layer 214 on the bottom and a portion of the sidewall of the contact hole 213; a silicide layer 216 on the cap layer 214; a conductive layer 217 is located over the silicide layer 216 and fills the contact hole 213.
In this embodiment, the material of the protection layer 214 is silicon nitride; in other embodiments, the protective layer 214 is silicon oxynitride or silicon carbonitride or boron doped silicon carbonitride.
In this embodiment, the bottom of the contact hole 213 extends into the substrate 200, so that the depth of the formed contact hole 213 is increased, the contact area between the source-drain doping layer 211 and the conductive layer 217 is increased, and the contact resistance between the source-drain doping layer 211 and the conductive layer 217 is reduced, thereby increasing the operation speed of the finally formed semiconductor device, reducing the heating effect, and enhancing the use performance of the semiconductor device.
In this embodiment, the thickness of the protection layer 214 is in a range from 2nm to 8nm, and when the thickness of the protection layer 214 is less than 2nm, the protection layer 214 cannot effectively control and prevent the leakage current between the metal contact hole and the substrate; when the thickness of the protective layer 214 is greater than 8nm, this reduces the amount of conductive layer that can be filled in the contact hole 213, resulting in higher resistance.
In this embodiment, the protection layer 214 is used to isolate the substrate 200 from the silicide layer 216, so as to prevent a leakage phenomenon between the substrate 200 and the silicide layer 216, and improve the performance of the semiconductor device.
In this embodiment, the depth ratio of the contact hole is 5 to 60, and when the aspect ratio of the contact hole 213 is smaller than 5; when the aspect ratio of the contact hole 213 is greater than 60, the metal layer is difficult to fill when filling the metal layer in the contact hole 213, which increases the difficulty of the process.
Second embodiment
The present embodiment differs from the first embodiment in that: the fin structure is different from that of the first embodiment.
Referring to fig. 20, a substrate 300 is provided, and a fin structure 301 is formed on the substrate 300 by etching a portion of the thickness of the substrate 300.
Referring to fig. 21, an isolation layer 302 is formed on the substrate 300, and the isolation layer 302 covers a portion of the sidewall of the fin structure 301.
Referring to fig. 22 to 23, a dummy gate structure crossing the fin structure 301 is formed on the substrate 300.
Fig. 23 isbase:Sub>A cross-sectional view of fig. 22 taken along section linebase:Sub>A-base:Sub>A.
The dummy gate structure includes: the semiconductor structure comprises a gate dielectric layer 303 positioned on the fin structure, a dummy gate layer 304 positioned on the gate dielectric layer 303, a hard mask layer 305 positioned on the dummy gate layer 304, and the side wall 306 positioned on the side walls of the dummy gate layer 304 and the hard mask layer 305.
Referring to fig. 24, the fin structure 301 on both sides of the dummy gate structure is etched, a groove (not shown) is formed in the fin structure 301, and a source-drain doping layer 307 is formed in the groove.
The process from the formation of the source and drain doped layers to the formation of the conductive layer in the contact hole is the same as in the first embodiment, and is described in detail with reference to fig. 12 to 19, which will not be redundantly described here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor device, comprising:
providing a substrate, and forming a source-drain doping layer on the substrate;
forming a dielectric layer on the source-drain doped layer;
sequentially etching the dielectric layer, the source-drain doping layer positioned at the bottom of the dielectric layer and the substrate with partial thickness positioned at the bottom of the source-drain doping layer to form a contact hole;
forming a protective layer on the bottom of the contact hole and the side wall of the contact hole;
forming a sacrificial layer on the protective layer at the bottom of the contact hole, wherein the sacrificial layer covers part of the protective layer on the side wall of the contact hole;
removing the protective layer uncovered by the sacrificial layer;
removing the sacrificial layer;
forming a silicide layer on the protective layer; and forming a conductive layer on the silicide layer, wherein the contact hole is filled with the conductive layer, and the protective layer electrically isolates the silicide layer from the substrate.
2. The forming method of claim 1, wherein a thickness of the protective layer is 2nm to 8nm.
3. The method of claim 1, wherein the protective layer is made of silicon nitride, silicon oxynitride, or silicon carbonitride.
4. The method of forming of claim 1, wherein the process of forming the protective layer is a chemical vapor deposition process or an atomic layer deposition process.
5. The method according to claim 1, wherein an aspect ratio of the contact hole is 5 to 1 to 60.
6. The forming method of claim 1, wherein a process of forming the contact hole is a dry etching process or a wet etching process.
7. The method according to claim 1, wherein the substrate further comprises a fin structure and a dummy gate structure crossing the fin structure, the source-drain doping layer is located in the fin structure on two sides of the dummy gate structure, the dielectric layer covers a side wall of the dummy gate structure, and a top surface of the dielectric layer is flush with a top surface of the dummy gate structure.
8. The method of claim 7, wherein the fin structure comprises a first fin layer and a second fin layer, wherein a portion of the first fin layer at the bottom of the dummy gate structure is etched to form a first modified fin layer before forming the source-drain doping layer, and an inner sidewall is formed on a sidewall of the first modified fin layer.
9. A semiconductor device, comprising:
a substrate;
the source-drain doping layer is positioned on the substrate;
the dielectric layer is positioned on the source-drain doping layer;
the contact holes are positioned in the dielectric layer, the source-drain doped layer at the bottom of the dielectric layer and the substrate at the bottom of the source-drain doped layer;
the protective layer is positioned on the bottom and part of the side wall of the contact hole;
the silicification layer is positioned on the protective layer;
and the conducting layer is positioned on the silicification layer and filled in the contact hole, and the protective layer electrically isolates the silicification layer from the substrate.
10. The semiconductor device according to claim 9, wherein a thickness of the protective layer is in a range of 2nm to 8nm.
11. The semiconductor device according to claim 9, wherein a depth ratio of the contact hole is 5 to 1 to 60.
12. The semiconductor device according to claim 9, wherein a material of the protective layer is silicon nitride, silicon oxynitride, or silicon carbonitride.
13. The semiconductor device according to claim 9, wherein the substrate further comprises a fin structure and a dummy gate structure crossing the fin structure, the source-drain doping layer is located in the fin structure on both sides of the dummy gate structure, the dielectric layer covers a sidewall of the dummy gate structure, and a top surface of the dielectric layer is flush with a top surface of the dummy gate structure.
14. The semiconductor device of claim 13, wherein the fin structure comprises a plurality of first modified fin layers overlapping in a direction normal to the surface of the substrate, and a second fin layer located between two adjacent first modified fin layers.
15. The semiconductor device according to claim 14, further comprising: and the inner side walls are positioned on the side walls of the first correction fin part layers, and are positioned between the adjacent second fin part layers and between the substrate and the second fin part layers.
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