CN103730494A - Structure of semiconductor power device for chip scale package - Google Patents
Structure of semiconductor power device for chip scale package Download PDFInfo
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- CN103730494A CN103730494A CN201210382123.7A CN201210382123A CN103730494A CN 103730494 A CN103730494 A CN 103730494A CN 201210382123 A CN201210382123 A CN 201210382123A CN 103730494 A CN103730494 A CN 103730494A
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- 239000004065 semiconductor Substances 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 188
- 239000002184 metal Substances 0.000 claims abstract description 188
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000002019 doping agent Substances 0.000 claims description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- 239000010703 silicon Substances 0.000 claims description 25
- 238000009825 accumulation Methods 0.000 claims description 24
- 230000005669 field effect Effects 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 16
- 238000001459 lithography Methods 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 14
- 238000005260 corrosion Methods 0.000 claims description 12
- 230000007797 corrosion Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910000838 Al alloy Inorganic materials 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 6
- 229910003978 SiClx Inorganic materials 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 238000007654 immersion Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 30
- 238000009792 diffusion process Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000007773 growth pattern Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
Abstract
The invention discloses a novel structure of a trench power MOSFET device for chip scale package. The novel structure is characterized in that a source electrode metal pad layer, a drain electrode metal pad layer and a grid electrode metal pad layer of the trench power MOSFET device are arranged on the surface of a chip, a trench MOSFET structure is arranged at the bottom of the source electrode metal pad layer, an LDMOS structure is arranged at the bottom of the drain electrode metal pad layer and the bottom of the grid electrode metal pad layer, and a drain region is connected to a substrate through a deep conducting trench; when connection is carried out, currents can flow to the source electrode metal pad layer from the drain electrode metal pad layer or the grid electrode metal pad layer through two paths; according to the first path, the currents longitudinally flow to the portion, corresponding to drain electrodes or grid electrodes, of the substrate through the deep conducting trench, then transversely flow to the portion, corresponding to source electrodes, of the substrate, and upwards flow to the source electrode metal pad layer through the substrate, an epitaxial layer, a conducting channel and a metal plug; according to the second path, the currents flow to the drain region arranged at the bottom of the drain electrode metal pad layer or the grid electrode metal pad layer from the drain electrode metal pad layer, and then transversely flow to the source electrode metal pad layer through the conducting channel and the metal plug.
Description
Technical field
The present invention relates to semiconductor power device technology field, specifically, relate to a kind of new construction of groove-type power FET device of chip size packages.
Background technology
Physical structure from device, the conducting channel of power field effect transistor (Power MOSFET) can be divided into longitudinally with horizontal, it has the features such as low forward voltage drop, high conversion speed, easy grid-control system, in low medium voltage electricity electronic application, become a kind of important semiconductor device, at present, power field effect transistor has been widely used in each electron-like, communication product, computer, consumer appliances and automotive electronics etc. as device for power switching.
The conducting channel of groove-type power field-effect transistor (Trench Power MOSFET) is in vertical direction, so compare with common horizontal power field effect transistor, under equal area, there is lower conducting resistance, because it has advantages of structural efficiently and on-resistance characteristics is low, groove type power field-effect transistor is controlled and is widely used with electronic device as power supply.
The nineties later stage, commercial groove-type power field-effect transistor product starts batch process, at that time, the cell size of device is about 4.0um left and right, be developed to about 2010, minimum cell size has been contracted to 0.8um, and the conducting resistance of device is improved greatly, and chip size greatly reduces.Trend along with consumption electronic product microminiaturization, the requirement of the encapsulation of power field effect transistor product is also become to microminiaturized, from early stage surface attaching type encapsulation (Surface Mount) S08, then be developed to SOT-23, SC-70, SC75A, SC89 etc. are to current chip size packages (Chip Scale Package, simple is CSP), encapsulate shared space more and more little.Chip size packages (CSP) requires the grid of device, source electrode and drain electrode are all on the surface of chip, the grid of groove-type power field-effect transistor, source electrode on the surface of chip and drain electrode at the back side of chip, in order to make groove-type power field-effect transistor, can make chip size packages (CSP), existing technology is that drain electrode is caused to the drain region metal bed course epi-layer surface from the back side of substrate, and Fig. 1 expresses the plan structure as the groove-type power field-effect transistor metal line of chip size packages (CSP); Fig. 2 expresses Structure of cross section, and its shortcoming is there is no FET unit under drain region metal bed course and gate metal bed course, and in other words, drain region metal bed course and gate metal bed course place chip area are only used as metal bed course, are not utilized attentively.
Summary of the invention
The present invention has overcome the shortcoming of existing device architecture, the new structure of the groove-type power FET device of a kind of chip size packages (CSP) is provided, its chip size packages groove-type power field-effect transistor before more effectively utilizes chip area, thereby has increased the ratio of performance to price of device.
In order to solve the problems of the technologies described above, the present invention improves the service efficiency of device chip area by following design:
Chip size packages (CSP) requires the source metal bed course of device, drain metal bed course and gate metal bed course are on the surface of chip, the structure of new device is: under source metal bed course, be trench field effect transistor structure, under drain metal bed course and gate metal bed course, be LDMOS structure and have conduction deep trench the drain region of epi-layer surface is connected to substrate.
Fig. 3 expresses the Structure of cross section of this new device under source metal bed course and under drain metal bed course, when break-over of device, electric current flows to source metal bed course from drain metal bed course, mainly contain two paths: the first path is that electric current longitudinally flows to the metal level of substrate and substrate back from drain metal bed course through conduction deep trench, then laterally along the metal level of substrate and substrate back, flow to the drain electrode source-substrate on side and the metal level of substrate back, then the substrate of upwards flowing through, epitaxial loayer, conducting channel, metal plug, source metal bed course; The second path is to flow to the drain region drain metal bed course from drain metal bed course, then the conducting channel of laterally flowing through, metal plug is to source metal bed course, and Fig. 4 is that Structure of cross section is expressed electric current the first path, Fig. 5 is the plan structure of CSP metal line, expresses electric current the second path.
Fig. 6 expresses the Structure of cross section of this new device under source metal bed course and under gate metal bed course, electric current flows to source metal bed course from drain metal bed course, mainly contain two paths: the first path is that electric current flows to from drain metal bed course the metal plug draining gate metal bed course, then the conduction of longitudinally flowing through deep trench flows to the metal level of substrate and substrate back, then laterally along the metal level of substrate and substrate back, flow to the source-substrate on grid side and the metal level of substrate back, then the substrate of upwards flowing through, epitaxial loayer, conducting channel, metal plug, source metal bed course, the second path is that electric current laterally flows to from drain metal bed course the metal plug draining gate metal bed course, the conducting channel of then laterally flowing through, and source region metal plug is to source metal bed course, Fig. 7 is that Structure of cross section is expressed electric current the first path, and Fig. 8 is the plan structure of CSP metal line, expresses electric current the second path.
Compared with prior art, the invention has the beneficial effects as follows:
Adopt the new device structure of chip size packages groove-type power field-effect transistor of the present invention can more effectively utilize chip area, can also improve the advantage index (Ron x Qg) of device electrical characteristic, thereby increase the ratio of performance to price of device.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, for explaining the present invention, is not construed as limiting the invention together with embodiments of the present invention, in the accompanying drawings:
Fig. 1 is the plan structure schematic diagram of the trench field effect transistor metal line of chip size packages;
Fig. 2 is the Structure of cross section schematic diagram of the trench field effect transistor of chip size packages;
Fig. 3 is the trench field effect transistor of chip size packages of the present invention Structure of cross section schematic diagram under source metal bed course and under drain metal bed course;
Fig. 4 is the Structure of cross section schematic diagram in electric current first path of the present invention between source metal bed course and drain metal bed course;
Fig. 5 is the plan structure schematic diagram in electric current second path of the present invention between source metal bed course and drain metal bed course;
Fig. 6 is the Structure of cross section schematic diagram of the present invention under source metal bed course and under gate metal bed course;
Fig. 7 is the Structure of cross section schematic diagram in electric current first path of the present invention between source metal bed course and gate metal bed course;
Fig. 8 is the plan structure schematic diagram in electric current second path of the present invention between source metal bed course and drain metal bed course;
Fig. 9 be the embodiment of the present invention 1 at drain metal bed course place, expose deep trench perforate schematic diagram;
Figure 10 be the embodiment of the present invention 1 at drain metal bed course place, form deep trench schematic diagram;
Figure 11 is that the N-type highly doped polysilicon that forms at drain metal bed course place of the embodiment of the present invention 1 is filled deep trench schematic diagram;
Figure 12 be the embodiment of the present invention 1 at source metal bed course place, form a plurality of gate trench schematic diagrames;
Figure 13 is schematic diagram after the highly doped polysilicon of the embodiment of the present invention 1 deposition;
Figure 14 is the embodiment of the present invention 1 schematic diagram after drain metal bed course place forms polysilicon gate;
Figure 15 is that the embodiment of the present invention 1 forms p type island region schematic diagram;
Figure 16 injects N-type dopant schematic diagram to silicon chip surface after the embodiment of the present invention 1 forms spacer;
Figure 17 is that the embodiment of the present invention 1 forms N-type lightly doped drain (LDD) schematic diagram after by High temperature diffusion operation;
Figure 18 is that the embodiment of the present invention 1 sees through inter-level dielectric to silicon chip surface injection N-type dopant schematic diagram;
Figure 19 is that the embodiment of the present invention 1 forms N-type source region schematic diagram after by High temperature diffusion operation;
Figure 20 is that the injection P type dopant of the embodiment of the present invention 1 is to contact hole channel bottom schematic diagram;
Figure 21 is the schematic diagram after metal plug of filling out of the embodiment of the present invention 1;
Figure 22 is the second layer inter-level dielectric schematic diagram of the embodiment of the present invention 1;
Figure 23 is that the embodiment of the present invention 1 deposits one deck aluminium alloy schematic diagram on the surface of this device;
Figure 24 is that the embodiment of the present invention 2 does not have the Structure of cross section schematic diagram of p type island region at place, drain region;
Figure 25 is that the embodiment of the present invention 3 forms N-type source region schematic diagram after by High temperature diffusion operation;
Figure 26 is that the embodiment of the present invention 3 is injected N-type dopant schematic diagram to deep trench;
Figure 27 is that the embodiment of the present invention 3 is injected P type dopant to contact hole channel bottom schematic diagram;
Figure 28 is the schematic diagram after metal plug of filling out of the embodiment of the present invention 3;
Figure 29 is the second layer inter-level dielectric schematic diagram of the embodiment of the present invention 3;
Figure 30 is that the embodiment of the present invention 3 deposits one deck aluminium alloy schematic diagram on the surface of this device.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein, only for description and interpretation the present invention, is not intended to limit the present invention.
The preparation method of the groove-type power field-effect transistor of the chip size packages of a kind of new device structure of the present invention (CSP), comprise the following steps: first epitaxial loayer is placed in to highly doped substrate top, at metal bed course place, drain region, form conduction deep trench the drain region of epi-layer surface is connected to substrate, the mode of utilizing trench mask to corrode on epitaxial loayer at metal bed course place, source region and forming a plurality of gate trenchs and grow by heat, the sidewall exposing at groove and bottom, form the thin grid oxic horizon of one deck with the upper surface of epitaxial loayer, then the polysilicon that deposits N-type high dopant is with filling groove and cover end face, utilize polysilicon mask step at metal bed course place, drain region, to form the polysilicon gate of LDMOS, polycrystalline silicon grid layer can be metallized, as formed cobalt SiClx (CoSi) on polysilicon layer surface, titanizing silicon (TiSi) or tungsten SiClx (WSi) etc., then silicon chip surface is injected to P type dopant and N-type dopant formation HeNXing lightly doped drain, p type island region (LDD) district, accumulation ground floor inter-level dielectric from the teeth outwards, then by contact hole mask step, expose the some parts of inter-level dielectric, then the part inter-level dielectric exposing is carried out to dry corrosion, until expose epi-layer surface, then silicon chip surface is injected to N-type dopant and form N-type source region, then by etching, form contact hole groove, and contact hole groove is carried out to metal plug filling, afterwards at surface deposition second layer inter-level dielectric, by inter-level dielectric masks, metal bed course place, drain region source region contact metal connector and drain metal are kept apart, simultaneously also the source region contact metal connector under gate metal bed course and drain region metal plug and gate metal bed course are isolated from each other and are come, follow the surface deposition one deck aluminium alloy at device, utilize metal mask to carry out metal attack, formation source electrode metal bed course, drain electrode metal bed course and gate electrode metal bed course, then substrate 10 its back sides of grinding that complete preceding working procedure are thick to being less than 160um, finally at the back of the body surface deposition multiple layer metal layer of silicon chip, form backplate.
Embodiment 1:
As shown in Figure 9, first N-type epitaxial loayer 20 is placed in to the top of N-type substrate 10, then on epitaxial loayer, adopt accumulation or hot growth pattern to form oxide layer 100 (thickness is 0.01um to 1um oxide hard light shield), accumulation one deck lithography coating 1000 again in oxide layer, then by deep trench mask, form the some parts that pattern exposes oxide layer, then oxide layer deep trench mask formation pattern being exposed carries out, after dry corrosion, exposing epitaxial loayer.
As shown in figure 10, then dispose lithography coating, then by etching, form deep trench 21 (degree of depth is 0.6um to 5.0um, and width is 0.1um to 1.5um), deep trench enters into N-type substrate through N-type epitaxial loayer.As shown in figure 11, deposit the polysilicon 22 of N-type high dopant in groove, polysilicon doping concentration is R
s=5 Ω/ to 100 Ω/ (sheet resistance), with filling groove and cover end face, then the polysilicon layer on epitaxial loayer surface oxide layer is carried out to plane corrosion treatment or chemical machinery, finally make polysilicon end face in groove be less than 0.5um under epi-layer surface, then dispose the oxide layer in epi-layer surface.
As shown in figure 12, on epitaxial loayer, adopt accumulation or hot growth pattern to form oxide layer 100 (thickness is 0.3um to 1.5um oxide hard light shield), accumulation one deck lithography coating 1000 again in oxide layer, then by gate trench mask, form the some parts that pattern exposes oxide layer, the oxide layer that gate trench mask formation pattern is exposed is carried out after dry corrosion, expose epitaxial loayer, then dispose lithography coating, (degree of depth is 0.6um to 5.0um by etching, to form gate trench, width is 0.12um to 1.5um), after forming groove, to groove sacrifice property, (time is 10 minutes to 100 minutes in oxidation, temperature is 1000 ℃ to 1200 ℃), to eliminate the silicon layer being destroyed by plasma in grooving process, then dispose all oxide layers.As shown in figure 13, the mode of growing by heat, the sidewall exposing at groove and bottom, and the upper surface of epitaxial loayer forms the thin grid oxic horizon 30 (thickness is 0.01um to 0.12um) of one deck, in groove, deposit the polysilicon 31 of N-type high dopant, polysilicon doping concentration is R
s=5 Ω/ to 100 Ω/ (sheet resistance), with filling groove and cover end face.
As shown in figure 14, accumulation one deck lithography coating 1000 on polysilicon layer, then by polysilicon mask, form the some parts that pattern exposes polysilicon layer, then polysilicon layer polysilicon layer mask formation pattern being exposed carries out after dry corrosion, until expose oxide layer on epitaxial loayer, then dispose lithography coating, (boron, dosage is 2e12/cm then to epi-layer surface, to inject P type dopant
3to 2e14/cm
3).
As shown in figure 15, by High temperature diffusion operation (time is 10 minutes to 1000 minutes, and temperature is 950 ℃ to 1200 ℃), the P type dopant propelling of injecting is diffused into epitaxial loayer and forms p type island region 24.
As shown in figure 16, in most surface, accumulation one deck medium, as silicon nitride, then carries out dry corrosion to medium and forms spacer32 afterwards, and (dosage is 1e12/cm then silicon chip surface to be injected to N-type dopant
3to 1e15/cm
3), there is the part of polysilicon layer and spacer not to be injected into, there is no the part of polysilicon layer and spacer, N-type dopant can be injected in epi-layer surface, and N-type dopant can adopt arsenic or phosphorus.
As shown in figure 17, by High temperature diffusion operation (time is 10 minutes to 200 minutes, and temperature is 950 ℃ to 1200 ℃), the N-type dopant propelling of injecting is diffused into epitaxial loayer afterwards and forms N-type lightly doped drain (LDD) district 25,
As shown in figure 18, follow accumulation ground floor inter-level dielectric in most surface, then accumulation one deck lithography coating 1000 on inter-level dielectric surface, by contact hole mask, form the some parts that pattern exposes inter-level dielectric afterwards, then the part inter-level dielectric exposing is carried out to dry corrosion, until expose epi-layer surface, dispose afterwards lithography coating, silicon chip surface is injected to N-type dopant, and (dosage is 1e15/cm
3to 2e16/cm
3), the part that has inter-level dielectric to cover is not injected into, the part that does not have inter-level dielectric to cover, and N-type dopant can be injected in epi-layer surface and form N-type district, and N-type dopant can adopt arsenic or phosphorus.
As shown in figure 19, the N-type dopant of injection is pushed into be diffused into by High temperature diffusion operation (time is 10 minutes to 1000 minutes, and temperature is 950 ℃ to 1200 ℃) and in epitaxial loayer, forms N-type source region 26.The formed N-type active area depth of this step (degree of depth is 0.1um to 0.6um).
As shown in figure 20, afterwards contact hole channel bottom is injected to P type high dopant 28, assorted agent dose is 10
14to 5 * 10
15/ cm
3to reduce the contact resistance between P type base and metal plug, the safe handling district that this increases device effectively, the P type dopant dose that is infused in place, LDMOS deep trench top is several times lower than than the N-type dopant dose at deep trench place, so on the not significantly impact of the doping content at deep trench place.
As shown in figure 21, at contact hole trenched side-wall, bottom and inter-level dielectric upper surface deposition one deck titanium/titanium nitride layer 33, then contact hole groove is carried out to tungsten 34 fills to form metal plug.
As shown in figure 22; the lip-deep one deck titanium/titanium nitride layer 33 of ground floor inter-level dielectric and tungsten layer 34 are disposed; then accumulation second layer inter-level dielectric 36 in most surface; accumulation one deck lithography coating on second layer inter-level dielectric surface; then pass through masks; at metal bed course place, drain region, the inter-level dielectric beyond protection contact hole trench metal connector top, source region, LDMOS place and gate metal bed course is disposed.
As shown in figure 23, at this, above device, deposit one deck aluminium alloy 40 (thickness is 0.8um to 5um), then by metal mask, carry out metal etch, form source region metal bed course, drain region metal bed course and gate metal bed course.
Then accumulation one deck passivation layer in most surface, carries out passivation layer etch by passivation layer mask, forms source region metal bed course perforate, drain region metal bed course perforate and the perforate of gate metal bed course.Afterwards the substrate 10 that completes preceding working procedure is ground to its back side to desired thickness, substrate final thickness is less than 250um, the last back of the body surface deposition multiple layer metal layer at silicon chip.
Embodiment 2:
For a kind of modification of the present invention (embodiment).
Step is identical with embodiment 1, just, in Figure 14 step, adds a masks drain region at metal bed course place, drain region is covered before injecting P type dopant to epi-layer surface, and those P type dopants do not inject, and the device architecture of embodiment 2 is with reference to Figure 24.
Embodiment 3:
For a kind of modification of the present invention (embodiment).
Forming metal bed course place, drain region conduction deep trench step, be positioned over after technological process, first: as shown in figure 10, on epitaxial loayer, adopt accumulation or hot growth pattern to form oxide layer 100 (thickness is 0.3um to 1.5um oxide hard light shield), accumulation one deck lithography coating 1000 again in oxide layer, then by gate trench mask, form the some parts that pattern exposes oxide layer, the oxide layer that gate trench mask formation pattern is exposed is carried out after dry corrosion, expose epitaxial loayer, then dispose lithography coating, by etching, (degree of depth is 0.6um to 5.0um at metal bed course place, source region, to form gate trench, width is 0.12um to 1.5um), after forming groove, to groove sacrifice property, (time is 10 minutes to 100 minutes in oxidation, temperature is 1000 ℃ to 1200 ℃), to eliminate the silicon layer being destroyed by plasma in grooving process, then dispose all oxide layers.Then step is if embodiment 1 is by Figure 11 to Figure 19 afterwards, forms behind N-type source region as Figure 25:
As shown in figure 26, accumulation one deck lithography coating 1000 in most surface, then by deep trench mask formation pattern, exposing some parts does not have inter-level dielectric there; Then (degree of depth is 0.6um to 5.0um by etching, to form deep trench 21, width is 0.1um to 1.5um), deep trench enters into N-type substrate through N-type source region and N-type epitaxial loayer, then by general ion implantation or plasma immersion ion implantation, deep trench sidewall is injected to N-type dopant and forms deep trench N-type doped sidewalls 23.
As shown in figure 27, dispose lithography coating, by etching, form ground floor contact hole groove 27 (degree of depth is 0.6um to 1.5um, and width is 0.1um to 1.5um), ground floor contact hole groove 27 enters into P type base through N-type source region; Afterwards contact hole groove is injected to P type high dopant 28, assorted agent dose is 1014 to 5 * 10
15/ cm
3, to reduce the contact resistance between P type base and metal plug, this increases the safe handling district of device effectively.
As shown in figure 28, at deep trench and contact hole trenched side-wall, bottom and inter-level dielectric upper surface deposition one deck titanium/titanium nitride layer 33, then deep trench and contact hole groove are carried out to tungsten 34 and fill to form metal plug.As shown in figure 29; the lip-deep one deck titanium/titanium nitride layer 33 of ground floor inter-level dielectric and tungsten layer 34 are disposed; then accumulation second layer inter-level dielectric 36 in most surface; accumulation one deck lithography coating on second layer inter-level dielectric surface; then pass through masks; at metal bed course place, drain region, the inter-level dielectric beyond protection contact hole trench metal connector top, source region, LDMOS place and gate metal bed course is disposed.
As shown in figure 30, then at this, above device, deposit one deck aluminium alloy 40 (thickness is 0.8um to 5um), then by metal mask, carry out metal etch, form source region metal bed course, drain region metal bed course and gate metal bed course.
Then accumulation one deck passivation layer in most surface, carries out passivation layer etch by passivation layer mask, forms source region metal bed course perforate, drain region metal bed course perforate and the perforate of gate metal bed course.Afterwards the substrate 10 that completes preceding working procedure is ground to its back side to desired thickness, substrate final thickness is less than 250um, the last back of the body surface deposition multiple layer metal layer at silicon chip.
Finally it should be noted that: these are only the preferred embodiments of the present invention, be not limited to the present invention, embodiments of the invention are to make an explanation with N-type passage device, the present invention also can be used for P type passage device, although the present invention is had been described in detail with reference to embodiment, for a person skilled in the art, its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement, but within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improve etc., within all should being included in protection scope of the present invention.
Reference symbol table:
10 substrates
20 epitaxial loayers
21 deep trench
Highly doped polysilicon in 22 deep trench
23 deep trench sidewall N-type source regions
24 P type bases
25 lightly doped drains (LDD) N-type district
26 N-type source regions
27 contact hole grooves
The P type high-doped zone of 28 contact hole channel bottoms
30 grid oxic horizons
31 gate polysilicon layers
32 spacer
33 ground floor inter-level dielectrics
34 titanium layers/titanium nitride layer
35 tungsten
36 second layer inter-level dielectrics
40 metal bed courses
100 oxide hard light shields
1000 lithography coatings.
Claims (11)
1. the structure of a chip size packages semiconductor power device comprises following part:
(1) the source metal bed course of device, drain metal bed course and gate metal bed course are all on the surface of chip;
(2) under source metal bed course, be trench field effect transistor structure;
(3) have a drain metal bed course at least, under it, be LDMOS structure and have conduction deep trench the drain region of epi-layer surface is connected to substrate;
(4) under gate metal bed course, be LDMOS structure and have conduction deep trench that the drain region of epi-layer surface is connected to substrate, the drain region electric current under gate metal bed course is to see through the drain metal of drain region metal plug from gate metal bed course to introduce;
(5) at source metal bed course, on drain metal bed course and gate metal bed course, can there is passivation layer, in passivation layer, there is perforate to be used for connecting soldered ball or metal routing;
(6) silicon chip completing after front degree operation need not grind the back side, also not be used in backside deposition multiple layer metal.
2. the structure of a kind of chip size packages semiconductor power device according to claim 1, wherein, conduction deep trench can be formed by highly doped polysilicon, and polysilicon doping concentration is R
s=5 Ω/ to 100 Ω/ (sheet resistance), conduction deep trench can be formed by metal plug, and metal plug material can be comprised of titanium layer/titanium nitride layer and tungsten, and it is 1um to 5um that gash depth is counted depth bounds from epi-layer surface to substrate direction; Conduction deep trench also can be divided into two parts, and end partial depth 3um to 4.5um, is formed by highly doped polysilicon, and top partial depth 0.5um to 2.0um, is formed by metal plug.
3. the structure of a kind of chip size packages semiconductor power device according to claim 1, wherein, the Shi You p type island region, drain region of the LDMOS under drain metal bed course.
4. the structure of a kind of chip size packages semiconductor power device according to claim 1, wherein, the drain region of LDMOS under drain metal bed course is there is no p type island region, and this needs a masks that the drain region of LDMOS was covered before injecting P type dopant.
5. the structure of a kind of chip size packages semiconductor power device according to claim 1, wherein, has a gate metal bed course at least, there is no LDMOS structure transistor unit under it.
6. the structure of a kind of chip size packages semiconductor power device according to claim 1, wherein, thick to being less than 250um the silicon chip grinding that completes front degree operation, then deposit multilayer metal overleaf.
7. a preparation method for chip size packages semiconductor power device, comprises the following steps:
(1) first N-type epitaxial loayer is placed in to the highly doped substrate of N-type top, the doping content of N-type substrate is higher than 1e19/cm
3, the doping content concentration range of N-type epitaxial loayer is 1e14/cm
3to 5e16/cm
3, at metal bed course place, drain region, form conduction deep trench the drain region of epi-layer surface be connected to substrate;
(2) at metal bed course place, source region, utilize gate trench mask to corrode on epitaxial loayer and form the mode that a plurality of gate trenchs are also grown by heat, the sidewall exposing at groove and bottom, form the thin grid oxic horizon of one deck with the upper surface of epitaxial loayer, the polysilicon that then deposits N-type high dopant is with filling groove and cover end face;
(3) utilize polysilicon mask step at metal bed course place, drain region, to form the polysilicon gate of LDMOS, then silicon chip surface is injected to P type dopant and form p type island region, the drain region of the LDMOS under the metal bed course of drain region is to have P type dopant to inject to form p type island region;
(4) in most surface, accumulation one deck medium, as silicon nitride, then carries out dry corrosion to medium and forms spacer32, then silicon chip surface is injected to N-type dopant and forms N-type lightly doped drain (LDD) district;
(5) accumulation ground floor inter-level dielectric from the teeth outwards, then by contact hole mask step, expose the some parts of inter-level dielectric, then the part inter-level dielectric exposing is carried out to dry corrosion, until expose epi-layer surface, then silicon chip surface is injected to N-type dopant and form N-type source region, N-type source region concentration is higher than 1e19/cm
3;
(6) then by etching, form contact hole groove, then contact hole channel bottom is injected to P type dopant, dosage range is 1e14/cm
3to 5e15/cm
3, and contact hole groove is carried out to metal plug filling;
(7) afterwards at surface deposition second layer inter-level dielectric, by inter-level dielectric masks, metal bed course place, drain region source region contact metal connector and drain metal are kept apart, simultaneously also the source region contact metal connector under gate metal bed course and drain region metal plug and gate metal bed course are isolated from each other and are come;
(8) then at surface deposition one deck aluminium alloy of device, utilize metal mask to carry out metal attack, form source electrode metal bed course, drain electrode metal bed course and gate electrode metal bed course;
(9) then the substrate 10 that completes preceding working procedure is ground to its back sides thick to being less than 250um, finally at the back of the body surface deposition multiple layer metal layer of silicon chip, form backplate.
A kind of chip size packages semiconductor power device according to claim 7 preparation method, wherein the described polysilicon gate of step (3) is highly doped, polysilicon doping concentration is R
s=5 Ω/ to 100 Ω/ (sheet resistance), polycrystalline silicon grid layer can be metallized, as formed cobalt SiClx (CoSi), titanizing silicon (TiSi) or tungsten SiClx (WSi) etc. on polysilicon layer surface.
A kind of chip size packages semiconductor power device according to claim 7 preparation method, what wherein step (3) was described injects P type dopant formation p type island region to silicon chip surface, before injecting P type dopant, with a masks, the drain region of LDMOS is covered, make P type dopant cannot inject the drain region of LDMOS, so the drain region of LDMOS does not have p type island region.
10. a preparation method for chip size packages semiconductor power device, comprises the following steps:
(1) first N-type epitaxial loayer is placed in to the highly doped substrate of N-type 10 tops, the doping content of N-type substrate is higher than 1e19/cm
3, the doping content concentration range of N-type epitaxial loayer is 1e14/cm
3to 5e16/cm
3;
(2) at metal bed course place, source region, utilize gate trench mask to corrode on epitaxial loayer and form the mode that a plurality of gate trenchs are also grown by heat, the sidewall exposing at groove and bottom, form the thin grid oxic horizon of one deck with the upper surface of epitaxial loayer, the polysilicon that then deposits N-type high dopant is with filling groove and cover end face;
(3) utilize polysilicon mask step at metal bed course place, drain region, to form the polysilicon gate of LDMOS, then silicon chip surface is injected to P type dopant and form p type island region, the drain region of the LDMOS under the metal bed course of drain region is to have P type dopant to inject to form p type island region;
(4) in most surface, accumulation one deck medium, as silicon nitride, then carries out dry corrosion to medium and forms spacer32, then silicon chip surface is injected to N-type dopant and forms N-type lightly doped drain (LDD) district;
(5) accumulation ground floor inter-level dielectric from the teeth outwards, then by contact hole mask step, expose the some parts of inter-level dielectric, then the part inter-level dielectric exposing is carried out to dry corrosion, until expose epi-layer surface, then silicon chip surface is injected to N-type dopant and form N-type source region, N-type source region concentration is higher than 1e19/cm
3;
(6) accumulation one deck lithography coating 1000 in most surface, then by deep trench mask formation pattern, exposing some parts does not have inter-level dielectric there; Then by etching, form deep trench, the degree of depth is 0.6um to 5.0um, width is 0.1um to 1.5um, deep trench enters into N-type substrate through N-type source region and N-type epitaxial loayer, then by general ion implantation or plasma immersion ion implantation, deep trench sidewall is injected to N-type dopant and forms deep trench N-type doped sidewalls 23;
(7) by etching, form contact hole groove, the degree of depth is 0.6um to 1.5um, and width is 0.1um to 1.5um, and contact hole groove enters into P type base through N-type source region; Afterwards contact hole groove is injected to P type high dopant, dosage is 10
14to 5 * 10
15/ cm
3;
(8) at deep trench and contact hole trenched side-wall, bottom and inter-level dielectric upper surface deposition one deck titanium/titanium nitride layer, then deep trench and contact hole groove are carried out to tungsten filling to form metal plug;
(9) the lip-deep one deck titanium/titanium nitride layer of ground floor inter-level dielectric and tungsten layer are disposed, then accumulation second layer inter-level dielectric 36 in most surface, by second layer inter-level dielectric masks, source region contact metal connector and drain metal under the metal bed course of drain region are kept apart, simultaneously also the source region contact metal connector under gate metal bed course and drain region metal plug and gate metal bed course are isolated from each other and are come;
(10) on device, deposit one deck aluminium alloy 40, thickness is 0.8um to 5um, then by metal mask, carries out metal etch, forms source region metal bed course, drain region metal bed course and gate metal bed course;
(11) then the substrate 10 that completes preceding working procedure is ground to its back sides thick to being less than 250um, finally at the back of the body surface deposition multiple layer metal layer of silicon chip, form backplate.
11. a kind of chip size packages semiconductor power devices according to claim 10 preparation method, what wherein step (3) was described injects P type dopant formation p type island region to silicon chip surface, before injecting P type dopant, with a masks, the drain region of LDMOS is covered, make P type dopant cannot inject the drain region of LDMOS, so the drain region of LDMOS does not have p type island region.
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| CN104409502A (en) * | 2014-11-13 | 2015-03-11 | 中航（重庆）微电子有限公司 | Power transistor and manufacturing method thereof |
| CN105762193A (en) * | 2016-04-28 | 2016-07-13 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN105845735A (en) * | 2016-04-28 | 2016-08-10 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
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| CN104409502A (en) * | 2014-11-13 | 2015-03-11 | 中航（重庆）微电子有限公司 | Power transistor and manufacturing method thereof |
| CN105762193A (en) * | 2016-04-28 | 2016-07-13 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN105845735A (en) * | 2016-04-28 | 2016-08-10 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN107591452A (en) * | 2017-10-10 | 2018-01-16 | 无锡新洁能股份有限公司 | A kind of wafer scale power semiconductor and preparation method thereof |
| CN107591452B (en) * | 2017-10-10 | 2024-03-12 | 无锡新洁能股份有限公司 | Wafer-level power semiconductor device and manufacturing method thereof |
| CN113113485A (en) * | 2020-01-13 | 2021-07-13 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor device and method of forming the same |
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