CN112086346B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN112086346B
CN112086346B CN201910511292.8A CN201910511292A CN112086346B CN 112086346 B CN112086346 B CN 112086346B CN 201910511292 A CN201910511292 A CN 201910511292A CN 112086346 B CN112086346 B CN 112086346B
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layer
forming
groove
size
mask
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CN112086346A (en
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张海洋
纪世良
张冬平
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor device and a method of forming the same, including: providing a substrate comprising first regions and second regions located between adjacent first regions; forming a first material layer on the surface of a substrate; forming a first mask layer on the surface of the first material layer, wherein the first mask layer is internally provided with a first groove positioned in the first area and a second groove exposing the second area; the first mask layer has a third dimension; doping first ions in a part of the first material layer at the bottom of the first groove to form a first sacrificial layer, enabling the undoped first material layer at the bottom of the first groove to form a second mask layer, enabling one side wall of the first sacrificial layer to be flush with one side wall of the first groove, and enabling the second mask layer to have a fifth size unequal to the third size; forming a second sacrificial layer in the first material layer at the bottom of the second groove, and forming a third mask layer on the first material layer at the bottom of the first mask layer; removing the first sacrificial layer to form a third groove; and removing the second sacrificial layer to form a fourth groove. The method improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
With the rapid development of semiconductor technology, the feature size of semiconductor devices is continuously reduced, so that the integrated circuit is more and more integrated, and the requirements on the semiconductor manufacturing process are also higher. Etching is an important process in semiconductor manufacturing, and is a process of transferring a pattern on a mask onto a material layer, and as the feature size is continuously reduced, the etching process encounters a bottleneck due to the existence of a wavelength limit in the photolithography process, so that etching of a trench with a smaller size cannot be provided.
In order to obtain smaller pitch sizes, multiple Patterning Lithography (MPL) has been developed. Two forms of MPL have been tried, one using repeated lithographic processes (photolithography-etch-lithography or LELE) techniques and the other based on self-aligned spacer processing. The self-aligned spacer process is advantageous when fabricating fins of FinFET structures.
The self-aligned spacer process is commonly referred to as a self-aligned dual process (SADP). In SADP, a set of mandrels is lithographically formed by patterning and etching a mandrel material. Sidewall spacers may then be formed on the sidewalls of the mandrels. The formation of sidewall spacers may be accomplished by depositing material over the mandrel material, removing the deposited material on the horizontal surfaces, and removing the mandrel material, leaving the sidewall spacers behind. The deposition of sidewall spacers may result in a spacer width that is much smaller than the spacer width achievable by photolithographic formation of mandrels. The sidewall spacers and mandrels may then be polished to expose the mandrels and the spacers that act as an etch mask to remove remaining mandrel material. The SADP process involves forming spacers as a film layer on the sidewalls of a pre-patterned mandrel, removing the spacer layer from the horizontal surface, and removing the initially patterned mandrel material leaving the spacers themselves. Since each mandrel has two sidewall spacers, the linear density is doubled. Thus, SADP is suitable for defining narrow fins at half the initial lithographic pitch.
However, due to the limitations of the photolithography process, the pitch of the fin formed by SADP is difficult to adjust.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which aims to improve the performance of the semiconductor device.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate comprising a plurality of first regions and a plurality of second regions located between adjacent first regions; forming a first material layer on the surfaces of the first area and the second area of the substrate; forming a first mask layer on the surface of the first material layer, wherein the first mask layer is internally provided with a first groove and a second groove which are separated from each other, the first groove is positioned in a first area, the second groove exposes a second area, the first groove has a first size in a first direction parallel to the surface of the substrate, the second groove has a second size, and the first mask layer has a third size; doping first ions in a part of the first material layer at the bottom of the first groove, forming a first sacrificial layer in the first material layer, enabling the first material layer without the first ions at the bottom of the first groove to form a second mask layer, enabling one side wall of the first sacrificial layer to be flush with one side wall of the first groove in a first direction parallel to the surface of the substrate, enabling the first sacrificial layer to have a fourth size in the first direction parallel to the surface of the substrate, enabling the fourth size to be smaller than the first size, enabling the second mask layer to have a fifth size, and enabling the value of the fifth size to be unequal to that of the third size; doping second ions in the first material layer at the bottom of the second groove to form a second sacrificial layer, and enabling the first material layer without doping the second ions at the bottom of the first mask layer to form a third mask layer, wherein the second sacrificial layer has a second size in a first direction parallel to the surface of the substrate, and the third mask layer has a third size; removing the first sacrificial layer to form a third groove; and removing the second sacrificial layer to form a fourth groove.
Optionally, the first groove has opposite first and second sidewalls, and the first sacrificial layer is flush with the first sidewall of the first groove; the method for forming the semiconductor device further comprises the following steps: doping first ions in a part of the first material layer at the bottom of the first groove after forming a first mask layer, and forming a third sacrificial layer, wherein the second mask layer is positioned between the first sacrificial layer and the third sacrificial layer, the third sacrificial layer is flush with the second side wall of the first groove, and the third sacrificial layer has a sixth size in a first direction parallel to the surface of the substrate; and removing the third sacrificial layer to form a fifth groove.
Optionally, after forming the third sacrificial layer, the first sacrificial layer is formed.
Optionally, the forming method of the first sacrificial layer includes: forming a first pattern layer on the first mask layer and the first material layer, wherein a first opening is formed in the first pattern layer, and the first opening exposes the first groove; and performing first inclined ion implantation on the first side wall of the first groove and the first material layer at the bottom of the first groove by taking the first graph layer as a mask to form the first sacrificial layer.
Optionally, after forming the first sacrificial layer, forming a third sacrificial layer; the method for forming the third sacrificial layer comprises the following steps: and performing second inclined ion implantation on the second side wall of the first groove and the first material layer at the bottom of the first groove by taking the first graph layer as a mask to form the third sacrificial layer.
Optionally, a first included angle is formed between the implantation direction of the first inclined ion implantation and the normal direction of the substrate surface, and the first included angle is greater than or equal to 0 degrees and less than 10 degrees.
Optionally, a second included angle is formed between the implantation direction of the second inclined ion implantation and the normal direction of the substrate surface, and the second included angle is greater than or equal to 0 degrees and less than 10 degrees.
Optionally, the material of the first material layer includes: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
Optionally, the first ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
Optionally, the forming method of the second sacrificial layer includes: forming a second pattern layer on the first mask layer and the first material layer, the second pattern layer exposing the second groove; and carrying out ion doping on the first material layer at the bottom of the second groove by taking the second patterned layer as a mask, wherein the ion doped ions are second ions, so as to form the second sacrificial layer.
Optionally, the ion doping process includes: an ion implantation process or a solid state source doping process.
Optionally, the second ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
Optionally, the material of the first mask layer includes: polysilicon, silicon nitride, titanium oxide or titanium nitride.
Optionally, after removing the first mask layer, removing the first sacrificial layer and the second sacrificial layer.
Optionally, the second sacrificial layer is removed in the process of removing the first sacrificial layer.
Optionally, the substrate includes: the substrate, the initial first dabber layer that is located the substrate surface and the initial second dabber layer that is located initial first dabber layer surface.
Optionally, the substrate further comprises: the first protection layer is formed on the surface of the substrate, and the initial first mandrel layer is positioned on the surface of the first protection layer; forming a second protective layer on the surface of the initial first mandrel layer, wherein the initial second mandrel layer is positioned on the surface of the second protective layer; and forming a third protective layer on the surface of the initial second mandrel layer, wherein the first material layer is positioned on the surface of the third protective layer.
Optionally, the method for forming a semiconductor device further includes: etching the initial first mandrel layer by taking the second mask layer and the third mask layer as masks to form a first mandrel layer, wherein a first opening is formed between adjacent first mandrel layers in the first region, the first opening has a first size, and a second opening is formed between the first mandrel layers in the adjacent first region; forming a first side wall on the side wall of the first mandrel layer, wherein the first side wall fills the first opening, and the first side wall is also positioned on the side wall of the second opening; removing the first mandrel layer after forming the first side wall; after the first mandrel layer is removed, the first side wall is used as a mask, the initial second mandrel layer is etched, a second mandrel layer is formed on the first area substrate, the second mandrel layer is further positioned on the second area substrate, two sides of the second mandrel layer of the first area are respectively provided with a third opening and a fourth opening, and in a first direction parallel to the surface of the substrate, the third opening is provided with a first size, and the fourth opening is provided with a fourth size; forming a second side wall on the side wall of the second mandrel layer, wherein the second side wall is further positioned on the second area substrate, the second side wall covers the third opening and the side wall of the fourth opening, the second side wall has a sixth size, the first size is larger than twice of the sixth size, and the fourth size is larger than twice of the sixth size; removing the second mandrel layer after forming the second side wall; removing the second side wall of the second region after removing the second mandrel layer; and after removing the second side wall of the second region, etching the substrate by taking the second side wall of the first region as a mask, and forming a fin part in the substrate.
The invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor device, the first material layer is divided into the first sacrificial layer, the second mask layer, the second sacrificial layer and the third mask layer through the ion doping process. The third mask layer is located at the bottom of the first mask layer, so that the size of the third mask layer is the same as that of the first mask layer, the second mask layer has a fifth size, and if the value of the third size is different from that of the fifth size, the sizes of the second mask layer and the third mask layer are also different. And forming a patterned layer of a subsequent SADP process by taking the second mask layer and the third mask layer as masks, thereby realizing fin parts with different pitches. Thereby improving the performance of the semiconductor device.
Further, the distance between the two second side walls of the side wall of the third opening is the size of the third opening minus the thickness of the two second side walls; the third opening is formed by reversely transferring the third mask layer, the size of the third opening is equal to that of the third mask layer, the size of the third mask layer is equal to that of the first mask layer, and the third opening has a third size. The distance between the two second side walls of the side wall of the fourth opening is the size of the fourth opening minus the thickness of the two second side walls; and the fourth opening is formed by reversely transferring the second mask layer, and the size of the fourth opening is equal to the size of the second mask layer and is the fifth size. The distance between the second side walls on two sides of the second mandrel layer in the first area is the size of the second mandrel layer, the second mandrel layer is formed by reversely transferring the third groove, the size of the second mandrel layer is equal to the size of the third groove, the third groove is formed by removing the first sacrificial layer, and the size of the third groove is equal to the size of the first sacrificial layer and is the fourth size. Therefore, the first size, the fourth size and the fifth size are reasonably designed, and fin portions with multiple pitches can be realized. Thereby improving the performance of the semiconductor device.
Drawings
Fig. 1 to 14 are schematic structural views of a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the prior art semiconductor device is poor.
As semiconductor devices develop, it is required to form fins with multiple pitches, i.e., the distance between adjacent fins has multiple dimensions. At the same time, the fin size of FinFET devices is further shrinking, and such small-sized fins have not been realized using photolithography techniques, but using SADP processes. However, it is difficult to form fins of multiple pitches even by the SADP process. Therefore, semiconductor devices having fins with multiple pitches are difficult to realize.
In an embodiment of the invention, a substrate is provided; forming a first material layer on the surface of a substrate; forming a first mask layer on the surface of the first material layer, wherein the first mask layer is internally provided with a first groove and a second groove, the first groove is provided with a first size, the second groove is provided with a second size, and the first mask layer is provided with a third size; doping first ions in a part of the first material layer at the bottom of the first groove to form a first sacrificial layer, forming the undoped first material layer at the bottom of the first groove into a second mask layer, wherein one side wall of the first sacrificial layer is flush with one side wall of the first groove, the first sacrificial layer has a fourth size, and the second sacrificial layer has a fifth size; doping second ions in the first material layer at the bottom of the second groove to form a second sacrificial layer, and forming the first material layer at the bottom of the first mask layer into a third mask layer; removing the first sacrificial layer to form a third groove; and removing the second sacrificial layer to form a fourth groove. The third mask layer is located at the bottom of the first mask layer, so that the size of the third mask layer is the same as that of the first mask layer, the second mask layer has a fifth size, and if the value of the third size is different from that of the fifth size, the sizes of the second mask layer and the third mask layer are also different. And then forming fin parts with different pitches through the second mask layers and the third mask layers with different sizes.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 to 14 are schematic structural views of a semiconductor device forming process.
Referring to fig. 1, a substrate is provided.
In this embodiment, the substrate includes a plurality of first regions I and a plurality of second regions II located between adjacent first regions I.
In this embodiment, the substrate includes: a substrate 200, an initial first mandrel layer 202 located on a surface of the substrate 200, and an initial second mandrel layer 204 located on a surface of the initial first mandrel layer 202.
In this embodiment, the substrate further includes: a first protective layer 201 formed on the surface of the substrate 200, wherein an initial first mandrel layer 202 is located on the surface of the first protective layer 201; forming a second protective layer 203 on the surface of the initial first mandrel layer 201, wherein the initial second mandrel layer 204 is positioned on the surface of the second protective layer 203; a third protective layer 205 is formed on the surface of the initial second mandrel layer 204.
The substrate 200 is used to provide a layer of material for forming the fin.
The substrate 200 includes: silicon, germanium, silicon carbide, gallium arsenide, or indium gallium. In this embodiment, the material of the substrate 200 is: silicon, the substrate 200 is formed using a selective epitaxial process.
The materials of the first protective layer 201, the second protective layer 202 and the third protective layer 205 include: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride or silicon oxycarbide.
The first protective layer 201, the second protective layer 202, and the third protective layer 205 are etching stop layers.
In this embodiment, the materials of the first protective layer 201, the second protective layer 202 and the third protective layer 205 are silicon oxide.
The materials of the first mandrel layer 202 include: amorphous silicon, amorphous carbon, polysilicon, silicon oxide, siCO, or SiCOH.
The materials of the second mandrel layer 204 include: amorphous silicon, amorphous carbon, polysilicon, silicon oxide, siCO, or SiCOH. A step of
In this embodiment, the material of the first mandrel layer 202 is polysilicon. The material of the second mandrel layer 204 is polysilicon.
With continued reference to fig. 1, a first material layer 210 is formed on the substrate surface.
In this embodiment, the first material layer 210 is located on the surface of the third protection layer 205.
The first material layer 210 provides a material layer for subsequently forming a second mask layer and a third mask layer.
The materials of the first material layer 210 include: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
In this embodiment, the material of the first material layer 210 is amorphous silicon.
The process of forming the first material layer 210 includes: a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the first material layer 210 is a chemical vapor deposition process. In other embodiments, the first material layer is formed using a physical vapor deposition process or an atomic layer deposition process.
Referring to fig. 2, a first mask layer 220 is formed on the surface of the second material layer 220, the first mask layer 220 has a first groove 221 and a second groove 222 separated from each other, the first groove 221 is located in a first region I, the second groove 222 exposes a second region II, the first groove 221 has a first dimension X in a first direction parallel to the substrate surface, the second groove 222 has a second dimension C, and the first mask layer 220 has a third dimension a.
In this embodiment, the first dimension X is greater than the second dimension C.
In this embodiment, the first mask layer 220 is located on the surface of the first material layer 210 in the first region I, and the first mask layer 220 exposes the surface of the first material layer 210 in the second region II.
The materials of the first mask layer 220 include: polysilicon, silicon nitride, titanium oxide or titanium nitride.
In this embodiment, the material of the first mask layer 220 is polysilicon. In other embodiments, the material of the first mask layer is silicon nitride, titanium oxide or titanium nitride.
The method for forming the first mask layer 220 includes: forming an initial first mask layer on the surface of the first material layer 210; forming a first photoresist layer on the surface of the initial first mask layer, wherein the first photoresist layer exposes part of the initial first mask layer of the first region; etching the initial first mask layer by using the first photoresist layer as a mask to form a first groove 221; after forming the first groove 221, removing the first photoresist layer; after the first photoresist layer is removed, a second photoresist layer is formed on the surface of the initial first mask layer, and the second photoresist layer exposes the surface of the initial first mask layer of the second region II; and etching the initial first mask layer by taking the second photoresist layer as a mask to form a second groove 222, and forming the initial first mask layer into a first mask layer 220.
In a first direction parallel to the substrate surface, the first mask layer 220 has the same size, and the first groove 221 and the second groove 222 have larger sizes, which is easy to implement by using a photolithography process.
Referring to fig. 3, first ions are doped in a portion of the first material layer 210 at the bottom of the first trench 221, forming a first sacrificial layer 240, and the first material layer 210, which is not doped with the first ions at the bottom of the first trench 221, is formed as a second mask layer 250, one sidewall of the first sacrificial layer 240 is flush with one sidewall of the first trench 221, the first sacrificial layer 240 has a fourth dimension B, which is smaller than the first dimension X, and the second mask layer 250 has a fifth dimension D, which is unequal to the third dimension a.
In this embodiment, the first trench 221 is located in the first region I, and the first sacrificial layer 240 and the second mask layer 250 are located on the substrate surface of the first region I.
The first sacrificial layer 240 defines the location of a subsequently formed third trench.
The first slot 221 has opposing first and second sidewalls.
In this embodiment, the first sacrificial layer 240 is flush with the first sidewall of the first trench 221. In other embodiments, the first sacrificial layer is flush with the second sidewall of the first trench.
In this embodiment, the method further includes: first ions are doped in a portion of the first material layer 210 at the bottom of the first trench 221 to form a third sacrificial layer 242, the second mask layer 250 is located between the first sacrificial layer 240 and the third sacrificial layer 242, and the third sacrificial layer 242 is flush with the second sidewall of the first trench 221.
In this embodiment, in the first direction parallel to the substrate surface, the size of the third sacrificial layer 242 is equal to the size of the first sacrificial layer 240 to be the fourth size B. In other implementations, the third sacrificial layer 242 is not the same size as the first sacrificial layer 240.
The third sacrificial layer 242 is located on the substrate of the first region I.
In this embodiment, the fourth dimension B is smaller than the first dimension X, and twice the fourth dimension B is smaller than the first dimension X.
In this embodiment, the first dimension X is equal to twice the sum of the fourth dimension B and the fifth dimension D.
In this embodiment, after the first sacrificial layer 240 is formed, the third sacrificial layer 242 is formed. In other embodiments, the first sacrificial layer is formed after the third sacrificial layer is formed.
The forming method of the first sacrificial layer 240 includes: forming a first pattern layer 230 on the first mask layer 220 and the first material layer 210, wherein the first pattern layer 230 has a first opening 231 therein, and the first opening 231 exposes the first groove 221; the first sacrificial layer 240 is formed by performing oblique ion implantation on the first sidewall of the first trench 211 and the first material layer 210 at the bottom of the first trench 221 using the first pattern layer 230 as a mask.
The implantation direction of the first inclined ion implantation and the normal direction of the substrate surface have a first included angle, and the first included angle is more than or equal to 0 degree and less than 90 degrees.
In this embodiment, the first included angle is greater than or equal to 0 degrees and less than 10 degrees.
The forming method of the third sacrificial layer 242 includes: and performing a second oblique ion implantation on the second sidewall of the first trench 211 and the first material layer 210 at the bottom of the first trench 221 by using the first pattern layer 230 as a mask, thereby forming the third sacrificial layer 242.
And a second included angle is formed between the implantation direction of the second inclined ion implantation and the normal direction of the substrate surface, and the first included angle is more than or equal to 0 degree and less than 90 degrees.
In this embodiment, the second included angle is greater than 0 degrees and less than 10 degrees.
In this embodiment, the second included angle is equal to the first included angle. In other embodiments, the second included angle is not equal to the first included angle.
The second angle is equal to the first angle, and then the first sacrificial layer 240 and the third sacrificial layer 242 are equal in size in the first direction.
The materials of the first graphic layer 230 include: photoresist, bottom antireflective coating, or amorphous carbon.
In this embodiment, the material of the first pattern layer 230 is a photoresist material.
In this embodiment, the first pattern layer 230 also exposes a portion of the top surface of the first mask layer 220 that is a portion of the sidewall of the first trench 221. In other embodiments, the first pattern layer 230 does not expose a top surface of the first mask layer of the first trench sidewall.
The first ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
In this embodiment, the first ion is a boron ion.
The first material layer 210 at the bottom of the first trench 221 is separated into the second mask layer 250, the third sacrificial layer 242, and the first sacrificial layer 240 by an ion implantation process such that the materials of the first sacrificial layer 240 and the third sacrificial layer 242 are different from the materials of the second mask layer 250.
The first sacrificial layer 240 and the third sacrificial layer 242 are formed by doping the first material layer 210 with first ions, and the first ions enter into ion gaps of the first material layer 210, so that ion states of the first sacrificial layer 240 and the third sacrificial layer 242 are stable and are not easy to be etched.
Referring to fig. 4, after the first sacrificial layer 240 is formed, the first pattern layer 230 is removed.
In this embodiment, after the first sacrificial layer 240 and the third sacrificial layer 242 are formed, the first pattern layer 230 is removed.
The process of removing the first pattern layer 230 is an ashing process.
The first pattern layer 230 is removed by an ashing process, the process is simple, and the first mask layer 220, the first sacrificial layer 240, and the third sacrificial layer 242 are less damaged.
The material of the first pattern layer 230 is different from the material of the first mask layer 220, the material of the first pattern layer 230 is different from the material of the first sacrificial layer 240, the material of the first pattern layer 230 is different from the material of the third sacrificial layer 242, and the first mask layer 220, the first sacrificial layer 240 and the third sacrificial layer 242 are preserved when the first pattern layer 230 is removed.
After the first pattern layer 230 is removed, the second trench 222 is exposed.
The second sacrificial layer 241 is formed by doping the second ions in the first material layer 210 at the bottom of the second trench 221, and the first material layer 210 at the bottom of the first mask layer 220 is formed as a third mask layer 251. The method for forming the second sacrificial layer 241 and the third mask layer 251 is specifically shown in fig. 5 to 6.
Referring to fig. 5, a second pattern layer 206 is formed on the first mask layer 220 and the first material layer 210, and the second pattern layer 206 exposes the second grooves 222.
The second pattern layer 206 and the first mask layer 220 together serve as a mask layer for the second sacrificial layer.
The materials of the second graphic layer 206 include: photoresist, bottom antireflective coating, or amorphous carbon.
In this embodiment, the material of the second pattern layer 206 is a photoresist material.
The forming method of the second graphic layer 206 includes: forming an initial second pattern layer on the first mask layer 220 and the first material layer 210; the initial second pattern layer is exposed and developed to form the second pattern layer 206.
In this embodiment, the second pattern layer 206 also exposes a portion of the top surface of the first mask layer 220 that is a portion of the sidewall of the second trench 222. In other embodiments, the second pattern layer 206 does not expose a top surface of the first mask layer of the second trench sidewall.
The material of the second pattern layer 206 is different from the material of the first mask layer 220, the material of the second pattern layer 206 is different from the material of the second sacrificial layer 241, and the first mask layer 220 and the second sacrificial layer are preserved when the second pattern layer 206 is subsequently removed.
Referring to fig. 6, the second sacrificial layer 241 is formed by ion doping the first material layer 210 at the bottom of the second trench 222 using the second pattern layer 206 as a mask, wherein the ion doped ions are second ions.
The second sacrificial layer 241 is located at the bottom of the second groove 222 in the direction perpendicular to the surface of the substrate, and the second sacrificial layer 241 is located on the substrate of the second region II.
The second sacrificial layer 241 has a second dimension C in a first direction parallel to the substrate surface.
The second sacrificial layer 241 is formed by doping the second ions in the first material layer 210 at the bottom of the second trench 221, and the first material layer 210, which is not doped with the second ions, at the bottom of the first mask layer 220 is formed as the third mask layer 251.
The third mask layer 251 is located at the bottom of the first mask layer 220 along a direction perpendicular to the substrate surface, and in a first direction parallel to the substrate surface, the third mask layer 251 has a third dimension a.
In this embodiment, the first trench 221 is located in the first area I, and then the second mask layer 250 and the third mask layer 251 are located on the substrate surface of the first area I.
The second sacrificial layer 241 defines the location of the fourth slot.
The ion doping process comprises the following steps: an ion implantation process or a solid state source doping process.
In this embodiment, the ion doping process is an ion implantation process. In other embodiments, the ion doping process is a solid state source doping process.
The second ion includes: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
In this embodiment, the second ion is a boron ion.
The first material layer 210 at the bottom of the second trench 222 is formed as the second sacrificial layer 241 through an ion implantation process such that the material of the second sacrificial layer 241 is different from the material of the third mask layer 251.
The second sacrificial layer 241 is formed by doping the first material layer 210 with second ions, and the second ions enter into the ion gaps of the first material layer 210, so that the ion state of the second sacrificial layer 241 is stable and is not easy to be etched.
Referring to fig. 7, the first sacrificial layer 240 is removed to form a third groove 252; the second sacrificial layer 241 is removed to form a fourth groove 253.
In this embodiment, before forming the third groove 252 and the fourth groove 253, further includes: the second graphics layer 206 is removed.
The process of removing the second pattern layer 206 is an ashing process.
And the second pattern layer 206 is removed by adopting an ashing process, so that the process is simple. And has less damage to the first mask layer 220, the first sacrificial layer 240, the second sacrificial layer 241 and the third sacrificial layer 242
In this embodiment, the method further includes: the third sacrificial layer 242 is removed to form a fifth trench 254.
The first sacrificial layer 240 has a fourth dimension B in a first direction parallel to the substrate surface, and the third trench 252 has a fourth dimension B.
The second sacrificial layer 241 has a second dimension C in a first direction parallel to the substrate surface, and the fourth groove 253 has the second dimension C.
In a first direction parallel to the substrate surface, the third sacrificial layer 242 has a fourth dimension B, and the fifth trench 254 has a fourth dimension B.
The second mask layer 250 and the third mask layer 251 are located on the substrate surface of the first region I.
The fourth trench 253 is formed for the transfer of the second trench 222, and the fourth trench 253 is located between the third mask layers 251 of the adjacent first regions I.
The third and fifth trenches 252 and 254 are located between adjacent second and third mask layers 250 and 251.
In this embodiment, after the first mask layer 220 is removed, the first sacrificial layer 240 and the second sacrificial layer 241 are removed.
In other embodiments, after removing the first sacrificial layer 240 and the second sacrificial layer 241, the first mask layer 220 is removed.
In this embodiment, the second sacrificial layer 241 is removed during the process of removing the first sacrificial layer 240. In other embodiments, the first sacrificial layer and the second sacrificial layer are not removed at the same time.
In this embodiment, the third sacrificial layer 242 is removed during the process of removing the first sacrificial layer 240. In other embodiments, the first sacrificial layer and the third sacrificial layer are not removed at the same time.
In this embodiment, the second sacrificial layer 241 and the third sacrificial layer 242 are removed during the process of removing the first sacrificial layer 240.
In the process of removing the first, second and third sacrificial layers 240, 241 and 242, there is a first etching rate for the first, second and third sacrificial layers 240, 241 and 242, and a second etching rate for the first material layer 210, the first etching rate being greater than the second etching rate.
In a specific embodiment, the ratio of the first etching rate to the second etching rate is 5 to 10.
The first etching rate is greater than the second etching rate, so that the consumption of the second mask layer 250 and the third mask layer 251 can be ensured to be small while the first sacrificial layer 240, the second sacrificial layer 241 and the third sacrificial layer 242 are removed.
The process of removing the first, second and third sacrificial layers 240, 241 and 242 includes: a dry etching process or a wet etching process.
In this embodiment, the process of removing the first sacrificial layer 240, the second sacrificial layer 241 and the third sacrificial layer 242 is a wet etching process; the parameters of the wet etching process include: HF and H 2 Hydrofluoric acid solution with O volume ratio of 1/2000-1/100.
And using the second mask layer 250 and the third mask layer 251 as masks to form a patterned layer of a subsequent SADP process, thereby forming fin portions with different pitches. Please refer to fig. 8 to fig. 14 in detail.
Referring to fig. 8, the second mask layer 250 and the third mask layer 251 are used as masks to etch the initial first mandrel layer 204 to form a first mandrel layer 260, wherein a first opening 261 is formed between adjacent first mandrel layers 260 of the first region I, and a second opening 262 is formed between adjacent first mandrel layers 260 of the first region I.
In this embodiment, a sixth opening 263 is further provided between adjacent first mandrel layers 260 in the first region I.
The first opening 261 is located at the bottom of the third slot 252. The second opening 262 is located at the bottom of the fourth groove 253. The sixth opening 263 is located at the bottom of the fifth groove 254.
In a first direction parallel to the substrate surface, the first opening 261 has a size equal to the third groove and is a fourth size B, the sixth opening 263 has a size equal to the fifth groove 254 and is a fourth size B, and the second opening 262 has a size equal to the fourth groove and is a second size C.
The second opening 262 is located on the second zone II substrate.
The material of the initial first mandrel layer 204 is polysilicon, and the material of the first mandrel layer 260 is polysilicon.
The process of etching the initial first mandrel layer 204 includes: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the second mask layer 250 and the third mask layer 251 are used as masks, and the third protection layer 205 and the initial first mandrel layer 204 are etched to form a first mandrel layer 260.
The first opening 261 and the second opening 262 expose the surface of the second protection layer 203. The second protective layer 203 is an etch stop layer when the initial first mandrel layer 204 is etched.
Referring to fig. 9, a first sidewall 270 is formed on a sidewall of the first mandrel layer 260, and the first opening 261 is filled with the first sidewall 270, and the first sidewall 270 is further located on a sidewall of the second opening 262.
In this embodiment, the first sidewall 270 further fills the sixth opening 263.
The material of the first sidewall 270 includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride or silicon oxycarbide.
In this embodiment, the material of the first sidewall 270 is silicon nitride.
The method for forming the first side wall 270 includes: forming an initial first sidewall material layer within the first opening 261, within the second opening 262, and on the surface of the first mandrel layer 260; and etching back the initial first sidewall material layer until the surface of the first mandrel layer 260, the bottom surfaces of the first opening 261 and the second opening 262 are exposed, thereby forming the first sidewall 270.
Referring to fig. 10, after the first sidewall 270 is formed, the first mandrel layer 260 is removed.
In this embodiment, before removing the first mandrel layer 260, removing the third protection layer 205 on top of the first mandrel layer 260 is further included.
The process of removing the first mandrel layer 260 includes: a dry etching process or a wet etching process.
In this embodiment, the material of the first mandrel layer 260 is polysilicon, and the process of removing the first mandrel layer 260 is a wet etching process.
Referring to fig. 11, after the first mandrel layer 260 is removed, the initial second mandrel layer 202 is etched using the first sidewall 270 as a mask, and a second mandrel layer 280 is formed on the first region I substrate 200, and the second mandrel layer 280 is further located on the second region II substrate 200.
In this embodiment, the method further includes: etching the second protective layer 203 and the initial second mandrel layer 202 with the first sidewall 270 as a mask; the second mandrel layer 280 is formed.
The second mandrel layer 280 of the first region I has a third opening 281 and a fourth opening 282 on both sides thereof, respectively.
The third opening 281 has a third dimension a in a first direction parallel to the substrate surface; the fourth opening 282 has a fifth dimension D.
A fifth opening 283 is formed between adjacent second mandrel layers 280 in the second region II.
The fifth opening 283 has a second dimension C in a first direction parallel to the substrate surface.
The third opening 281, the fourth opening 282, and the fifth opening 283 expose the surface of the first protective layer 201.
Referring to fig. 12, a second sidewall 290 is formed on the sidewall of the second mandrel layer 280, and the second sidewall 290 is further located on the substrate 200 in the second region II.
In a first direction parallel to the substrate surface, the second sidewall 290 has a sixth dimension e, the third dimension a is greater than twice the sixth dimension e, and the fifth dimension D is greater than twice the sixth dimension e.
The second sidewall 290 covers the sidewalls of the third opening 281, the fourth opening 282 and the fifth opening 283.
The dimensions of the second sidewall 290 in the first region I in the first direction parallel to the substrate surface determine the width of the fin to be subsequently formed. The second side walls are located in the third opening 281 and the fourth opening 282, and then in the first direction parallel to the substrate surface, the size of the third opening 281 and the size of the fourth opening 282 determine the distance between the second side walls 290 located in the third opening 281 and the size of the fourth opening 282 determines the distance between the second side walls 290 located in the fourth opening 282.
The second side walls 290 of the side walls of the third opening 281 are separated by a first distance a, where the first distance a is the dimension of the third opening 281 minus the thickness of the two second side walls 290.
In this embodiment, the first distance a=the third dimension a-2×the sixth dimension e.
The distance between the two second side walls 290 of the side wall of the fourth opening 282 is a second distance b, and the second distance b is the size of the fourth opening 282 minus the thickness of the two second side walls 290.
In this embodiment, the second distance b=fifth dimension D-2×sixth dimension e.
The distance between the second sidewalls 290 on both sides of the second mandrel layer 280 in the first region I is a third distance c, and the third distance c is equal to the size of the second mandrel layer 280 in the first region I.
In this embodiment, the third distance c=a fourth dimension B.
The materials of the second sidewall 290 include: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride or silicon oxycarbide.
In this embodiment, the material of the second sidewall 290 is silicon nitride.
The method for forming the second sidewall 290 includes: forming an initial second sidewall material layer in the third opening 281, in the fourth opening 282, in the fifth opening 283 and on the surface of the second mandrel layer 280; and etching the initial second sidewall material layer until the bottom surfaces of the second mandrel layer 280, the third opening 281, the fourth opening 282 and the fifth opening 283 are exposed, thereby forming the second sidewall 290.
Referring to fig. 13, after forming the second sidewall 290, the second mandrel layer 280 is removed; after removing the second mandrel layer 280, the second sidewall 290 of the second region II is removed.
In this embodiment, before removing the second mandrel layer 280, removing the second protective layer 203 on top of the second mandrel layer 280 is further included.
The process of removing the second mandrel layer 280 includes: a dry etching process or a wet etching process.
The method for removing the second sidewall 290 of the second region II includes: forming a third mask layer on the substrate 200, where the third mask layer covers the surface of the second sidewall 290 of the first region I, and exposes the second sidewall 290 of the second region II; and removing the second side wall 290 of the second region II by taking the third mask layer as a mask.
The second side walls 290 have a sixth dimension e, and the distance between the adjacent second side walls 290 in the first region I is a first distance a, a second distance b and a third distance c.
Referring to fig. 14, after removing the second sidewall 290 of the second region II, the substrate 200 is etched with the second sidewall 290 of the first region I as a mask, and a fin 291 is formed in the substrate 200.
The fin 290 has a width of a sixth dimension e.
The pitch between fins 290 includes a first distance a, a second distance b, and a third distance c.
The first distance a=third dimension a-2 x sixth dimension e.
The second distance b=fifth dimension D-2 x sixth dimension e.
The third distance c=fourth dimension B.
Therefore, by adopting the method for forming a semiconductor device provided in this embodiment, the distance between the two second side walls of the side wall of the third opening is the size of the third opening minus the thickness of the two second side walls; the third opening is formed by reversely transferring the third mask layer, the size of the third opening is equal to that of the third mask layer, the size of the third mask layer is equal to that of the first mask layer, and the third opening has a third size. The distance between the two second side walls of the side wall of the fourth opening is the size of the fourth opening minus the thickness of the two second side walls; and the fourth opening is formed by reversely transferring the second mask layer, and the size of the fourth opening is equal to the size of the second mask layer and is the fifth size. The distance between the second side walls on two sides of the second mandrel layer in the first area is the size of the second mandrel layer, the second mandrel layer is formed by reversely transferring the third groove, the size of the second mandrel layer is equal to the size of the third groove, the third groove is formed by removing the first sacrificial layer, and the size of the third groove is equal to the size of the first sacrificial layer and is the fourth size. The fin parts with multiple pitches can be obtained by reasonably designing the numerical values of the third dimension A, the fourth dimension B and the fifth dimension D.
Correspondingly, the embodiment also provides a semiconductor device formed by adopting the method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A method of forming a semiconductor device, comprising:
providing a substrate comprising a plurality of first regions and a plurality of second regions located between adjacent first regions;
forming a first material layer on the surfaces of the first area and the second area of the substrate;
forming a first mask layer on the surface of the first material layer, wherein the first mask layer is internally provided with a first groove and a second groove which are separated from each other, the first groove is positioned in a first area, the second groove exposes a second area, the first groove has a first size in a first direction parallel to the surface of the substrate, the second groove has a second size, and the first mask layer has a third size;
doping first ions in a part of the first material layer at the bottom of the first groove, forming a first sacrificial layer in the first material layer, enabling the first material layer without the first ions at the bottom of the first groove to form a second mask layer, enabling one side wall of the first sacrificial layer to be flush with one side wall of the first groove in a first direction parallel to the surface of the substrate, enabling the first sacrificial layer to have a fourth size in the first direction parallel to the surface of the substrate, enabling the fourth size to be smaller than the first size, enabling the second mask layer to have a fifth size, and enabling the value of the fifth size to be unequal to that of the third size;
Doping second ions in the first material layer at the bottom of the second groove to form a second sacrificial layer, and enabling the first material layer without doping the second ions at the bottom of the first mask layer to form a third mask layer, wherein the second sacrificial layer has a second size in a first direction parallel to the surface of the substrate, and the third mask layer has a third size;
removing the first sacrificial layer to form a third groove;
and removing the second sacrificial layer to form a fourth groove.
2. The method of forming a semiconductor device of claim 1, wherein the first trench has opposing first and second sidewalls, the first sacrificial layer being flush with the first sidewall of the first trench; the method for forming the semiconductor device further comprises the following steps: doping first ions in a part of the first material layer at the bottom of the first groove after forming a first mask layer, and forming a third sacrificial layer, wherein the second mask layer is positioned between the first sacrificial layer and the third sacrificial layer, the third sacrificial layer is flush with the second side wall of the first groove, and the third sacrificial layer has a sixth size in a first direction parallel to the surface of the substrate; and removing the third sacrificial layer to form a fifth groove.
3. The method for forming a semiconductor device according to claim 2, wherein the first sacrificial layer is formed after the third sacrificial layer is formed.
4. The method of forming a semiconductor device according to claim 2, wherein the method of forming the first sacrificial layer comprises: forming a first pattern layer on the first mask layer and the first material layer, wherein a first opening is formed in the first pattern layer, and the first opening exposes the first groove; and performing first inclined ion implantation on the first side wall of the first groove and the first material layer at the bottom of the first groove by taking the first graph layer as a mask to form the first sacrificial layer.
5. The method for forming a semiconductor device according to claim 4, wherein after the first sacrificial layer is formed, a third sacrificial layer is formed; the method for forming the third sacrificial layer comprises the following steps: and performing second inclined ion implantation on the second side wall of the first groove and the first material layer at the bottom of the first groove by taking the first graph layer as a mask to form the third sacrificial layer.
6. The method according to claim 4 or 5, wherein the first oblique ion implantation has a first angle between an implantation direction and a normal direction of the substrate surface, the first angle being 0 degrees or more and 10 degrees or less.
7. The method according to claim 5, wherein the second oblique ion implantation has a second angle between an implantation direction and a normal direction of the substrate surface, the second angle being 0 degrees or more and 10 degrees or less.
8. The method of forming a semiconductor device according to claim 1, wherein a material of the first material layer comprises: amorphous silicon, amorphous carbon, polysilicon, siCO or SiCOH.
9. The method of forming a semiconductor device according to claim 1, wherein the first ions comprise: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
10. The method of forming a semiconductor device according to claim 1, wherein the method of forming the second sacrificial layer comprises: forming a second pattern layer on the first mask layer and the first material layer, the second pattern layer exposing the second groove; and carrying out ion doping on the first material layer at the bottom of the second groove by taking the second graph layer as a mask, wherein the ion doped ions are second ions, so as to form the second sacrificial layer.
11. The method of forming a semiconductor device of claim 10, wherein the ion doping process comprises: an ion implantation process or a solid state source doping process.
12. The method of forming a semiconductor device according to claim 1 or 10, wherein the second ions include: arsenic ions, boron ions, phosphorus ions, gallium ions or indium ions.
13. The method of forming a semiconductor device of claim 1, wherein the material of the first mask layer comprises: polysilicon, silicon nitride, titanium oxide or titanium nitride.
14. The method of forming a semiconductor device according to claim 1, wherein after removing the first mask layer, the first sacrificial layer and the second sacrificial layer are removed.
15. The method of forming a semiconductor device according to claim 1, wherein the second sacrificial layer is removed during the removal of the first sacrificial layer.
16. The method of forming a semiconductor device according to claim 1, wherein the substrate comprises: the substrate, the initial first dabber layer that is located the substrate surface and the initial second dabber layer that is located initial first dabber layer surface.
17. The method of forming a semiconductor device of claim 16, wherein the substrate further comprises: the first protection layer is formed on the surface of the substrate, and the initial first mandrel layer is positioned on the surface of the first protection layer; forming a second protective layer on the surface of the initial first mandrel layer, wherein the initial second mandrel layer is positioned on the surface of the second protective layer; and forming a third protective layer on the surface of the initial second mandrel layer, wherein the first material layer is positioned on the surface of the third protective layer.
18. The method for forming a semiconductor device according to claim 17, wherein the method for forming a semiconductor device further comprises: etching the initial first mandrel layer by taking the second mask layer and the third mask layer as masks to form a first mandrel layer, wherein a first opening is formed between adjacent first mandrel layers in the first region, the first opening has a first size, and a second opening is formed between the first mandrel layers in the adjacent first region; forming a first side wall on the side wall of the first mandrel layer, wherein the first side wall fills the first opening, and the first side wall is also positioned on the side wall of the second opening; removing the first mandrel layer after forming the first side wall; after the first mandrel layer is removed, the first side wall is used as a mask, the initial second mandrel layer is etched, a second mandrel layer is formed on the first area substrate, the second mandrel layer is further positioned on the second area substrate, two sides of the second mandrel layer of the first area are respectively provided with a third opening and a fourth opening, and in a first direction parallel to the surface of the substrate, the third opening is provided with a first size, and the fourth opening is provided with a fourth size; forming a second side wall on the side wall of the second mandrel layer, wherein the second side wall is further positioned on the second area substrate, the second side wall covers the third opening and the side wall of the fourth opening, the second side wall has a sixth size, the first size is larger than twice of the sixth size, and the fourth size is larger than twice of the sixth size; removing the second mandrel layer after forming the second side wall; removing the second side wall of the second region after removing the second mandrel layer; and after removing the second side wall of the second region, etching the substrate by taking the second side wall of the first region as a mask, and forming a fin part in the substrate.
19. A semiconductor device formed by the method of any one of claims 1 to 18.
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CN105336793A (en) * 2014-07-29 2016-02-17 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof
CN106856190A (en) * 2015-12-09 2017-06-16 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure

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