CN105336793A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN105336793A CN105336793A CN201410367354.XA CN201410367354A CN105336793A CN 105336793 A CN105336793 A CN 105336793A CN 201410367354 A CN201410367354 A CN 201410367354A CN 105336793 A CN105336793 A CN 105336793A
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Abstract
The invention discloses a semiconductor device and a forming method thereof. The forming method comprises the steps as follows: a substrate is provided; a sacrificial layer is formed on the surface of the substrate; an opening for exposing partial surface of the substrate is formed in the sacrificial layer; a barrier layer is formed at the bottom of the opening; a first semiconductor layer is formed on the surface of the barrier layer and is doped with first ions; a first doped region is formed at the bottom of the first semiconductor layer; the first semiconductor layer is doped with second ions; a second doped region is formed at the top of the first doped region; the second ions and the first ions are different in conductive type; after the first doped region and the second doped region are formed, the sacrificial layer is removed and the surface of the substrate is exposed; after the sacrificial layer is removed, a second semiconductor layer is formed on the surface of the substrate and is doped with the first ions; and a source region and a drain region are formed at two sides of the first doped region and the second doped region respectively. The performance of the formed semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor device and forming method thereof.
Background technology
Along with the fast development of semiconductor technology, in order to meet the development of various electronic equipment, power supply for integrated circuit (IC) also has more various technical need, such as adopt the different voltage regulator such as stepup transformer (Boostconverter), reducing transformer (Buckconverter) to combine, meet the different electrical power demand of various integrated circuit.Therefore, whether can provide all kinds of different ic power, also become one of key factor of electronic product development.
Junction field effect transistor (JunctionFieldEffectTransistor, be called for short JFET) be widely used in various device due to its good performance, especially junction field effect transistor has good voltage regulation capability, therefore, it is possible to as the voltage regulator of integrated circuit front-end.
Existing jfet structure as shown in Figure 1, comprising: substrate 100; Be positioned at the grid doped region, top 101 of substrate 100, the top surface of grid doped region, described top 101 flushes with described substrate 100 surface, has the first Doped ions in grid doped region, described top 101; Be positioned at the channel doping district 102 bottom grid doped region, described top 101, have the second Doped ions in described channel doping district 102, the conduction type of described second Doped ions is contrary with the first Doped ions; Be positioned at the bottom gate doped region 103 bottom described channel doping district 102, in described bottom gate doped region 103, there is the first Doped ions; Be positioned at source region 104 and the drain region 105 of substrate 100, described source region 104 and drain region 105 lay respectively at both sides, grid doped region 101, described top, described source region 104 is connected with described channel doping district 102 with drain region 105, and mutually isolated by isolation structure 106 between described source region 104 and drain region 105 and grid doped region 101, top.
But the yield of existing junction field effect transistor is lower, poor-performing, the structure or the manufacturing process that need by improving described junction field effect transistor, to improve device performance.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and forming method thereof, improves the performance of semiconductor device.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising: substrate is provided; Form sacrifice layer at described substrate surface, there is in described sacrifice layer the opening exposing section substrate surface; On the formation barrier layer, bottom of described opening; The first semiconductor layer is formed at described barrier layer surface; Adulterate the first ion in described first semiconductor layer, and the bottom section in described first semiconductor layer forms the first doped region; Adulterate the second ion in described first semiconductor layer, and form the second doped region at described first top, doped region, described second ion is different from the conduction type of the first ion; After described first doped region of formation and the second doped region, remove described sacrifice layer, and expose substrate surface; After the described sacrifice layer of removal, form the second semiconductor layer at described substrate surface; Adulterate the first ion in described second semiconductor layer, forms source region and drain region respectively in described first doped region and the second both sides, doped region.
Optionally, also comprise: before the described barrier layer of formation, form side wall in the sidewall surfaces of described opening; After formation side wall, on the formation barrier layer, bottom of described opening; After the described barrier layer of formation, remove described side wall, and expose substrate surface; After the described side wall of removal, the substrate surface adopting selective epitaxial depositing operation to expose in described open bottom and barrier layer surface form the first semiconductor layer.
Optionally, described barrier layer is identical with the material of described side wall, and before the described side wall of removal, form protective layer at the barrier layer surface of described open bottom, the material of described protective layer is different from the material of described side wall; With described protective layer for mask, etching removes described side wall; After the described side wall of removal, remove described protective layer.
Optionally, the formation process of described protective layer comprises: in described sacrificial layer surface and opening, form diaphragm, and full described opening filled by described diaphragm; Planarization is carried out to described diaphragm, till exposing side wall top surface.
Optionally, described barrier layer is different from the material of described side wall, after the described barrier layer of formation, adopts etching technics to remove described side wall.
Optionally, the formation process of described first semiconductor layer comprises: the substrate surface exposed using described open bottom is as Seed Layer, selective epitaxial depositing operation is adopted to form the first semiconductor film in described open bottom, described first semiconductor film covers described barrier layer, and the surface of described first semiconductor film higher than or flush in described sacrificial layer surface; Carry out planarization to described first semiconductor film, till exposing described sacrificial layer surface, form the first semiconductor layer, the surface of described first semiconductor layer flushes with sacrificial layer surface; After described flatening process, in described first semiconductor layer, form described first doped region and the second doped region.
Optionally, the thickness of described side wall is less than 1/4 of described A/F.
Optionally, also comprise: after formation first doped region and the second doped region, form the second mask layer in the first semiconductor layer surface, described second mask layer is different from the material of the first semiconductor layer.
Optionally, the surface of described first semiconductor layer is lower than described sacrificial layer surface, the formation process of described second mask layer comprises: form the second mask material film at sacrifice layer and the first semiconductor layer surface, the surface of described second mask material film higher than or flush in described sacrificial layer surface; Second mask material film described in planarization, till exposing sacrificial layer surface.
Optionally, the formation process of described first semiconductor layer comprises: in described opening, form the first semiconductor layer, and described first semiconductor layer is covered in described barrier layer surface, and the surface of described first semiconductor layer flushes with sacrificial layer surface; Etching technics is carried out back to described first semiconductor layer, makes the surface of described first semiconductor layer lower than described sacrificial layer surface.
Optionally, the surface of described first semiconductor layer flushes in described sacrificial layer surface, and the formation process of described second mask layer comprises: form the second mask material film at sacrifice layer and the first semiconductor layer surface; Second mask material film described in etched portions, till exposing sacrificial layer surface, forms the second mask layer in the first semiconductor layer surface.
Optionally, also comprise: after the described source region of formation and drain region, remove described second mask layer.
Optionally, described sacrificial layer surface also has the first mask layer, and the material of described first mask layer is different from the material of sacrifice layer.
Optionally, the formation process of described sacrifice layer comprises: form expendable film at substrate surface; Form the first mask layer on described expendable film surface, described first mask layer exposes the surface of partial sacrifice film; With described first mask layer for mask, etch described expendable film, till exposing substrate surface, form sacrifice layer.
Optionally, the material on described barrier layer is silica; The formation process on described barrier layer is thermal oxidation technology; The thickness on described barrier layer is 10 nanometer ~ 100 nanometers.
Optionally, described first ion is P type ion, and described P type ion is indium ion or boron ion; Described second ion is N-type ion, and described N-type ion is phosphonium ion or arsenic ion.
Optionally, described first ion is N-type ion, and described N-type ion is phosphonium ion or arsenic ion; Described second ion is P type ion, and described P type ion is indium ion or boron ion.
Optionally, the technique forming the first doped region in the first semiconductor layer is ion implantation technology or in-situ doped technique; The technique forming the second doped region in the first semiconductor layer is ion implantation technology; The technique forming source region and drain region in the second semiconductor layer is ion implantation technology or in-situ doped technique.
Optionally, the material of described sacrifice layer is silica, silicon nitride, silicon oxynitride or amorphous carbon; The material of described first semiconductor layer is silicon, germanium, SiGe or carborundum; The material of described second semiconductor layer is silicon, germanium, SiGe or carborundum; The formation process of described second semiconductor layer is selective epitaxial depositing operation.
Accordingly, the present invention also provides a kind of semiconductor device adopting above-mentioned any one method to be formed, and comprising: substrate; Be positioned at the barrier layer of described substrate surface; Be positioned at the first semiconductor layer of described barrier layer surface; Be positioned at the first doped region of described first semiconductor layer, doped with the first ion in described first doped region, described first doped region is positioned at the bottom section of the first semiconductor layer; Be positioned at the second doped region of described first semiconductor layer, doped with the second ion in described second doped region, described second doped region is positioned at the top of described first doped region, and described second ion is different from the conduction type of the first ion; Be positioned at the second semiconductor layer of the substrate surface of described first semiconductor layer and both sides, barrier layer; Be positioned at source region and the drain region of the second semiconductor layer, described source region and drain region lay respectively at described first semiconductor layer and both sides, barrier layer, and doped with the first ion in described source region and drain region.
Compared with prior art, technical scheme of the present invention has the following advantages:
In formation method of the present invention, open bottom in sacrifice layer forms barrier layer, the first semiconductor layer is formed at described barrier layer surface, adulterate the first ion in described first semiconductor layer, the first doped region is formed in the bottom of described first semiconductor layer, adulterate the second ion in described first semiconductor layer, and to form the second doped region being positioned at the first top, doped region, and described first ion is different from the conduction type of the second ion.Wherein, described first doped region is as the channel doping district of junction field effect transistor, and described second doped region is as top doped region.Afterwards, remove sacrifice layer, and form the second semiconductor layer in the both sides of the first semiconductor layer, by first ion that adulterates in the second semiconductor layer, can in the formation source region, both sides of the first doped region and the second doped region and drain region, and described source region can be connected with the first doped region with drain region.Because described source region and drain region are formed after formation first doped region and the second doped region, the technique that can avoid the formation of the first doped region and the second doped region makes formed source region and drain region that transition diffusion occur, thus ensure that the functional of formed source region and drain region, be conducive to preventing leakage current.And, because described barrier layer can stop the first ion in the first doped region to spread in substrate, after apply bias voltage between described first doped region and the second doped region, the first ion in the first doped region can be enable only to spread in the second doped region, described second doped region and the first doped region is made to be easy to form depletion layer, and without the need to forming extra bottom gate doped region bottom the first doped region.Owing to not having by bottom gate doped region in formed junction field effect transistor, thus the technology difficulty of junction field effect transistor can be reduced, and, avoid performance because of formed bottom gate doped region bad and the performance of transistor is caused damage.
Further, before the described barrier layer of formation, form side wall in the sidewall surfaces of described opening; After formation side wall, on the formation barrier layer, bottom of described opening; After the described barrier layer of formation, remove described side wall, and expose substrate surface.The substrate surface that described open bottom exposes can, as the Seed Layer of subsequent selective epitaxial depositing operation, adopt described selective epitaxial depositing operation can form the first semiconductor layer in opening.Because the formation process of described first semiconductor layer is selective epitaxial depositing operation, make the lattice structure rule of the first formed semiconductor layer neat, thus the electrical property of the first doped region making to be formed in the first semiconductor layer and the second doped region is good.
In structure of the present invention, described substrate surface has barrier layer, described barrier layer surface has the first semiconductor layer, and the bottom section in described first semiconductor layer has the first doped region, the top of described first doped region has the second doped region, and described first doped region is different with the conduction type of the second doped region.Wherein, described first doped region is as the channel doping district of junction field effect transistor, and described second doped region as top doped region, and has source region and drain region in both sides second semiconductor layer of described first doped region and the second doped region respectively.Because described barrier layer can stop the first ion in the first doped region to spread in substrate, after apply bias voltage between described first doped region and the second doped region, the first ion in the first doped region can be enable only to spread in the second doped region, described second doped region and the first doped region is made to be easy to form depletion layer, therefore, without the need to extra bottom gate doped region bottom described first doped region, make the structure of described junction field effect transistor simple, and performance improvement, stability improve.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing junction field effect transistor;
Fig. 2 to Figure 14 is the cross-sectional view of the forming process of the semiconductor device of the embodiment of the present invention.
Embodiment
As stated in the Background Art, lower, the poor-performing of the yield of existing junction field effect transistor.
Please continue to refer to Fig. 1, the operation principle of junction field effect transistor is: when grid doped region, described top 101 and bottom gate doped region 103 all ground connection time, because described source region 104, drain region 105 are identical with the Doped ions in channel region 102, therefore described source region 104, drain region 105 and channel doping district 102 conducting; After apply bias voltage between grid doped region, described top 101 and bottom gate doped region 103, the second Doped ions in described channel doping district 102 and the first Doped ions phase counterdiffusion of pushing up in grid doped region 101 and bottom gate doped region 103, thus make grid doped region, top 101, channel doping district 102 and bottom gate doped region 103 form depletion layer; And the bias voltage applied is larger, to form depletion layer thickness thicker, until pinch off between described source region 104 and drain region 105.Therefore, by regulating the bias voltage size between grid doped region 101, top and bottom gate doped region 103, can the size of current that drain region 105 exports be regulated.
But, because grid doped region, described top 101, channel doping district 102 and bottom gate doped region 103 are all formed by ion implantation technology, and described bottom gate doped region 103 is positioned at the bottom in grid doped region, described top 101 and channel doping district 102, therefore the position of described bottom gate doped region 103 is larger to the distance on substrate 100 surface, make the ion implantation technology difficulty forming described bottom gate doped region 103 larger, and the thickness of the bottom gate doped region 103 formed and described bottom gate doped region 103 are difficult to accurate control to the distance on substrate 100 surface.And, after employing ion implantation technology forms grid doped region, described top 101, channel doping district 102, bottom gate doped region 103, source region 104 and drain region 105, need to adopt one or many annealing with active ions, but, because the distance to substrate 100 surface of described bottom gate doped region 103 is larger, make being heated of bottom gate doped region 103 uneven, and the temperature that bottom gate doped region 103 is subject to is difficult to accurate control, what easily cause in bottom gate doped region 103 is ion-activated uneven, and then has influence on the performance of formed junction field effect transistor.
In order to solve the problem, the present invention proposes a kind of semiconductor device and forming method thereof.Wherein, open bottom in sacrifice layer forms barrier layer, the first semiconductor layer is formed at described barrier layer surface, adulterate the first ion in described first semiconductor layer, the first doped region is formed in the bottom of described first semiconductor layer, by second ion that adulterates in described first semiconductor layer, to form the second doped region being positioned at the first top, doped region, and described first ion is different from the conduction type of the second ion.Remove sacrifice layer afterwards, and form the second semiconductor layer in the both sides of the first semiconductor layer, by first ion that adulterates in the second semiconductor layer, can in the first formation source region, semiconductor layer both sides and drain region.Wherein, described first doped region is as channel doping district, and described second doped region is as top doped region, and described source region and drain region and described first doped region and the second doped region can form junction field effect transistor.After apply bias voltage between described first doped region and the second doped region, described barrier layer can stop the first ion in the first doped region to spread in substrate, thus the first ion in the first doped region is only spread in the second doped region, make described second doped region and the first doped region be easy to form depletion layer, the resistance between source region and drain region is increased.Owing to not having by bottom gate doped region in formed junction field effect transistor, thus the technology difficulty of junction field effect transistor can be reduced, and avoid because of the performance of bottom gate doped region bad and the performance of transistor is caused damage.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 2 to Figure 14 is the cross-sectional view of the forming process of the semiconductor device of the embodiment of the present invention.
Please refer to Fig. 2, substrate 200 is provided; Form sacrifice layer 201 on described substrate 200 surface, there is in described sacrifice layer 201 opening 202 exposing section substrate 200 surface.
Described substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or gallium arsenide substrate etc.).Because follow-up substrate 200 surface adopting selective epitaxial depositing operation to go out in described opening 202 bottom-exposed that needs forms the first semiconductor layer, therefore the material on described substrate 200 surface is semi-conducting material, and in the present embodiment, described substrate 200 is silicon substrate.
Described sacrifice layer 201 covers the follow-up region and the position that need formation second semiconductor layer, follow-up for the formation of source region and drain region in described second semiconductor layer.Opening 202 in described sacrifice layer 201 exposes the follow-up region and the position that need formation first semiconductor layer, follow-uply in described first semiconductor layer need formation first doped region and be positioned at second doped region at the first top, doped region, described first doped region is used for the channel doping district as technotron, and described second doped region is used for as grid doped region, top.
In the present embodiment, described sacrifice layer 201 surface also has the first mask layer 203, and described first mask layer 203 forms the mask of opening 202 as etching in sacrifice layer 201.The material of described first mask layer 203 is different from the material of sacrifice layer 201, and the material of described first mask layer 203 is one or more combinations in silica, silicon nitride, silicon oxynitride, amorphous carbon, titanium nitride, tantalum nitride.In the present embodiment; the material of described first mask layer 203 is silicon nitride; because the physical strength of described silicon nitride is higher; during using described silicon nitride material as mask; can ensure the figure stability of described first mask layer 203 in etching process, in addition, described first mask layer can also as the stop-layer of follow-up planarization or etching technics; with the stop position of definition process, and protect described sacrifice layer 201.
The formation process of described sacrifice layer 201 and opening 202 comprises: form expendable film on substrate 200 surface; Form the first mask layer 203 on described expendable film surface, described first mask layer 203 exposes the surface of partial sacrifice film; With described first mask layer 203 for mask, etch described expendable film, till exposing substrate 200 surface, form sacrifice layer 201, and form opening 202 in described sacrifice layer 201.
The technique of the formation of described expendable film is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process, the technique of described etches sacrificial film is anisotropic dry etch process, makes the sidewall of formed opening 202 surperficial relative to substrate 200 vertical.The material of described sacrifice layer 201 is silica, silicon nitride, silicon oxynitride or amorphous carbon, and the material of described sacrifice layer 201 is different from the material on substrate 200 surface, after ensureing follow-up removal sacrifice layer 201 with this, less to the damage on substrate 200 surface.In the present embodiment, the material of described sacrifice layer 201 is silica, and described silica is easy to be removed, and when removing silica, less to the damage on substrate 200 surface.
In order to avoid forming the bottom gate doped region in technotron, the Doped ions in channel doping district is only spread in grid doped region, top, and follow-up needs form barrier layer in the lower surface of described opening 202.In the present embodiment, before the described barrier layer of formation, need to form side wall in the sidewall surfaces of described opening 202, after the described barrier layer of follow-up formation, remove described side wall and can expose substrate 200 surface, thus the first semiconductor layer can be formed with selective epitaxial depositing operation bottom described opening 202.
In another embodiment, described barrier layer directly can be formed at the lower surface of described opening 202, and without the need to forming described side wall.Follow-up employing chemical vapor deposition method forms the first semiconductor layer at barrier layer surface, and the material of the first semiconductor layer formed is polysilicon.
Please refer to Fig. 3, form side wall 204 in the sidewall surfaces of described opening 202.
Substrate 200 surface bottom described side wall 204 cover part opening 202, follow-uply bottom opening 202, form barrier layer, and after removing described side wall 204, section substrate 200 surface bottom opening 202 can be exposed, substrate 200 surface exposed as the Seed Layer of selective epitaxial depositing operation, can form the first semiconductor layer for follow-up in opening 202.
The formation process of described side wall 204 comprises: form side wall film at sacrifice layer 201 surface and the sidewall of opening 202 and lower surface; Return the described side wall film of etching, till the surface exposing sacrifice layer 201.In the present embodiment, described sacrifice layer 201 surface has the first mask layer 203, described side wall film is formed at described first mask layer 203 surface, and etch described side wall film for described time, till exposing described first mask layer 203, described first mask layer 203 can as the stop-layer of described time etching technics.
After the thickness of described side wall 204 determines the described side wall of follow-up removal, substrate 200 area that described opening 202 bottom-exposed goes out, the first semiconductor layer due to follow-up formation is positioned at exposed substrate 200 surface, in order to avoid the Doped ions in described first semiconductor layer too much spreads in substrate 200, substrate 200 area exposed is unsuitable excessive, and therefore the thickness of described side wall 204 is without the need to blocked up.But, when the thickness of described side wall 204 is less, substrate 200 area that follow-up opening 202 bottom-exposed goes out is less, when with exposed substrate 200 surface, Seed Layer forms the first semiconductor layer the most, the process rate forming described first semiconductor layer is comparatively slow, and therefore the thickness of described side wall 204 is unsuitable too small.In the present embodiment, the thickness of described side wall 204 is less than 1/4 of described opening 202 width, is greater than 1/10 of opening 202 width.
The formation process of described side wall film is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process, the technique of described time etching side wall film is anisotropic dry etch process, can remove the part side wall film of the first mask layer 203 surface and opening 202 lower surface, and reservation is positioned at the part side wall film of opening 202 sidewall surfaces to form side wall 204.
The material of described side wall 204 is silica, silicon nitride, silicon oxynitride or amorphous carbon, and the material of described side wall 204 is different from the material on substrate 200 surface, and the material of described side wall 204 can be identical or different with the material of sacrifice layer 201.Described side wall 204 needs to choose to be easy to removed material, after preventing follow-up removal side wall 204, causes damage to substrate 200 surface.In the present embodiment, the material of described side wall 204 is silica.
Please refer to Fig. 4, after formation side wall 204, on the formation barrier layer, bottom 205 of described opening 202.
Described barrier layer 205 is formed at opening 202 lower surface, the follow-up surface on described barrier layer 205 forms the first semiconductor layer, and the bottom in described first semiconductor layer needs formation first doped region, described barrier layer 205 can prevent the Doped ions in the first doped region from spreading in substrate 200, Doped ions in first doped region is only spread to the second doped region, then the first doped region and the second doped region are easy to form depletion layer, therefore without the need to forming extra bottom gate doped region bottom the first doped region, make the technique of the formation junction field effect transistor of the present embodiment simple.
The material on described barrier layer 205 is insulating dielectric materials, therefore follow-up in the first semiconductor layer during Doped ions, can not in described barrier layer 205 Doped ions, make described barrier layer 205 that blocks ions can be stoped to spread in substrate 200.
In the present embodiment, the formation process on described barrier layer 205 is thermal oxidation technology, and the gas of described thermal oxidation technology is oxygen, and temperature is greater than 600 degrees Celsius.Substrate 200 surface that described thermal oxidation technology can go out opening 202 bottom-exposed is oxidized, and form oxidize semiconductor material in opening 202 lower surface, the formation process on described barrier layer 205 is simple, without the need to adopting extra photoetching or etching technics, namely only can form barrier layer 205 in opening 202 lower surface, and described side wall 204 and the first mask layer 203 surface can not form described barrier layer 205.And barrier layer 205 dense uniform formed, can stop that the Doped ions in the first doped region of follow-up formation spreads in substrate 200 effectively.
In other embodiments, described barrier layer 205 can also adopt nitriding process, and the material on the barrier layer 205 formed is nitridation of semiconductor material.
In the present embodiment, the material on described substrate 200 surface is silicon, and the formation process on described barrier layer 205 is thermal oxidation technology, and the material on the barrier layer 205 formed is silica.The thickness on the barrier layer 205 formed, without the need to blocked up, carries out ensureing that formed barrier layer 205 is enough to stop the diffusion of Doped ions to substrate 200; In the present embodiment, the thickness on described barrier layer 205 is 10 nanometer ~ 100 nanometers.
In the present embodiment; because described barrier layer 205, side wall 204 are identical with the material of sacrifice layer 201, described side wall 204 can be removed in order to follow-up, need to form protective layer on surface, described barrier layer 205; with described protective layer and the first mask layer 203 for mask, etching removes described side wall 204.
In another embodiment, described barrier layer 205 is different from the material of described side wall 204, after the described barrier layer 205 of formation, can directly adopt etching technics to remove described side wall 204.
Please refer to Fig. 5, form protective layer 206 on the surface, barrier layer 205 of described opening 202 (as shown in Figure 4) bottom, the material of described protective layer 206 is different from the material of described side wall 204.
Described protective layer 206 and the first mask layer 203 remove the mask of side wall 204 as subsequent etching; after removing side wall 204; expose the section substrate 200 bottom opening 202, in opening 202, form the first semiconductor layer with selective epitaxial depositing operation so that follow-up.
In the present embodiment, the material of described protective layer 206 is silicon nitride, and the material of described protective layer 206 is identical with the first mask layer 203.The formation process of described protective layer 206 comprises: in described first mask layer 203 surface and opening 202, form diaphragm, full described opening 202 filled by described diaphragm; Planarization is carried out to described diaphragm, till exposing side wall 204 top surface.
The formation process of described diaphragm comprises chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process; Described flatening process is CMP (Chemical Mechanical Polishing) process, in described CMP (Chemical Mechanical Polishing) process, can the thickness of thinning described first mask layer 203, and the top surface area that described side wall 204 is exposed is larger.
Please refer to Fig. 6, with described protective layer 206 for mask, etching removes described side wall 204 (as shown in Figure 5), and exposes substrate 200 surface.
After removing described side wall 204, expose opening 202 (as shown in Figure 4) bottom section substrate 200 surface, follow-up can from described substrate 200 surface to grown on top first semiconductor layer of opening 202.
The etching technics of described removal side wall 204 is dry etch process or wet-etching technology, and described dry etch process can be isotropic dry etch process or anisotropic dry etch process.In the present embodiment, the etching technics of described removal side wall 204 comprises: adopt anisotropic dry etch process to etch described side wall 204, until expose substrate 200 surface; Afterwards, isotropic dry etch process or wet-etching technology is adopted to remove the part side wall 204 of described protective layer 206 sidewall surfaces remnants.
In the present embodiment, the material of described side wall 204 is silica, and the etching liquid removing the wet-etching technology of described side wall 204 is hydrofluoric acid solution, and temperature is 20 degrees Celsius ~ 200 degrees Celsius; The etching gas removing the dry etch process of described side wall 204 comprises hydrocarbon gas, such as CHF
3, CF
4.
Please refer to Fig. 7, after the described side wall 204 (as shown in Figure 5) of removal, remove described protective layer 206 (as shown in Figure 6).
After removing described protective layer 206, again expose the barrier layer 205 of described opening 202 and open bottom, thus follow-uply can form the first semiconductor layer on surface, described barrier layer 205.The technique removing described protective layer 206 is etching technics, and described etching technics is dry etch process or wet-etching technology, and described dry etch process can be isotropic dry etch process or anisotropic dry etch process.
Because material and the barrier layer 205 of described protective layer 206, substrate 200 are all not identical with the material of sacrifice layer 201; described protective layer 206 is made to have higher Etch selectivity relative to described barrier layer 205, substrate 200 and sacrifice layer 201; after removing described protective layer 206, less to the damage of described barrier layer 205, substrate 200 and sacrifice layer 201.In the present embodiment, because protective layer 206 is identical with the material of the first mask layer 203, in the technique of follow-up removal side wall 204, described protective layer 206 and the first mask layer 203 are jointly as etch mask.
In the present embodiment, the material of described protective layer 206 is silicon nitride, and the etching liquid removing the wet-etching technology of described side wall 204 is phosphoric acid solution, and temperature is 20 degrees Celsius ~ 200 degrees Celsius; The etching gas removing the dry etch process of described side wall 204 comprises hydrocarbon gas, such as CHF
3, CF
4.
Please refer to Fig. 8; after the described side wall 204 (as shown in Figure 5) of removal and protective layer 206 (as shown in Figure 6), selective epitaxial depositing operation is adopted to form the first semiconductor layer 207 on substrate 200 surface that described opening 202 bottom-exposed goes out and surface, barrier layer 205.
Described first semiconductor layer 207 is for the formation of the grid structure of junction field effect transistor, follow-up needs form the first doped region and the second doped region in described first semiconductor layer 207, described first doped region is positioned at the bottom section of the first semiconductor layer 207, described second doped region is positioned at the top of described first doped region, wherein, described first doped region is as the channel doping district of junction field effect transistor, and the second doped region is as the grid doped region, top of junction field effect transistor.
In the present embodiment, because described first semiconductor layer 207 is formed at surface, barrier layer 205, first doped region of follow-up formation is positioned at surface, described barrier layer 205, described barrier layer 205 can stop the Doped ions in the first doped region to spread in substrate 200, thus ensure that the Doped ions in the first doped region only can move to the direction of the second doped region, be easy to make the Doped ions compound in described first doped region and the second doped region to form depletion layer.
The material of described first semiconductor layer 207 is silicon, germanium, SiGe or carborundum.In the present embodiment, because described opening 202 bottom-exposed goes out section substrate 200 surface, and the material on described substrate 200 surface is silicon materials, therefore described first semiconductor layer 207 can be formed with selective epitaxial depositing operation, and described selective epitaxial depositing operation is using exposed substrate 200 surface as Seed Layer growth regulation semi-conductor layer 207.Adopt the first Semiconductor substrate 207 lattice structure marshalling, material dense uniform that selective epitaxial depositing operation is formed, with the grid structure that described first semiconductor layer 207 is formed, there is good electrical property, formed transistor stability can be made to improve.
The formation process of described first semiconductor layer 207 comprises: using substrate 200 surface that described opening 202 bottom-exposed goes out as Seed Layer, selective epitaxial depositing operation is adopted to form the first semiconductor film bottom described opening 202, described first semiconductor film covers described barrier layer 205, and the surface of described first semiconductor film higher than or flush in described sacrifice layer 201 surface; Carry out planarization to described first semiconductor film, till exposing described sacrifice layer 201 surface, form the first semiconductor layer 207, the surface of described first semiconductor layer 207 flushes with sacrifice layer 201 surface.
In the present embodiment, the material of described first semiconductor layer 207 is silicon, and the parameter of described selective epitaxial depositing operation comprises: temperature is 500 degrees Celsius ~ 800 degrees Celsius, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas (such as SiH
4, SiH
2cl
2), the flow of described silicon source gas be 1 standard milliliters per minute ~ 1000 standard milliliters are per minute, the gas of described selective epitaxial depositing operation also comprises HCl and H
2, the flow of described HCl be 1 standard milliliters per minute ~ 1000 standard milliliters are per minute, H
2flow be 0.1 Standard Liters per Minute ~ 50 Standard Liters per Minute.
In the present embodiment, follow-up in described first semiconductor layer 207, form the first doped region and the second doped region after, need to form the second mask layer on the first semiconductor layer 207 surface, described second mask layer is as follow-up formation second semiconductor layer and the mask forming source region and drain region.
And, in the present embodiment, the surface of follow-up the second formed mask layer flushes with the surface of sacrifice layer 201, therefore, the surface of described first semiconductor layer 207 needs lower than described sacrifice layer 201 surface, the formation process of described first semiconductor layer 207 also comprises: after described flatening process, carries out back etching technics to described first semiconductor layer 207, makes the surface of described first semiconductor layer 207 lower than described sacrifice layer 201 surface.Described time etching technics is anisotropic dry etch process, due to after flatening process, the surface of described first semiconductor layer 207 is smooth, therefore, after described time etching technics, the surface of described first semiconductor layer 207 still can keep smooth.
In another embodiment, after described flatening process, also can not carry out back etching to the first semiconductor layer 207, form the second mask layer subsequently through deposition and etching technics on described first semiconductor layer 207 surface.
Please refer to Fig. 9, adulterate the first ion in described first semiconductor layer 207, and the bottom section in described first semiconductor layer 207 forms the first doped region 208.
Contrary with follow-up the second doped region doping type be formed in described first doped region 208, make described first doped region 208 can form PN junction with the second doped region of follow-up formation, by described first time doped region 208 and described second doped region between apply bias voltage, the depletion width between described PN junction can be controlled, with this, electric current between source region of follow-up formation and drain region is regulated and controled.
In described first doped region 208, the first ion adulterated is N-type ion or P type ion, and described N-type ion is phosphonium ion or arsenic ion, and described P type ion is indium ion or boron ion.In the present embodiment, described first ion is adulterated by the bottom section of ion implantation technology in the first semiconductor layer 207, to form described first doped region 208.The Implantation Energy of described ion implantation technology is 2kev ~ 5kev, and doping content is 5E17atom/cm
3~ 1E25atom/cm
3.
In another embodiment, described first ion can also be formed in the selective epitaxial deposition process of the first semiconductor layer 207 in preorder, adulterates with the bottom section that in-situ doped technique is mixed in the first semiconductor layer 207.Adopt described first ion of in-situ doped technique doping, the first ion distribution in the first doped region 208 can be made even, formed transistor performance is stablized.
Please refer to Figure 10, adulterate the second ion in described first semiconductor layer 207, and form the second doped region 209 at described first top, doped region 208, described second ion is different from the conduction type of the first ion.
Described second doped region 209 is contrary with the doping type of described first doped region, and therefore described second doped region 209 can form PN junction with described first doped region 208.The source region of follow-up formation is identical with the doping type of described first doped region 208 with drain region, therefore, described first doped region 208 can as the channel doping district of junction field effect transistor, and described second doped region 209 can as the grid doped region, top of technotron.
In described second doped region 209, the doping content of the second ion is higher than the doping content of the first ion in the first doped region 208, the second ion adulterated is N-type ion or P type ion, and described N-type ion is phosphonium ion or arsenic ion, and described P type ion is indium ion or boron ion.When the first ion in the first doped region 208 is P type ion, the second ion in described second doped region 209 is N-type ion; When the first ion in the first doped region 208 is N-type ion, the second ion in described second doped region 209 is P type ion.
In the present embodiment, described second ion is adulterated by the bottom section of ion implantation technology in the first semiconductor layer 207, to form described second doped region 209.The Implantation Energy of described ion implantation technology is 500ev ~ 1kev, and doping content is 5E17atom/cm
3~ 1E25atom/cm
3.
In another embodiment, described second ion can also be formed in the selective epitaxial deposition process of the first semiconductor layer 207 in preorder, adulterates with the top area that in-situ doped technique is mixed in the first semiconductor layer 207.
It should be noted that, after formation first doped region 208 and the second doped region 209, can annealing process be carried out, to activate the first ion in the first doped region 208 and the second ion in the second doped region 209.
Please refer to Figure 11, after formation first doped region 208 and the second doped region 209, form the second mask layer 210 on the first semiconductor layer 207 surface, described second mask layer 210 is different from the material of the first semiconductor layer 207.
Described second mask layer 210 can rear removal sacrifice layer 201, formed the second semiconductor layer and formed source region and drain region time, for the protection of described first semiconductor layer 208.The described material of the second mask layer 210 is different from the material of the material of sacrifice layer 201 and the first semiconductor layer 207, makes to have higher Etch selectivity between the second mask layer 210 and sacrifice layer 201.The material of described second mask layer 210 is one or more combinations in silica, silicon nitride, silicon oxynitride, amorphous carbon.In the present embodiment, described second mask layer 210 comprises silicon oxide layer and is positioned at the silicon nitride layer on silicon oxide layer surface.Described silicon oxide layer for improving the binding ability between silicon nitride layer and the first semiconductor layer 207, and when follow-up removal the second silicon nitride layer, protects the first semiconductor layer 207 surface.
In the present embodiment, the surface of described first semiconductor layer 207 is lower than described sacrifice layer 201 surface, the formation process of described second mask layer 210 comprises: form the second mask material film at sacrifice layer 201 and the first semiconductor layer 207 surface, the surface of described second mask material film higher than or flush in described sacrifice layer 201 surface; Second mask material film described in planarization, till exposing sacrifice layer 201 surface.Wherein, the technique forming described second mask material film is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process; Described flatening process is CMP (Chemical Mechanical Polishing) process.
In another embodiment, the surface of described first semiconductor layer 207 flushes in described sacrifice layer 201 surface, and the formation process of described second mask layer 210 comprises: form the second mask material film at sacrifice layer 201 and the first semiconductor layer 207 surface; Second mask material film described in etched portions, till exposing sacrifice layer 201 surface, forms the second mask layer 210 on the first semiconductor layer 207 surface.The technique forming described second mask material film is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process; The technique etching described second mask material film is isotropic dry etch process.
Please refer to Figure 12, after described second mask layer 210, first doped region 208 of formation and the second doped region 209, remove described sacrifice layer 201 (as shown in figure 11), and expose substrate 200 surface.
After removing described sacrifice layer 201, substrate 200 surface exposed can as the Seed Layer of follow-up formation second semiconductor layer, described second semiconductor layer is for the formation of source region and drain region, because described source region and drain region are formed after formation first doped region 208 and the second doped region 209, therefore, form the technique of described first doped region 208 and the second doped region 209, such as ion implantation technology or annealing process, can not cause damage to the performance in described source region and drain region, thus improve performance and the stability of formed transistor.
The technique removing described sacrifice layer 201 is dry etch process or wet-etching technology, and described dry etch process can be isotropic dry etch process or anisotropic dry etch process.In the present embodiment, the material of described sacrifice layer 201 is silica, and the etching gas of described dry etch process is fluorocarbon gas, such as CF
4, CHF
3; The etching liquid of described wet etching is hydrofluoric acid solution, and temperature is 20 degrees Celsius ~ 200 degrees Celsius.
Please refer to Figure 13, after the described sacrifice layer 201 (as shown in figure 11) of removal, form the second semiconductor layer 211 on described substrate 200 surface.
The material of described second semiconductor layer 211 is silicon, germanium, SiGe or carborundum; The formation process of described second semiconductor layer 211 is selective epitaxial depositing operation
Described second semiconductor layer 211, for the formation of source region and drain region, described source region and drain region, forms junction field effect transistor with the first doped region 208 and the second doped region 209 jointly.
The material of described second semiconductor layer 211 is silicon, germanium, SiGe or carborundum.In the present embodiment, after the described sacrifice layer 201 of removal, expose substrate 200 surface around the first semiconductor layer 207, the formation process of described second semiconductor layer 211 is selective epitaxial depositing operation, and described selective epitaxial depositing operation grows the second semiconductor layer 211 using exposed substrate 200 surface as Seed Layer.
In the present embodiment, the material of described second semiconductor layer 211 is silicon, and the parameter of described selective epitaxial depositing operation comprises: temperature is 500 degrees Celsius ~ 800 degrees Celsius, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas comprises silicon source gas (such as SiH
4, SiH
2cl
2), the flow of described silicon source gas be 1 standard milliliters per minute ~ 1000 standard milliliters are per minute, the gas of described selective epitaxial depositing operation also comprises HCl and H
2, the flow of described HCl be 1 standard milliliters per minute ~ 1000 standard milliliters are per minute, H
2flow be 0.1 Standard Liters per Minute ~ 50 Standard Liters per Minute.
Please refer to Figure 14, adulterate the first ion in described second semiconductor layer 211 (as shown in figure 13), forms source region 212 and drain region 213 respectively in described first doped region 208 and the second both sides, doped region 209.
Described source region 212 is identical with the first doped region 208 with the doping type in drain region 213, contrary with the second doped region 209, and the doping content in described source region 212 and drain region 213 is higher than the doping content of the first doped region 208.Form PN junction between described source region 212 and the second doped region 209, between described drain region 213 and the second doped region 209, form PN junction.When not applying bias voltage to the second doped region 209, described source region 212, conducting between drain region 213 and the first doped region 208; When applying bias voltage to described second doped region 209 and drain region 213, and during the ground connection 212 of source region, and when there is electrical potential difference between described second doped region 209 and drain region 213, described second doped region 209 and can depletion layer be formed between doped region 208, drain region 213, first and source region 212, described depletion layer makes the resistance between source region 212 and drain region 213 increase, thus, by the bias voltage regulating and controlling to apply the second doped region 209, the size of current exported by drain region can be regulated.
In described source region 212 and drain region 213, the first ion adulterated is N-type ion or P type ion, and described N-type ion is phosphonium ion or arsenic ion, and described P type ion is indium ion or boron ion.In the present embodiment, to be adulterated in the second semiconductor layer 211 first ion by ion implantation technology, to form source region 212 and drain region 213, the Implantation Energy of described ion implantation technology is 2kev ~ 5kev, and doping content is 5E17atom/cm
3~ 1E25atom/cm
3.
In another embodiment, described first ion can also be formed in the selective epitaxial deposition process of the first semiconductor layer 207 in preorder, adulterates with the bottom section that in-situ doped technique is mixed in the first semiconductor layer 207.Adopt described first ion of in-situ doped technique doping, the first ion distribution in source region 212 and drain region 213 can be made even, and fine adjustment can be carried out to the doping content of the first ion, make the diverse location in source region 212 and drain region 213, the doping content of the first ion differs, thus meet more complicated process requirements, such as, the doping content bottom source region 212 and drain region 213 can be made to be less than or greater than the doping content at top.
In the present embodiment, after the described source region of formation and drain region, remove described second mask layer, the technique removing described second mask layer is dry etch process or wet-etching technology.
In the present embodiment, open bottom in sacrifice layer forms barrier layer, the first semiconductor layer is formed at described barrier layer surface, adulterate the first ion in described first semiconductor layer, the first doped region is formed in the bottom of described first semiconductor layer, adulterate the second ion in described first semiconductor layer, and to form the second doped region being positioned at the first top, doped region, and described first ion is different from the conduction type of the second ion.Wherein, described first doped region is as the channel doping district of junction field effect transistor, and described second doped region is as top doped region.Afterwards, remove sacrifice layer, and form the second semiconductor layer in the both sides of the first semiconductor layer, by first ion that adulterates in the second semiconductor layer, can in the formation source region, both sides of the first doped region and the second doped region and drain region, and described source region can be connected with the first doped region with drain region.Because described source region and drain region are formed after formation first doped region and the second doped region, the technique that can avoid the formation of the first doped region and the second doped region makes formed source region and drain region that transition diffusion occur, thus ensure that the functional of formed source region and drain region, be conducive to preventing leakage current.And, because described barrier layer can stop the first ion in the first doped region to spread in substrate, after apply bias voltage between described first doped region and the second doped region, the first ion in the first doped region can be enable only to spread in the second doped region, described second doped region and the first doped region is made to be easy to form depletion layer, and without the need to forming extra bottom gate doped region bottom the first doped region.Owing to not having by bottom gate doped region in formed junction field effect transistor, thus the technology difficulty of junction field effect transistor can be reduced, and, avoid performance because of formed bottom gate doped region bad and the performance of transistor is caused damage.
Accordingly, the embodiment of the present invention also provides a kind of semiconductor device adopting said method to be formed, and please continue to refer to Figure 14, comprising: substrate 200; Be positioned at the barrier layer 205 on described substrate 200 surface; Be positioned at first semiconductor layer 207 on surface, described barrier layer 205; Be positioned at the first doped region 208 of described first semiconductor layer 207, doped with the first ion in described first doped region 208, described first doped region 208 is positioned at the bottom section of the first semiconductor layer 207; Be positioned at the second doped region 209 of described first semiconductor layer 207, doped with the second ion in described second doped region 209, described second doped region 209 is positioned at the top of described first doped region 208, and described second ion is different from the conduction type of the first ion; Be positioned at second semiconductor layer 211 on substrate 200 surface of described first semiconductor layer 207 and both sides, barrier layer 205; Be positioned at source region 212 and the drain region 213 of the second semiconductor layer 211, described source region 212 and drain region 213 lay respectively at described first semiconductor layer 207 and both sides, barrier layer 205, and doped with the first ion in described source region 212 and drain region 213.
In the present embodiment, described substrate surface has barrier layer, described barrier layer surface has the first semiconductor layer, and the bottom section in described first semiconductor layer has the first doped region, the top of described first doped region has the second doped region, and described first doped region is different with the conduction type of the second doped region.Wherein, described first doped region is as the channel doping district of junction field effect transistor, and described second doped region as top doped region, and has source region and drain region in both sides second semiconductor layer of described first doped region and the second doped region respectively.Because described barrier layer can stop the first ion in the first doped region to spread in substrate, after apply bias voltage between described first doped region and the second doped region, the first ion in the first doped region can be enable only to spread in the second doped region, described second doped region and the first doped region is made to be easy to form depletion layer, therefore, without the need to extra bottom gate doped region bottom described first doped region, make the structure of described junction field effect transistor simple, and performance improvement, stability improve.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor device, is characterized in that, comprising:
Substrate is provided;
Form sacrifice layer at described substrate surface, there is in described sacrifice layer the opening exposing section substrate surface;
On the formation barrier layer, bottom of described opening;
The first semiconductor layer is formed at described barrier layer surface;
Adulterate the first ion in described first semiconductor layer, and the bottom section in described first semiconductor layer forms the first doped region;
Adulterate the second ion in described first semiconductor layer, and form the second doped region at described first top, doped region, described second ion is different from the conduction type of the first ion;
After described first doped region of formation and the second doped region, remove described sacrifice layer, and expose substrate surface;
After the described sacrifice layer of removal, form the second semiconductor layer at described substrate surface;
Adulterate the first ion in described second semiconductor layer, forms source region and drain region respectively in described first doped region and the second both sides, doped region.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, also comprise: before the described barrier layer of formation, forms side wall in the sidewall surfaces of described opening; After formation side wall, on the formation barrier layer, bottom of described opening; After the described barrier layer of formation, remove described side wall, and expose substrate surface; After the described side wall of removal, the substrate surface adopting selective epitaxial depositing operation to expose in described open bottom and barrier layer surface form the first semiconductor layer.
3. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, described barrier layer is identical with the material of described side wall, before the described side wall of removal, form protective layer at the barrier layer surface of described open bottom, the material of described protective layer is different from the material of described side wall; With described protective layer for mask, etching removes described side wall; After the described side wall of removal, remove described protective layer.
4. the formation method of semiconductor device as claimed in claim 3, it is characterized in that, the formation process of described protective layer comprises: in described sacrificial layer surface and opening, form diaphragm, and full described opening filled by described diaphragm; Planarization is carried out to described diaphragm, till exposing side wall top surface.
5. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, described barrier layer is different from the material of described side wall, after the described barrier layer of formation, adopts etching technics to remove described side wall.
6. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, the formation process of described first semiconductor layer comprises: the substrate surface exposed using described open bottom is as Seed Layer, selective epitaxial depositing operation is adopted to form the first semiconductor film in described open bottom, described first semiconductor film covers described barrier layer, and the surface of described first semiconductor film higher than or flush in described sacrificial layer surface; Carry out planarization to described first semiconductor film, till exposing described sacrificial layer surface, form the first semiconductor layer, the surface of described first semiconductor layer flushes with sacrificial layer surface; After described flatening process, in described first semiconductor layer, form described first doped region and the second doped region.
7. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, the thickness of described side wall is less than 1/4 of described A/F.
8. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, also comprise: after formation first doped region and the second doped region, form the second mask layer in the first semiconductor layer surface, described second mask layer is different from the material of the first semiconductor layer.
9. the formation method of semiconductor device as claimed in claim 8, it is characterized in that, the surface of described first semiconductor layer is lower than described sacrificial layer surface, the formation process of described second mask layer comprises: form the second mask material film at sacrifice layer and the first semiconductor layer surface, the surface of described second mask material film higher than or flush in described sacrificial layer surface; Second mask material film described in planarization, till exposing sacrificial layer surface.
10. the formation method of semiconductor device as claimed in claim 9, it is characterized in that, the formation process of described first semiconductor layer comprises: in described opening, form the first semiconductor layer, described first semiconductor layer is covered in described barrier layer surface, and the surface of described first semiconductor layer flushes with sacrificial layer surface; Etching technics is carried out back to described first semiconductor layer, makes the surface of described first semiconductor layer lower than described sacrificial layer surface.
The formation method of 11. semiconductor device as claimed in claim 8, it is characterized in that, the surface of described first semiconductor layer flushes in described sacrificial layer surface, and the formation process of described second mask layer comprises: form the second mask material film at sacrifice layer and the first semiconductor layer surface; Second mask material film described in etched portions, till exposing sacrificial layer surface, forms the second mask layer in the first semiconductor layer surface.
The formation method of 12. semiconductor device as claimed in claim 8, is characterized in that, also comprise: after the described source region of formation and drain region, remove described second mask layer.
The formation method of 13. semiconductor device as claimed in claim 1, it is characterized in that, described sacrificial layer surface also has the first mask layer, and the material of described first mask layer is different from the material of sacrifice layer.
The formation method of 14. semiconductor device as claimed in claim 13, it is characterized in that, the formation process of described sacrifice layer comprises: form expendable film at substrate surface; Form the first mask layer on described expendable film surface, described first mask layer exposes the surface of partial sacrifice film; With described first mask layer for mask, etch described expendable film, till exposing substrate surface, form sacrifice layer.
The formation method of 15. semiconductor device as claimed in claim 1, is characterized in that, the material on described barrier layer is silica; The formation process on described barrier layer is thermal oxidation technology; The thickness on described barrier layer is 10 nanometer ~ 100 nanometers.
The formation method of 16. semiconductor device as claimed in claim 1, it is characterized in that, described first ion is P type ion, described P type ion is indium ion or boron ion; Described second ion is N-type ion, and described N-type ion is phosphonium ion or arsenic ion.
The formation method of 17. semiconductor device as claimed in claim 1, it is characterized in that, described first ion is N-type ion, and described N-type ion is phosphonium ion or arsenic ion; Described second ion is P type ion, and described P type ion is indium ion or boron ion.
The formation method of 18. semiconductor device as claimed in claim 1, is characterized in that, the technique forming the first doped region in the first semiconductor layer is ion implantation technology or in-situ doped technique; The technique forming the second doped region in the first semiconductor layer is ion implantation technology; The technique forming source region and drain region in the second semiconductor layer is ion implantation technology or in-situ doped technique.
The formation method of 19. semiconductor device as claimed in claim 1, is characterized in that, the material of described sacrifice layer is silica, silicon nitride, silicon oxynitride or amorphous carbon; The material of described first semiconductor layer is silicon, germanium, SiGe or carborundum; The material of described second semiconductor layer is silicon, germanium, SiGe or carborundum; The formation process of described second semiconductor layer is selective epitaxial depositing operation.
20. 1 kinds adopt as any one of claim 1 to 19 method the semiconductor device that formed, it is characterized in that, comprising:
Substrate;
Be positioned at the barrier layer of described substrate surface;
Be positioned at the first semiconductor layer of described barrier layer surface;
Be positioned at the first doped region of described first semiconductor layer, doped with the first ion in described first doped region, described first doped region is positioned at the bottom section of the first semiconductor layer;
Be positioned at the second doped region of described first semiconductor layer, doped with the second ion in described second doped region, described second doped region is positioned at the top of described first doped region, and described second ion is different from the conduction type of the first ion;
Be positioned at the second semiconductor layer of the substrate surface of described first semiconductor layer and both sides, barrier layer;
Be positioned at source region and the drain region of the second semiconductor layer, described source region and drain region lay respectively at described first semiconductor layer and both sides, barrier layer, and doped with the first ion in described source region and drain region.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086346A (en) * | 2019-06-13 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN113644063A (en) * | 2020-04-27 | 2021-11-12 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, memory and forming method thereof |
| CN113644065A (en) * | 2020-04-27 | 2021-11-12 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, memory and forming method thereof |
| CN111834212B (en) * | 2019-04-23 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| US12075612B2 (en) | 2020-04-27 | 2024-08-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for forming the same, and memory and method for forming the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62254470A (en) * | 1986-04-28 | 1987-11-06 | Seiko Instr & Electronics Ltd | Manufacture of junction type thin film transistor |
| JP2002329730A (en) * | 2001-05-01 | 2002-11-15 | Sony Corp | Field-effect transistor and its manufacturing method |
| CN1954439A (en) * | 2004-06-24 | 2007-04-25 | 国际商业机器公司 | Integration of strained Ge into advanced CMOS technology |
| CN103715244A (en) * | 2012-09-28 | 2014-04-09 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN103811353A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Junction field-effect transistor and preparation method thereof |
-
2014
- 2014-07-29 CN CN201410367354.XA patent/CN105336793B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62254470A (en) * | 1986-04-28 | 1987-11-06 | Seiko Instr & Electronics Ltd | Manufacture of junction type thin film transistor |
| JP2002329730A (en) * | 2001-05-01 | 2002-11-15 | Sony Corp | Field-effect transistor and its manufacturing method |
| CN1954439A (en) * | 2004-06-24 | 2007-04-25 | 国际商业机器公司 | Integration of strained Ge into advanced CMOS technology |
| CN103715244A (en) * | 2012-09-28 | 2014-04-09 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN103811353A (en) * | 2012-11-08 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Junction field-effect transistor and preparation method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111834212B (en) * | 2019-04-23 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112086346A (en) * | 2019-06-13 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112086346B (en) * | 2019-06-13 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN113644063A (en) * | 2020-04-27 | 2021-11-12 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, memory and forming method thereof |
| CN113644065A (en) * | 2020-04-27 | 2021-11-12 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, memory and forming method thereof |
| CN113644065B (en) * | 2020-04-27 | 2024-03-29 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, memory and forming method thereof |
| CN113644063B (en) * | 2020-04-27 | 2024-03-29 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, memory and forming method thereof |
| US12075612B2 (en) | 2020-04-27 | 2024-08-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for forming the same, and memory and method for forming the same |
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