CN109950311B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109950311B CN109950311B CN201711383823.7A CN201711383823A CN109950311B CN 109950311 B CN109950311 B CN 109950311B CN 201711383823 A CN201711383823 A CN 201711383823A CN 109950311 B CN109950311 B CN 109950311B
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: providing a substrate having a plurality of discrete support structures thereon, the support structures comprising: the first fin part is positioned on the surface of the substrate; forming a first isolation layer on the substrate, wherein the surface of the first isolation layer is lower than the top surface of the first fin part; forming a second fin part on the first isolation layer; and removing at least part of the first fin part, wherein the bottom surface of the opening is lower than that of the second fin part. The substrate is not in contact with the second fin portion, and therefore carriers in the second fin portion are not easy to diffuse into the substrate, and therefore leakage current of the formed semiconductor structure can be reduced.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the devices. However, as the size of the transistor is sharply reduced, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A first fin part is formed by the protrusion of a channel of the FinFET out of the surface of a substrate, and a grid electrode covers the top and the side wall of the original first fin part, so that an inversion layer is formed on each side of the channel, and the on and off of a multi-side control circuit of the first fin part can be controlled. The design can increase the control of the gate to the channel region, thereby well inhibiting the leakage current of the transistor.
However, the leakage current of the semiconductor structure formed by the prior art is still large.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can reduce the leakage current of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of discrete support structures thereon, the support structures comprising: the first fin part is positioned on the surface of the substrate; forming a first isolation layer on the substrate, wherein the first isolation layer covers the side wall of the first fin part, and the surface of the first isolation layer is lower than the top surface of the first fin part; forming a second fin part on the surface of the side wall of the first fin part exposed by the first isolation layer, wherein the second fin part is positioned on the first isolation layer; after the second fin portion is formed, removing part or all of the first fin portion to form an opening, wherein the bottom surface of the opening is lower than the bottom surface of the second fin portion.
Optionally, the support structure further includes: a mask layer located on the first fin portion; after forming the first isolation layer and before removing part or all of the first fin portion, the forming method further includes: and removing the mask layer.
Optionally, the step of forming the substrate and the support structure comprises: providing an initial substrate; forming a patterned mask layer on the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form a substrate and a first fin part positioned on the substrate.
Optionally, the step of forming the mask layer includes: forming an initial mask layer on the initial substrate; forming a graphical pattern layer on the initial mask layer, and etching the initial mask layer and the initial substrate by taking the graphical pattern layer as a mask to form a substrate, a first fin part positioned on the substrate and a mask layer positioned on the first fin part; the step of forming the graphic layer includes: forming a plurality of discrete core layers on the initial mask layer; forming a pattern layer on the surface of the side wall of the core layer; after the patterned layer is formed, the core layer is removed.
Optionally, the thickness of the mask layer is 10nm to 60 nm; the height of the first fin portion is 10 nm-70 nm.
Optionally, the second fin portion is made of silicon, germanium, silicon germanium, or silicon carbide.
Optionally, the process of forming the second fin portion includes a chemical vapor deposition epitaxy process or a solid phase epitaxy process.
Optionally, after forming the second fin portion, the method further includes: forming a protective layer on the second fin portion, wherein the material of the protective layer is different from that of the first fin portion, and the material of the protective layer is different from that of the second fin portion; after removing part or all of the first fin portion, the method further includes: and removing the protective layer.
Optionally, the material of the protective layer is amorphous carbon, silicon nitride or silicon oxide.
Optionally, the second fin top surface is lower than the support structure top surface; the step of forming the protective layer includes: forming an initial protection layer on the second fin portion and the top of the support structure; and carrying out planarization treatment on the initial protection layer until the top surface of the support structure is exposed.
Optionally, the step of forming the initial protection layer includes: a chemical vapor deposition process or an atomic layer deposition process; the process for removing the protective layer comprises a dry etching process.
Optionally, the method further includes: and forming a second isolation layer in the opening, wherein the top surface of the second isolation layer is lower than that of the second fin part.
Optionally, the second isolation layer is made of silicon oxide or a low-k dielectric material.
Optionally, the thickness of the second isolation layer is 2nm to 5 nm.
Optionally, after forming the second isolation layer, the method further includes: and forming a grid electrode structure crossing the second fin part, wherein the grid electrode structure covers part of the top and part of the side wall surface of the second fin part.
Optionally, the thickness of the first isolation layer is 10nm to 60 nm.
Optionally, before removing part or all of the first fin portion, a distance between the top surface of the second fin portion and the top surface of the first fin portion is 2.7nm to 3.3 nm.
Optionally, the material of the first isolation layer is silicon oxide or a low-k dielectric material.
Optionally, the size of the removed first fin portion along a direction perpendicular to the substrate surface is 10nm to 30 nm.
Correspondingly, the technical solution of the present invention further provides a semiconductor structure, which includes: a substrate; a first isolation layer on the substrate; a second fin portion on the first isolation layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first isolation layer is formed on the substrate before the second fin part is formed, the first isolation layer is arranged between the second fin part and the substrate, and the first isolation layer can realize the electrical isolation between the second fin part and the substrate. In addition, after the second fin portion is formed, part or all of the first fin portion is removed to form an opening. And removing part of the first fin parts to enable the base and the rest of the first fin parts to form a substrate, or removing all the first fin parts to enable the base to form the substrate. And the bottom surface of the opening is lower than the bottom surface of the second fin part, so that the side wall of the second fin part is not contacted with the substrate. In summary, the substrate is not in contact with the second fin portion, and carriers in the second fin portion are not easy to diffuse into the substrate, so that leakage current of the formed semiconductor structure can be reduced. In addition, the first isolation layer exposes the first fin portion, the first fin portion is used as seed crystal in the process of forming the second fin portion, the process difficulty of forming the second fin portion can be reduced, the process cost is reduced, and the height of the second fin portion can be easily controlled.
Furthermore, the supporting structure further comprises a mask layer positioned on the first fin portion, and in the process of forming the first isolation layer, the mask layer can reduce the loss of the first fin portion, so that the first fin portion can provide high-quality seed crystals for the second fin portion, and the quality of the formed second fin portion is improved.
Further, after the second fin portion is formed, a protective layer is formed on the second fin portion. In the process of removing at least part of the first fin portion, the protective layer can protect the second fin portion, loss of the second fin portion is reduced, and therefore performance of the formed semiconductor structure can be improved.
Further, removing a part of the first fin parts to enable the base and the rest of the first fin parts to form a substrate, or removing all the first fin parts to enable the base to form the substrate. The forming method further comprises the step of forming a second isolation layer in the opening, wherein the second isolation layer can realize electrical isolation between the grid structure and the substrate, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The formation method of the semiconductor structure has many problems, such as: the resulting semiconductor structure has poor performance.
Now, with a method for forming a semiconductor structure, the reason for the poor performance of the formed semiconductor structure is analyzed:
fig. 1 and 2 are schematic structural views of steps of a method of forming a semiconductor structure.
Referring to fig. 1, a substrate is provided; forming a patterned mask layer 103 on the substrate; and etching the substrate by taking the mask layer 103 as a mask to form a substrate 100 and a first fin part 101 positioned on the substrate 100.
Referring to fig. 2, the mask layer 103 (shown in fig. 1) is removed; after removing the mask layer 103, forming a gate structure 120 crossing the first fin portion 101, wherein the gate structure 120 covers part of the sidewall and the top surface of the first fin portion 101; source and drain doped layers (not shown) are formed in the first fin portions 101 at two sides of the gate structure 120.
The first fin portion 101 is in contact with the substrate 100, and then the first fin portion 101 is electrically connected to the substrate 100. In the working process of the formed semiconductor structure, a channel is formed in the first fin portion 101 below the gate structure 120, so that the source-drain doped layers on two sides of the gate structure 120 are conducted. However, since the first fin 101 is in contact with the substrate 100, carriers in the channel and the source-drain doped layer easily enter the substrate 100, so that the formed semiconductor structure has a large leakage current.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a first isolation layer on the substrate, wherein the surface of the first isolation layer is lower than the top surface of the first fin part; forming a second fin part on the first isolation layer; and removing at least part of the first fin part, wherein the bottom surface of the opening is lower than that of the second fin part. The substrate is not in contact with the second fin portion, and therefore carriers in the second fin portion are not easy to diffuse into the substrate, and therefore leakage current of the formed semiconductor structure can be reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Subsequently, a substrate is provided, wherein the substrate is provided with a plurality of discrete support structures, and the support structures comprise first fin parts positioned on the surface of the substrate.
In this embodiment, the support structure further includes: a mask layer on the first fin. Specifically, in this embodiment, the steps of forming the substrate and the support structure are as shown in fig. 3 to 6.
Referring to fig. 3, an initial substrate 200 is provided.
The initial substrate 200 is used for the subsequent formation of a substrate and a plurality of discrete first fins on the substrate.
In this embodiment, the initial substrate 200 is made of silicon, germanium, or silicon germanium. In other embodiments, the material of the initial substrate may also be a single crystal of a group III-V element material, such as: InP, GaAs, or InGaAs.
A patterned mask layer is subsequently formed on the initial substrate 200.
In this embodiment, the step of forming the mask layer is as shown in fig. 3 to 5.
With continued reference to fig. 3, an initial mask layer 211 is formed on the initial substrate 200.
In this embodiment, the initial mask layer 211 is made of silicon nitride. Silicon nitride has very good etch resistance. In other embodiments, the material of the initial mask layer is silicon oxynitride or amorphous carbon.
In this embodiment, before forming the initial mask layer 211, the method further includes: an initial adhesive layer 210 is formed on the initial substrate 200.
The initial adhesion layer 210 serves to increase adhesion between the initial mask layer 211 and the initial substrate 200.
The material of the initial adhesion layer 210 is silicon oxide.
A patterned pattern layer is subsequently formed on the initial mask layer 211.
In this embodiment, the steps of forming the pattern layer are as shown in fig. 4 to 6.
Referring to fig. 4, a plurality of discrete core layers 221 are formed on the initial mask layer 211.
The core layer 221 is used for support of the subsequent formation of the patterning layer 222.
The core layer 221 is made of amorphous carbon, amorphous silicon or amorphous germanium.
The step of forming the core layer 221 includes: forming an initial core layer on the initial mask layer 211; etching part of the initial core layer to form a core layer 221.
The width of the core layer 221 determines a distance between the subsequently formed first fin portions, and specifically, the distance between the subsequently formed first fin portions is equal to the width of the core layer 221 and equal to the width of the subsequently formed second fin portions; the distance between the core layers minus the thickness of the subsequently formed pattern layer is equal to the distance between the subsequently formed first fin portions.
If the spacing between the core layers 221 is too large, the integration of the formed semiconductor structure is easily reduced; if the pitch between the core layers 221 is too small, the width of the second fin 230 formed subsequently is too small, which results in too small a channel width of the formed semiconductor structure and poor performance of the semiconductor structure. Specifically, in this embodiment, the distance between the core layers 221 is 13nm to 48 nm.
If the width of the core layer 221 is too large, the integration of the formed semiconductor structure is easily reduced; if the width of the core layer 221 is too small, the width of the second fin portion formed subsequently is too small, which may easily result in too small a channel width of the formed semiconductor structure and poor performance of the semiconductor structure. Specifically, in this embodiment, the width of the core layer 221 is 10nm to 38 nm.
Forming a pattern layer on the surface of the side wall of the core layer 221; after the graphics layer is formed, the core layer 221 is removed.
In this embodiment, the step of forming the pattern layer on the sidewall surface of the core layer 221 is shown in fig. 5 and 6.
Referring to fig. 5, an initial graphics layer 223 is formed covering the sidewalls and top of the core layer 221.
The material of the initial graphic layer 223 is different from that of the core layer 221.
Specifically, in this embodiment, the material of the initial pattern layer 223 is silicon oxide or silicon oxynitride. In other embodiments, the material of the initial pattern layer is also silicon nitride.
In this embodiment, the thickness of the initial pattern layer 223 determines the thickness of a pattern layer to be formed later, so as to determine the width of the first fin portion to be formed later.
If the thickness of the initial pattern layer 223 is too large, the width of the first fin portion formed subsequently is too large, which is easy to reduce the integration level of the formed semiconductor structure; if the thickness of the initial pattern layer 223 is too small, the width of the subsequently formed first fin portion 201 is too small, which may easily result in too small a distance between the subsequently formed second fin portions 230, and may easily increase leakage between the adjacent second fin portions 230. Specifically, in this embodiment, the thickness of the initial pattern layer 223 is 3nm to 10 nm.
Referring to fig. 6, the initial graphics layer on the core layer 221 is removed to form a graphics layer 222; after the patterned layer 222 is formed, the core layer is removed (as shown in fig. 5).
The pattern layer is used for etching the initial mask layer and the mask of the initial substrate subsequently.
The process of removing the initial pattern layer on the core layer 221 includes an anisotropic dry etching process.
The process of removing the core layer 221 includes: a dry etching process or a wet etching process.
Referring to fig. 7, the initial substrate 200 (shown in fig. 6) is etched by using the pattern layer 222 (shown in fig. 6) as a mask to form a substrate 202 and a first fin portion 201 on the substrate 202; after the substrate 202 and the first fin portion 201 are formed, the pattern layer 222 is removed.
The step of etching the initial mask layer 211 and the initial substrate 200 includes: etching the initial mask layer 211 by using the pattern layer 222 as a mask to form a mask layer 213; and etching the initial substrate 200 by using the mask layer 213 as a mask to form a substrate 202 and a first fin portion 201 on the substrate 202.
In this embodiment, before forming the first fin portion 201, the step of forming the support structure further includes: the initial adhesion layer 210 (as shown in fig. 6) is etched by using the mask layer 213 as a mask, so as to form an adhesion layer 212.
In this embodiment, the pattern layer 222 and the initial mask layer 211 are made of different materials, and after the mask layer 213 and the first fin 201 are formed, the mask layer 213 still has the pattern layer 222 thereon. In other embodiments, the pattern layer is made of the same material as the initial mask layer, and is consumed in the process of etching the initial mask layer, and is removed in the process of forming the mask layer.
In this embodiment, the process of etching the initial mask layer 211 includes a dry etching process; the process of etching the initial substrate 200 includes a dry etching process. The dry etching has a good line width control, and can control the width of the first fin portion 201.
The dimension of the mask layer 213 in the width direction of the first fin 201 is the same as the width of the first fin 201.
If the width of the first fin portion 201 is too small, it is easy to cause the channel width of the formed semiconductor structure to be too small, thereby affecting the performance of the formed semiconductor structure; if the width of the first fin 201 is too large, the integration of the formed semiconductor structure is easily reduced. The width of the first fin portion 201 is the same as the width of the pattern layer 222. Specifically, in the present embodiment, the width of the first fin portion 201 is 3nm to 10 nm.
The spacing between some adjacent first fins 201 is equal to the width of the core layer 221; the spacing between some adjacent first fins 201 is equal to the spacing between the core layers 221 minus twice the width of the graphics layer 222. In this embodiment, the width of the core layer 221 is equal to the distance between the core layers 221 minus two times the width of the graphics layer 222, that is, in this embodiment, the distance between adjacent first fins 201 is equal to the width of the core layer 221.
The dimension of the first fin portion 201 along the direction perpendicular to the surface of the substrate 202 is the height of the first fin portion 201.
If the height of the first fin 201 is too small, the thickness of the first isolation layer 220 formed subsequently is too small, which is not favorable for electrical isolation between the second fin 230 formed subsequently and the substrate 202; if the height of the first fin 201 is too large, the process difficulty is increased. Specifically, in the present embodiment, the height of the first fin portion 201 is 10nm to 70 nm.
It should be noted that, in the present embodiment, the support structure includes a first fin portion 201; an adhesion layer 212 on top of the first fin 201; and a mask layer 213 on the surface of the adhesion layer 212. In other embodiments, the support structure may not include one or a combination of both an adhesion layer and a mask layer.
Referring to fig. 8, a first isolation layer 220 is formed on the substrate 202, the first isolation layer 220 covers sidewalls of the first fin 201, and a surface of the first isolation layer 220 is lower than a top surface of the first fin 201.
The first isolation layer 220 is used to achieve electrical isolation between the subsequently formed second fin and the substrate 202.
In this embodiment, the first isolation layer 220 is made of silicon oxide. Silicon oxide has good insulating properties. In other embodiments, the material of the first isolation layer is a low-k dielectric material.
The step of forming the first isolation layer 220 includes: forming a first initial isolation layer on the substrate 202, the first initial isolation layer having a top higher than the support structure top surface; and etching the first initial isolation layer to form a first isolation layer 220, wherein the top surface of the first isolation layer 220 is lower than that of the first fin portion 201.
Specifically, in this embodiment, the top surface of the supporting structure is the surface of the mask layer 213. In other embodiments, the support structure does not include the mask layer and the adhesion layer, and the support structure top surface is the first fin top surface.
In this embodiment, the process of forming the first initial isolation layer includes a fluid chemical vapor deposition process. The first initial isolation layer formed by the fluid chemical vapor deposition process has good gap filling capability. In other embodiments, the process of forming the first initial isolation layer comprises an atomic layer deposition process.
The process for etching the first initial isolation layer comprises a dry etching process. In other embodiments, the process of etching the first initial isolation layer may further include a wet etching process.
It should be noted that the surface of the first isolation layer 220 is lower than the top surface of the first fin 201, and the first isolation layer 220 exposes the sidewall of the first fin 201. The sidewalls of the first fin portion 201 exposed by the first isolation layer 220 can be used as seed crystals for forming a second fin portion later.
In the process of etching the first initial isolation layer, the mask layer 213 can protect the first fin portion 201 and reduce damage to the first fin portion 201, so that the first fin portion 201 can provide high-quality seed crystals for a subsequently formed second fin portion, and defects in the subsequently formed second fin portion are reduced.
The dimension of the first fin portion 201 along the direction perpendicular to the surface of the substrate 202 is the height of the first fin portion 201.
If the first fin portion 201 exposed by the first isolation layer 220 is too small in height, more defects in a subsequently formed second fin portion are easily caused, so that the conductivity of the second fin portion is affected; if the height of the first fin portion 201 exposed by the first isolation layer 220 is too large, the thickness of the first isolation layer 220 is too small, which is not favorable for increasing the electrical isolation between the subsequently formed second fin portion and the substrate 202, and is not favorable for reducing the electric leakage. Specifically, in the present embodiment, the height of the first fin portion 201 exposed by the first isolation layer 220 is 2nm to 5 nm.
If the thickness of the first isolation layer 220 is too small, it is not favorable for electrical isolation between the subsequently formed second fin portion and the substrate 202, and thus it is not easy to reduce the leakage of the formed semiconductor structure. The thickness of the first isolation layer 220 is equal to the height of the first fin 201 minus the height of the first fin 201 exposed by the first isolation layer 220.
Referring to fig. 9, a second fin 230 is formed on the sidewall surface of the first fin 201 exposed by the first isolation layer 220, and the second fin 230 is located on the first isolation layer 220.
The second fin 230 serves as a channel for forming the formed semiconductor structure.
In this embodiment, the material of the second fin 230 is monocrystalline silicon. In other embodiments, the material of the second fin portion may be monocrystalline germanium, monocrystalline silicon germanium or monocrystalline III-V element material.
In this embodiment, the process of forming the second fin 230 includes a chemical vapor deposition epitaxy process. In other embodiments, the process of forming the second fin portion includes a solid phase epitaxy process.
In this embodiment, the process parameters for forming the second fin portion 230 include: silicon source gas H2And HCl; the silicon source gas comprises SiH4Or SiH2Cl2One or a combination of two of them; wherein is SiH4、SiH2Cl2The flow rate of HCl and HCl are all 1 sccm-1000 sccm; h2The flow rate of (2) is 0.1slm to 50 slm.
The dimension of the second fin 230 in a direction perpendicular to the surface of the substrate 202 is the height of the second fin 230.
If the height of the second fin 230 is too large, the distance from the channel of the formed semiconductor structure to the bottom of the second fin 230 is large, which is not beneficial to reducing the channel leakage current of the formed semiconductor structure; if the height of the second fin 230 is too small, it is easy to reduce the channel width of the formed transistor, thereby increasing the resistance of the channel. Specifically, in the present embodiment, the distance between the top surface of the second fin 230 and the top surface of the first fin 201 is 2.7nm to 3.3 nm.
The dimension of the second fin 230 along the direction perpendicular to the sidewall surface of the first fin 201 is the width of the second fin 230.
If the width of the second fin 230 is too small, the channel width of the formed semiconductor structure is easily affected; if the width of the second fin 230 is too large, the integration of the semiconductor structure is easily reduced. The width of the second fin 230 is equal to the distance between adjacent first fins 201. Specifically, in this embodiment, the width of the second fin 230 is equal to the width of the core layer 221, and the width of the second fin 230 is 10nm to 38 nm.
It should be noted that, in the present embodiment, the top surface of the second fin 230 is lower than the top surface of the support structure, that is, the top surface of the second fin 230 is lower than the surface of the mask layer 213.
The top surface of the second fin 230 is lower than the top surface of the support structure, and the initial protection layer on the mask layer 213 can be subsequently removed by a planarization process, leaving the initial protection layer on the second fin 230.
Referring to fig. 10, a protection layer 231 is formed on the second fin 230.
The protection layer 231 is used for protecting the second fin portion 230 in the subsequent etching process of the first fin portion 201, and reducing the loss of the second fin portion 230.
In this embodiment, the material of the protection layer 231 is amorphous carbon. In other embodiments, the material of the protection layer may also be amorphous silicon, amorphous germanium or amorphous silicon germanium.
The step of forming the protective layer 231 includes: forming an initial protection layer on top of the second fin 230 and the support structure; the initial passivation layer is planarized until the top of the support structure is exposed, forming a passivation layer 231.
The mask layer 213 can serve as a stop layer for the planarization process. In the planarization process, the mask layer 213 can also protect the first fin portion 201, so that the loss of the first fin portion 201 is reduced, and the height of the first fin portion 201 can be controlled in the subsequent process of etching the first fin portion 201.
In this embodiment, the process of forming the initial protection layer 231 includes a plasma chemical vapor deposition process.
The process parameters for forming the initial protection layer 231 include: the reaction gas comprises benzene, the flow rate of the benzene is 5 sccm-20 sccm, and the gas pressure is 0.13 Pa-0.17 Pa; the radio frequency power is 700W-900W.
The planarization treatment process comprises a chemical mechanical polishing process.
If the thickness of the protection layer 231 is too small, it is not favorable for protecting the second fin portion 230 in the subsequent etching process of the first fin portion 201; if the thickness of the protection layer 231 is too large, the difficulty of removing the protection layer 231 later is easily increased. Specifically, the thickness of the protective layer 231 is 5nm to 100 nm.
Referring to fig. 11, after the protection layer 231 is formed, the mask layer 213 is removed (as shown in fig. 10).
The mask layer 213 is removed to expose the top of the first fin 201, thereby facilitating the subsequent etching of the first fin 201.
The process of removing the mask layer 213 includes: a wet etching process or a dry etching process.
When the process for removing the mask layer 213 is wet etching, the parameters for removing the mask layer 213 include that the etching solution comprises phosphoric acid, and the etching temperature is 700-900 ℃.
After removing the mask layer 213, the method further includes: the adhesive layer 212 is removed. The process of removing the adhesion layer 212 includes a dry etching process or a wet etching process.
Referring to fig. 12, after the second fin 230 is formed, part or all of the first fin 201 is removed to form an opening, and a bottom surface of the opening is lower than a bottom surface of the second fin 230.
The first isolation layer 220 enables electrical isolation between the second fin 230 and the substrate 202. After the second fin 230 is formed, a portion of the first fin 201 is removed to form the substrate 202 and the remaining first fins 201, or all of the first fins 201 are removed to form the substrate 202. The top surface of the substrate is lower than the bottom surface of the second fin 230, and the sidewalls of the second fin 230 are not in contact with the substrate. The substrate is not in contact with the second fin portion 230, and carriers in the second fin portion 230 are not easy to diffuse into the substrate, so that leakage current of the formed semiconductor structure can be reduced.
In this embodiment, after removing the mask layer 213 (as shown in fig. 10), a part or all of the first fin 201 is removed.
In this embodiment, when removing a portion of the first fin portion 201, the substrate includes a base and the remaining first fin portion 201 on the base; when all of the first fins 201 are removed, the substrate includes a base.
In this embodiment, a portion of the first fin 201 is removed, such that the top surface of the first fin 201 is lower than the bottom surface of the second fin 230. In other embodiments, all of the first fins may also be removed.
The step of removing part or all of the first fin 201 includes: and etching the first fin portion 201 by using the protection layer 231 as a mask.
In the process of etching the first fin portion 201, the protective layer 231 may protect the second fin portion 230, and reduce loss of the second fin portion 230, thereby increasing performance of the formed semiconductor structure.
Specifically, in the present embodiment, the process of removing part or all of the first fin portion 201 includes a dry etching process. In other embodiments, the process of removing part or all of the first fin portion includes a wet etching process.
The dimension of the removed first fin 201 in a direction perpendicular to the surface of the substrate 202 is the height of the removed first fin 201.
If the height of the removed first fin portion 201 is too small, the distance between the bottom surface of the opening and the top surface of the substrate is too small, which is easy to increase the leakage current between the substrate and the second fin portion 230; the process difficulty may be increased if the removed first fin 201 is too high. Specifically, in the present embodiment, the height of the removed first fin portion 201 is 10nm to 30 nm.
The process parameters for removing at least a portion of the first fin 201 include: the etching gas includes: CH (CH)4And CHF3Wherein, CH is4The flow rate of (1) is 8sccm to 500sccm, CHF3The flow rate of the etching solution is 30-200 sccm, the radio frequency power is 100-1300W, the bias voltage is 80-500V, the etching time is 4-500 s, and the gas pressure is 10-2000 mtorr.
Referring to fig. 13, a second isolation layer 240 is in the opening, and a top surface of the second isolation layer 240 is lower than a top surface of the second fin 230.
The second isolation layer 240 is used to achieve electrical isolation between a subsequently formed gate structure and a substrate.
In this embodiment, the top surface of the second isolation layer 240 is higher than the bottom surface of the second fin 230, so that the second isolation layer 240 can also realize isolation between adjacent second fins 230, and reduce leakage between adjacent second fins 230.
In this embodiment, the material of the second isolation layer 240 is silicon oxide. In other embodiments, the material of the second isolation layer may also be a low-k dielectric material.
The step of forming the second isolation layer 240 includes: forming a second initial isolation layer on the second fin 230, the second initial isolation layer having a surface higher than the top surface of the second fin 230; and etching the second initial isolation layer to form a second isolation layer 240, wherein the top surface of the second isolation layer 240 is lower than the top surface of the second fin 230.
In this embodiment, the process of forming the second initial isolation layer includes a fluid chemical vapor deposition process. The fluid chemical vapor deposition process has good gap filling capacity, and the formed second initial isolation layer has good isolation performance. In other embodiments, the process of forming the second initial isolation layer comprises an atomic layer deposition process.
And the process for etching the second initial isolation layer comprises a dry etching process or a wet etching process.
In the process of etching the second initial isolation layer, the protection layer 231 may protect the second fin portion 230, and reduce damage to the second fin portion 230.
Referring to fig. 14, after the opening is formed, the protection layer 231 is removed (as shown in fig. 13).
In this embodiment, the process of removing the protection layer 231 includes a plasma dry etching process.
The process parameters for removing the protection layer 231 include: the etching gas comprises oxygen, the flow rate of the oxygen is 4.5 sccm-5.5 sccm, and the gas pressure is 0.08 Pa-0.09 Pa.
In this embodiment, after the second isolation layer 240 is formed, the protection layer 231 is removed.
Referring to fig. 15, after forming the second isolation layer 240, a gate structure 250 is formed across the second fin 230, wherein the gate structure 250 covers a portion of the sidewalls and the top surface of the second fin 230.
The gate structure 250 includes: and a gate dielectric layer crossing the second fin 230, wherein the gate dielectric layer covers part of the sidewall and the top surface of the second fin 230.
In this embodiment, the gate dielectric layer is made of silicon oxide. In other embodiments, the material of the gate dielectric layer may also be a high-k dielectric material.
In this embodiment, the gate is made of polysilicon. In other embodiments, the material of the gate may also be metal.
In the present embodiment, in the working process of the formed semiconductor structure, a channel is formed in the second fin 230 below the gate structure 250. Because the first isolation layer 220 is arranged between the second fin portion 230 and the substrate, the first isolation layer 220 can realize electrical isolation between the second fin portion 230 and the substrate, so that diffusion of carriers in a channel into the substrate can be reduced, and further, leakage current of a formed semiconductor structure can be reduced.
In this embodiment, the semiconductor structure is a MOS transistor. In other embodiments, the formed semiconductor structure may also be a diode, a transistor, or a resistor. When the formed semiconductor structure is a diode, a triode or a resistor, the forming method does not comprise the step of forming the grid structure.
The forming method further includes: source and drain doped layers are formed in the second fin portions 230 on both sides of the gate structure 250.
Due to the first isolation layer 220 arranged between the second fin portion 230 and the substrate, the first isolation layer 220 can realize electrical isolation between the second fin portion 230 and the substrate, so that diffusion of carriers in the source-drain doping layer into the substrate can be reduced, and junction leakage current of the formed semiconductor structure can be further reduced.
With continued reference to fig. 15, an embodiment of the present invention further provides a semiconductor structure formed by the forming method of the previous embodiment, including: a substrate 202; a first isolation layer 220 on the substrate 202; a second fin 230 on the first isolation layer 220.
In this embodiment, the semiconductor structure further includes: a first fin portion 201 on the substrate 202; a second isolation layer 240 on the first fin 201; a gate structure 250 spanning the second fin 230, the gate structure 250 covering a portion of the sidewalls and a top surface of the second fin 230; and source and drain doped layers located in the second fin portions 230 on two sides of the gate structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate having a plurality of discrete support structures thereon, the support structures comprising: the first fin part is positioned on the surface of the substrate;
forming a first isolation layer on the substrate, wherein the first isolation layer covers the side wall of the first fin part, and the surface of the first isolation layer is lower than the top surface of the first fin part;
forming a second fin part on the surface of the side wall of the first fin part exposed by the first isolation layer, wherein the second fin part is positioned on the first isolation layer;
after the second fin portion is formed, removing part or all of the first fin portion to form an opening, wherein the bottom surface of the opening is lower than the bottom surface of the second fin portion.
2. The method of forming a semiconductor structure of claim 1, wherein the support structure further comprises: a mask layer located on the first fin portion;
after forming the first isolation layer and before removing part or all of the first fin portion, the forming method further includes: and removing the mask layer.
3. The method of forming a semiconductor structure of claim 2, wherein forming the substrate and support structure comprises: providing an initial substrate; forming a patterned mask layer on the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form a substrate and a first fin part positioned on the substrate.
4. The method of forming a semiconductor structure of claim 3, wherein the step of forming the mask layer comprises: forming an initial mask layer on the initial substrate; forming a graphical pattern layer on the initial mask layer, and etching the initial mask layer and the initial substrate by taking the graphical pattern layer as a mask to form a substrate, a first fin part positioned on the substrate and a mask layer positioned on the first fin part;
the step of forming the graphic layer includes: forming a plurality of discrete core layers on the initial mask layer; forming a pattern layer on the surface of the side wall of the core layer; after the patterned layer is formed, the core layer is removed.
5. The method of claim 2, wherein the mask layer has a thickness of 10nm to 60 nm; the height of the first fin portion is 10 nm-70 nm.
6. The method of claim 1, wherein a material of the second fin is silicon, germanium, silicon germanium, or silicon carbide.
7. The method of claim 1, wherein the second fin portion is formed by a Chemical Vapor Deposition (CVD) epitaxy process or a solid phase epitaxy process.
8. The method of forming a semiconductor structure of claim 1, wherein after forming the second fin, further comprising: forming a protective layer on the second fin portion, wherein the material of the protective layer is different from that of the first fin portion, and the material of the protective layer is different from that of the second fin portion;
after removing part or all of the first fin portion, the method further includes: and removing the protective layer.
9. The method of claim 8, wherein a material of the protective layer is amorphous carbon, silicon nitride, or silicon oxide.
10. The method of forming a semiconductor structure of claim 8, wherein a top surface of the second fin is lower than a top surface of the support structure; the step of forming the protective layer includes: forming an initial protection layer on the second fin portion and the top of the support structure; and carrying out planarization treatment on the initial protection layer until the top surface of the support structure is exposed.
11. The method of forming a semiconductor structure of claim 10, wherein forming the initial protective layer comprises: a chemical vapor deposition process or an atomic layer deposition process; the process for removing the protective layer comprises a dry etching process.
12. The method of forming a semiconductor structure of claim 1, further comprising: and forming a second isolation layer in the opening, wherein the top surface of the second isolation layer is lower than that of the second fin part.
13. The method of forming a semiconductor structure of claim 12, wherein a material of the second isolation layer is silicon oxide or a low-k dielectric material.
14. The method of forming a semiconductor structure of claim 12, wherein the second spacer layer has a thickness of 2nm to 5 nm.
15. The method of forming a semiconductor structure of claim 12, further comprising, after forming the second isolation layer: and forming a grid electrode structure crossing the second fin part, wherein the grid electrode structure covers part of the top and part of the side wall surface of the second fin part.
16. The method of forming a semiconductor structure of claim 1, wherein the first spacer has a thickness of 10nm to 60 nm.
17. The method of claim 1, wherein a distance between a top surface of the second fin and a top surface of the first fin is between 2.7nm and 3.3nm before removing part or all of the first fin.
18. The method of claim 1, wherein the first spacer layer is formed of a silicon oxide or a low-k dielectric material.
19. The method of claim 1, wherein the removed first fin portion has a dimension in a direction perpendicular to the substrate surface of between 10nm and 30 nm.
20. A semiconductor structure formed by the method of forming a semiconductor structure of any one of claims 1 through 19, comprising:
a substrate;
a first isolation layer on the substrate;
a second fin portion on the first isolation layer.
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