CN106952816B - Method for forming fin type transistor - Google Patents

Method for forming fin type transistor Download PDF

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CN106952816B
CN106952816B CN201610006646.XA CN201610006646A CN106952816B CN 106952816 B CN106952816 B CN 106952816B CN 201610006646 A CN201610006646 A CN 201610006646A CN 106952816 B CN106952816 B CN 106952816B
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layer
gate
forming
fin
oxide layer
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CN106952816A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a fin transistor, comprising: providing a substrate, wherein the substrate comprises a core area and a peripheral area, and fin parts are respectively arranged on the surfaces of the substrate in the core area and the peripheral area; forming an isolation layer on the surface of the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part; forming a first gate oxide layer on the side wall and the top surface of the exposed fin part; forming a protective layer on the surface of the first gate oxide layer; forming a pseudo gate layer respectively crossing the fin parts of the core region and the peripheral region on the surface of the protective layer; forming a dielectric layer on the surface of the protective layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the peripheral region, and forming a second groove in the dielectric layer of the core region; removing the protective layer and the first gate oxide layer at the bottom of the second trench to expose partial side wall and top surface of the fin part in the core region; and forming a second gate oxide layer on the exposed side wall of the fin part at the bottom of the second groove and the surface of the top part. The leakage current of the formed fin type transistor is controlled, and the reliability is improved.

Description

Method for forming fin type transistor
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin type transistor.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. The structure of the fin field effect transistor comprises: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as the density and size of semiconductor devices increase, the difficulty of the fin field effect transistor fabrication process increases, and the performance and reliability of the formed fin field effect transistor deteriorate.
Disclosure of Invention
The invention aims to provide a method for forming a fin type transistor, wherein the leakage current of the formed fin type transistor is controlled, the driving current is improved, the power consumption is reduced, and the stability is improved.
To solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, wherein the substrate comprises a core area and a peripheral area, and fin parts are respectively arranged on the surfaces of the substrate in the core area and the peripheral area; forming an isolation layer on the surface of the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part; forming a first gate oxide layer on the side wall and the top surface of the exposed fin part; forming a protective layer on the surface of the first gate oxide layer; forming a pseudo gate layer on the surface of the protective layer and respectively crossing the fin parts of the core region and the peripheral region, wherein the pseudo gate layer covers partial side walls and the tops of the fin parts; forming a dielectric layer on the surface of the protective layer, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the peripheral area, and forming a second groove in the dielectric layer of the core area; removing the protective layer and the first gate oxide layer at the bottom of the second trench to expose partial side wall and top surface of the fin part in the core region; forming a second gate oxide layer on the side wall of the fin part exposed at the bottom of the second groove and the surface of the top part; forming a first grid structure which is filled in the first groove on the surface of the protection layer; and forming a second grid structure filled in the second groove on the surface of the second grid oxide layer.
Optionally, the protective layer comprises a nitrogen-containing layer.
Optionally, the material of the protective layer includes silicon nitride or silicon oxynitride.
Optionally, the forming process of the protective layer is an atomic layer deposition process; the protective layer is also formed on the surface of the isolation layer.
Optionally, the protective layer further includes a silicon oxide layer located on the surface of the nitrogen-containing layer.
Optionally, after removing the protective layer and the first gate oxide layer at the bottom of the second trench, the silicon oxide layer in the first trench is removed.
Optionally, the step of removing the protective layer and the first gate oxide layer at the bottom of the second trench includes: forming a first graphical layer in the surface of the dielectric layer and the first groove; etching the protective layer and the first gate oxide layer in the second groove by taking the first patterning layer as a mask until part of the side wall and the top surface of the fin part in the core region are exposed; after the protective layer and the first gate oxide layer are etched, removing the first patterning layer; after removing the first patterned layer, the silicon oxide layer in the first trench is removed.
Optionally, the process for removing the dummy gate layer is one or two of a wet etching process and a dry etching process.
Optionally, the dry etching process is an isotropic dry etching process.
Optionally, the dry etching process is a plasma dry etching process.
Optionally, the forming process of the first gate oxide layer is an in-situ steam generation process.
Optionally, the forming process of the second gate oxide layer is a thermal oxidation process or a wet oxidation process.
Optionally, after removing the protective layer and the first gate oxide layer at the bottom of the second trench and before forming the second gate oxide layer, the inner wall surfaces of the first trench and the second trench are pre-cleaned.
Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first trench is filled with the first gate layer; the second gate structure comprises a second gate dielectric layer and a second gate layer positioned on the second gate dielectric layer, and the second trench is filled with the second gate layer.
Optionally, the forming steps of the first gate structure and the second gate structure include: forming a gate dielectric film on the surface of the dielectric layer, the surface of the inner wall of the first groove and the surface of the inner wall of the second groove; after forming the gate dielectric film, forming a gate film which is filled in the first groove and the second groove; and flattening the gate film and the gate dielectric film until the surface of the dielectric layer is exposed, forming a first gate dielectric layer and a first gate layer in the first groove, and forming a second gate dielectric layer and a second gate layer in the second groove.
Optionally, the top surface of the fin portion further has a mask layer.
Optionally, the forming steps of the substrate and the fin portion include: providing a semiconductor substrate; forming a mask layer on part of the surface of the semiconductor substrate, wherein the mask layer covers the corresponding position and shape of the fin part to be formed; and etching the semiconductor substrate by taking the mask layer as a mask to form the substrate and the fin part.
Optionally, the forming step of the isolation layer includes: forming isolation films on the surfaces of the substrate and the fin part; planarizing the isolation film; and after the isolation film is planarized, etching back the isolation film until part of the fin side wall is exposed.
Optionally, the mask layer is removed while or after the isolation film is etched back.
Optionally, before forming the isolation layer, forming a liner oxide layer on the surface of the substrate and the surface of the fin portion; after the isolation layer is formed, the exposed pad oxide layer is removed.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method, after the first gate oxide layer is formed on the side wall and the top surface of the fin part, the protective layer is formed on the surface of the first gate oxide layer, and the pseudo gate layer is formed on the surface of the protective layer. When a dielectric layer is formed subsequently and the pseudo gate layer is removed, the protective layer can be used for protecting the first gate oxide layer from being damaged and preventing the first gate oxide layer from generating a time-dependent breakdown effect, so that the inhibition capability of the formed fin type transistor on a short channel effect is improved, the driving current is improved, the power consumption of the transistor is reduced, and the influence of an unstable bias temperature effect is inhibited. In addition, the protective layer is high in density, and can prevent the damage of an etching process to the fin part when the pseudo gate layer is removed, so that the quality of a channel region of the fin type transistor is improved, the leakage current is reduced, and the performance and the reliability of the fin type transistor are improved.
Drawings
Fig. 1 to 4 are schematic cross-sectional views illustrating a fin field effect transistor formation process;
fig. 5 to 15 are schematic cross-sectional views illustrating a formation process of a fin transistor according to an embodiment of the invention.
Detailed Description
As described in the background, as the density and the size of semiconductor devices increase, the performance and the reliability of the formed fin field effect transistor deteriorate.
In order to further reduce the size of a device and improve the density of the device, a high-K metal Gate transistor is introduced on the basis of a fin field effect transistor, namely, a high-K dielectric material is used as a Gate dielectric layer, and a metal material is used as a Gate, moreover, in order to improve the combination state between the Gate dielectric layer of the high-K dielectric material and a fin part, a Gate oxide layer is required to be formed between the Gate dielectric layer of the high-K dielectric material and the fin part for bonding, the high-K metal Gate transistor is formed by adopting a Gate-last (Gate L ast) process, wherein in the Gate-last process, after a pseudo Gate layer of polycrystalline silicon is removed and a Gate groove is formed, a Gate dielectric layer of the high-K dielectric material is formed on the inner wall surface of the Gate groove.
However, for the finfet in the periphery region, since the gate oxide layer is formed before the dummy gate layer is formed, the process of removing the dummy gate layer may damage the gate oxide layer. With the smaller size of the fin field effect transistor, the damage of the gate oxide layer has more obvious influence on the performance of the device. The following description will be made with reference to the accompanying drawings.
Fig. 1 to 4 are schematic cross-sectional views illustrating a formation process of a finfet.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a core region 110 and a peripheral region 120, the surfaces of the substrate 100 in the core region 110 and the peripheral region 120 respectively have fins 101, an isolation layer 102 is formed on the surface of the substrate 100, the isolation layer 102 covers part of the sidewall surfaces of the fins 101, and the surface of the isolation layer 102 is lower than the top surface of the fins 101.
Referring to fig. 2, a first gate oxide layer 103 is formed on the exposed sidewall and top surface of the fin 101; forming a dummy gate layer 104 respectively crossing the fin 101 in the core region 110 and the peripheral region 120 on the surface of the first gate oxide layer 103, wherein the dummy gate layer 104 covers part of the sidewall and the top of the fin 101.
Referring to fig. 3, a dielectric layer 105 is formed on the surface of the first gate oxide layer 103, the dielectric layer 105 covers the sidewalls of the dummy gate layer 104, and the dielectric layer 105 exposes the top of the dummy gate layer 104.
Referring to fig. 4, the dummy gate layer 104 is removed, a first trench 121 is formed in the dielectric layer 105 in the peripheral region 120, and a second trench 111 is formed in the dielectric layer 105 in the core region 110.
The first gate oxide layer 103 is formed by an atomic layer deposition process, and is made of silicon oxide. The first gate oxide layer 103 is used to protect the sidewalls and the top surface of the fin 101 in the core region 110 and the peripheral region 120 when the dummy gate layer 104 is removed. Since the density of the silicon oxide formed by the atomic layer deposition process is low and defects are easily formed inside, the first gate oxide layer 103 is not suitable for being used as a gate oxide layer of the finfet in the core region 110, and the first gate oxide layer 103 in the core region 110 needs to be removed subsequently.
Secondly, since the finfet in the periphery region 120 has lower requirements for the density of the gate oxide layer and the number of internal defects, the first oxide layer 103 in the periphery region 120 can be retained as the gate oxide layer in the finfet formed in the periphery region 120. After removing the dummy gate layer 104, the first gate oxide layer 103 of the core region 110 needs to be removed, and a second gate oxide layer is formed on the exposed fin 101 and the bottom surface of the core region 110 by a thermal oxidation process.
However, although the first gate oxide layer 103 can protect the sidewalls and the top surface of the fin 101 in the core region 110 and the peripheral region 120 when the dummy gate layer 104 is removed, the etching process for removing the dummy gate layer 104 is also likely to damage the first gate oxide layer 103, and the damaged first gate oxide layer 103 is likely to not only cause Time Dependent Dielectric Breakdown (TDDB), short channel effect, driving current reduction, power consumption improvement, but also cause a transistor performance degradation due to Bias Temperature Instability (BTI).
In addition, the process of removing the dummy gate layer 104 can be a dry etching process or a wet etching process. Particularly, when the dummy gate layer 104 is removed by using a plasma dry etching process, not only the first gate oxide layer 103 is easily damaged, but also the inside of the fin portion 101 is easily damaged by the plasma with energy; when the width of the fin 101 is smaller, the damaged area of the fin 101 is larger, and the damage to the fin 101 has a larger influence on the formed fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, wherein the substrate comprises a core area and a peripheral area, and fin parts are respectively arranged on the surfaces of the substrate in the core area and the peripheral area; forming an isolation layer on the surface of the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part; forming a first gate oxide layer on the side wall and the top surface of the exposed fin part; forming a protective layer on the surface of the first gate oxide layer; forming a pseudo gate layer on the surface of the protective layer and respectively crossing the fin parts of the core region and the peripheral region, wherein the pseudo gate layer covers partial side walls and the tops of the fin parts; forming a dielectric layer on the surface of the protective layer, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the peripheral area, and forming a second groove in the dielectric layer of the core area; removing the protective layer and the first gate oxide layer at the bottom of the second trench to expose partial side wall and top surface of the fin part in the core region; forming a second gate oxide layer on the side wall of the fin part exposed at the bottom of the second groove and the surface of the top part; forming a first grid structure which is filled in the first groove on the surface of the protection layer; and forming a second grid structure filled in the second groove on the surface of the second grid oxide layer.
After forming the first gate oxide layer on the side wall and the top surface of the fin portion, forming a protective layer on the surface of the first gate oxide layer, and forming the pseudo gate layer on the surface of the protective layer. When a dielectric layer is formed subsequently and the pseudo gate layer is removed, the protective layer can be used for protecting the first gate oxide layer from being damaged and preventing the first gate oxide layer from generating a time-dependent breakdown effect, so that the inhibition capability of the formed fin type transistor on a short channel effect is improved, the driving current is improved, the power consumption of the transistor is reduced, and the influence of an unstable bias temperature effect is inhibited. In addition, the protective layer is high in density, and can prevent the damage of an etching process to the fin part when the pseudo gate layer is removed, so that the quality of a channel region of the fin type transistor is improved, the leakage current is reduced, and the performance and the reliability of the fin type transistor are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 15 are schematic cross-sectional views illustrating a formation process of a fin transistor according to an embodiment of the invention.
Referring to fig. 5, a substrate 200 is provided, where the substrate 200 includes a core region 220 and a peripheral region 210, and the surfaces of the substrate 200 in the core region 220 and the peripheral region 210 respectively have fins 201.
The core region 220 is used to form a core device and the peripheral region 210 is used to form a peripheral device, such as an input/output (I/O) device. The density of core devices in the core region 220 is greater than the density of peripheral devices in the peripheral region 210, and the feature size (CD) of the core devices is smaller than the feature size of the peripheral devices. The working current or working voltage of the core device is less than that of the peripheral device. In this embodiment, the surfaces of the substrate 200 in the core region 220 and the peripheral region 210 respectively have fins 201 for forming fin transistors in the core region 220 and the peripheral region 210 respectively.
In this embodiment, the top surface of the fin 201 further has a mask layer 202. The mask layer 202 serves as a mask for forming the fin portion 201 through etching, and the mask layer 202 can also be used for protecting the top surface of the fin portion 201 in a subsequent process.
In this embodiment, the steps of forming the substrate 200 and the fin 201 include: providing a semiconductor substrate; forming a mask layer 202 on a part of the surface of the semiconductor substrate, wherein the mask layer 202 covers the corresponding position and shape of the fin portion 200 to be formed; and etching the semiconductor substrate by taking the mask layer 202 as a mask to form the substrate 200 and the fin part 201.
The semiconductor base is a silicon substrate, a germanium substrate and a silicon-germanium substrate. In this embodiment, the semiconductor base is a single crystal silicon substrate, that is, the material of the fin 201 and the substrate 200 is single crystal silicon.
The forming step of the mask layer 202 includes: forming a mask material film on the surface of the semiconductor substrate; forming a second patterning layer on the surface of the mask material film; and etching the mask material film by taking the second patterning layer as a mask until the surface of the semiconductor substrate is exposed to form the mask layer 204.
In one embodiment, the second patterned layer is a patterned photoresist layer, and the second patterned layer is formed by a coating process and a photolithography process. In another embodiment, in order to reduce the feature size of the fins 201 and the distance between adjacent fins 201, the second patterning layer is formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
The process for etching the semiconductor substrate is an anisotropic dry etching process. The sidewalls of the fin 201 are perpendicular or inclined with respect to the surface of the substrate 200, and when the sidewalls of the fin 201 are inclined with respect to the surface of the substrate 200, the bottom dimension of the fin 201 is larger than the top dimension. In the present embodiment, the sidewalls of the fin 201 are inclined with respect to the surface of the substrate 200.
The substrate 200 and the fin portion 201 of the peripheral region 210 further have a first well region therein, and the substrate 200 and the fin portion 201 of the core region 220 further have a second well region therein. The first well region and the second well region are formed by adopting an ion implantation process; the first well region and the second well region can be formed before the semiconductor substrate is etched to form the fin portion 201; alternatively, the first well region and the second well region can be formed after the fin 201 is formed.
In another embodiment, the fin portion is formed by etching a semiconductor layer formed on the surface of the substrate; the semiconductor layer is formed on the surface of the substrate by adopting a selective epitaxial deposition process. The substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a group III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate, or the like. The semiconductor layer is made of silicon, germanium, silicon carbide or silicon germanium.
In this embodiment, before forming the isolation layer subsequently, a liner oxide layer 203 is further formed on the surfaces of the substrate 200 and the fin 201. The liner oxide layer 203 is formed by an In-Situ steam generation (ISSG) process. The parameters of the in-situ steam generation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 20 seconds-10 minutes. The liner oxide layer 203 formed by the in-situ steam generation process has good step coverage capability, so that the formed liner oxide layer 203 can tightly cover the sidewall surface of the fin portion 201, and the thickness of the formed liner oxide layer 203 is uniform.
By forming the pad oxide layer 203, damage to the surfaces of the substrate 200 and the fin portion 201 during a preceding etching process and an ion implantation process can be repaired. Moreover, the liner oxide layer 203 can also protect the surfaces of the fin 201 and the substrate 200 during subsequent processes.
Referring to fig. 6, an isolation layer 204 is formed on the surface of the substrate 200, wherein the isolation layer 204 covers a portion of the sidewall of the fin 201, and the surface of the isolation layer 204 is lower than the top surface of the fin 201.
The forming step of the isolation layer 204 includes: forming an isolation film on the surfaces of the substrate 200 and the fin portion 201; planarizing the isolation film; after the isolation film is planarized, the isolation film is etched back until a portion of the sidewalls of the fin 201 is exposed.
In this embodiment, the material of the isolation layer 204 is silicon oxide; the thickness of the isolation layer 204 is 1/4-1/2 of the height of the fin 201. The formation process of the isolation film is a Fluid Chemical Vapor Deposition (FCVD) process. In other embodiments, the isolation film can also be formed using other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
In this embodiment, the fluid chemical vapor deposition process comprises the steps of: forming a precursor dielectric film on the surfaces of the substrate 200, the fin portion 201 and the mask layer 202; and carrying out an annealing process to solidify the precursor dielectric film to form the isolating film.
The material of the precursor dielectric film is a silicon-containing flowable material; the flowable material can be a polymeric polymer containing one or more of Si-H bonds, Si-N bonds, and Si-O bonds. The forming process parameters of the precursor dielectric film comprise: the process temperature is 60 ℃ to 70 ℃ and 65 ℃ in the present example.
The annealing process in the fluid chemical vapor deposition process can be a wet annealing process or a dry annealing process; the above-mentionedThe parameters of the annealing process include: the temperature is less than or equal to 600 ℃, the annealing gas comprises H2、O2、N2And one or more of Ar and He, wherein the annealing time is 5 seconds to 1 minute. Wherein when the annealing gas comprises H2And O2Meanwhile, the annealing process is a wet annealing process.
The planarization process is a chemical mechanical polishing process (CMP); in the present embodiment, the chemical mechanical polishing process uses the mask layer 202 as a stop layer. The process for back etching the isolating film is an isotropic dry etching process, an anisotropic dry etching process or a wet etching process.
In this embodiment, the mask layer 202 is removed (as shown in fig. 5) while or after etching back the isolation film. After the isolation layer 204 is formed, the exposed liner oxide layer 203 is removed; since the exposed pad oxide layer 203 is damaged in the process of etching back the isolation film, the pad oxide layer 203 is not suitable for being used as a subsequent gate oxide layer, and therefore the pad oxide layer 203 needs to be removed.
Referring to fig. 7, a first gate oxide layer 211 is formed on the exposed sidewalls and top surface of the fin 201.
In this embodiment, the first gate oxide layer 211 is used to form a gate oxide layer in the fin-type transistor in the peripheral region 210, and is used to enhance the bonding strength between the fin 201 and a subsequently formed first gate dielectric layer in the peripheral region 210, where the first gate dielectric layer is made of a high-K dielectric material (the dielectric coefficient is greater than 3.9), and the first gate dielectric layer is used as a gate dielectric layer of the fin-type field effect transistor in the peripheral region 210.
The first gate oxide layer 211 is made of silicon oxide, and the forming process of the first gate oxide layer 211 is an in-situ steam generating process; the first gate oxide layer 211 has a thickness of 20 to 50 angstroms, in this embodiment, 30 angstroms. The parameters of the in-situ steam generation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 10 seconds-5 minutes.
In another embodiment, the forming process of the first gate oxide layer 211 is a chemical oxidation process; the steps of the chemical oxidation process include: and oxidizing the exposed side wall and the exposed top surface of the fin part 201 by adopting an aqueous solution into which ozone is introduced, and forming a first oxidation layer on the side wall and the top surface of the fin part 201. Wherein, in the water solution with the ozone, the concentration of the ozone in the water is 1 to 15 percent.
Referring to fig. 8, a protection layer is formed on the surface of the first gate oxide layer 211.
The protection layer is used for protecting the fin 201 and the first gate oxide layer 211 from being damaged when the dummy gate layer is removed subsequently. In the embodiment, the protection layer includes the nitrogen-containing layer 212, and the density and hardness of the nitrogen-containing layer 212 are higher, which is beneficial to protecting the first gate oxide layer 211 and the fin 201 in the subsequent process. Moreover, the nitrogen-containing layer 212 has a higher dielectric coefficient, which is beneficial to inhibiting the tunneling phenomenon of carriers between the fin portion 201 and the first gate dielectric layer formed subsequently, and reducing the leakage current.
In the present embodiment, the material of the nitrogen-containing layer 212 includes silicon nitride or silicon oxynitride; the formation process of the nitrogen-containing layer 212 is an atomic layer deposition process; the thickness of the nitrogen-containing layer 212 is 30 to 50 angstroms. The nitrogen-containing layer 212 formed by the atomic layer deposition process has good step coverage capability and can be tightly attached to the surfaces of the isolation layer 204 and the first gate oxide layer 211.
Firstly, since the first gate oxide layer 211 is used to form a gate oxide layer in the finfet of the peripheral region 210, the first gate oxide layer 211 of the peripheral region 210 needs to be exposed in a subsequent process, and the formed protective layer can reduce damage to the first gate oxide layer 211 in an etching process for removing a dummy gate layer in a subsequent process.
Secondly, when the subsequent etching process for removing the dummy gate layer includes a plasma dry etching process, the plasma etching process is easy to damage the inside of the fin portion 201, and the protective layer has high density and hardness, so that the protective layer can be used for blocking plasma, the fin portion 201 is prevented from being damaged, leakage current in the fin transistor formed in the peripheral region 210 can be reduced, and the performance of the fin transistor is improved.
In this embodiment, the protection layer further includes a silicon oxide layer 213 on the surface of the nitrogen-containing layer 212. The nitrogen-containing layer 212 is required to remain in the fin transistor, and the silicon oxide layer can protect the surface of the nitrogen-containing layer 212 from being damaged when the first gate oxide layer 211 of the core region 220 is removed, so that the stability of the fin transistor in the peripheral region 210 is ensured.
Referring to fig. 9, a dummy gate layer 205 is formed on the surface of the protection layer and respectively crosses over the fin 201 in the core region 220 and the peripheral region 210, and the dummy gate layer 205 covers a portion of the sidewall and the top of the fin 201.
The material of the dummy gate layer 205 is polysilicon. The forming step of the dummy gate layer 205 includes: forming a pseudo gate electrode film on the surface of the protective layer; flattening the pseudo gate electrode film; after the planarization process, forming a third patterning layer on the surface of the dummy gate film, wherein the third patterning layer covers the position and the shape of the dummy gate layer 205 to be formed; and etching the pseudo gate film by taking the third patterning layer as a mask until the surface of the protective layer is exposed to form a pseudo gate layer.
In this embodiment, forming a sidewall on a sidewall surface of the dummy gate layer 205; and forming a source region and a drain region in the dummy gate layer 205 and the fin part 201 on two sides of the side wall.
The material of the side wall comprises one or more of silicon oxide, silicon nitride and silicon oxynitride. The forming step of the side wall comprises the following steps: forming a side wall film on the surfaces of the protective layer and the dummy gate layer 205 by adopting a deposition process; and etching the side wall film back until the position of the protective layer on the surface of the fin part 201 is exposed to form the side wall.
In one embodiment, the source and drain regions are formed by an ion implantation process. In another embodiment, the forming of the source and drain regions further comprises: forming grooves in the pseudo gate layer 205 and the fin parts on two sides of the side wall; forming a stress layer in the groove by adopting a selective epitaxial deposition process; and doping ions in the stress layer to form a source region and a drain region. The doping process is one or the combination of an ion implantation process and an in-situ doping process. When the formed fin type transistor is a PMOS transistor, the stress layer is made of silicon germanium, ions doped in the stress layer are P-type ions, and the stress layer is a sigma-type stress layer. When the formed fin type transistor is an NMOS transistor, the stress layer is made of silicon carbide, and ions doped in the stress layer are N-type ions.
Referring to fig. 10, a dielectric layer 206 is formed on the surface of the protection layer, the dielectric layer 206 covers the sidewall of the dummy gate layer 205, and the dielectric layer 206 exposes the top of the dummy gate layer 205.
The forming step of the dielectric layer 206 includes: forming a dielectric film on the surfaces of the protective layer and the dummy gate layer 205; and flattening the dielectric film until the top surface of the dummy gate layer 205 is exposed to form the dielectric layer 206.
The forming step of the dielectric film is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The dielectric layer 206 is made of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material (having a dielectric constant of greater than or equal to 2.5 and less than 3.9, such as porous silicon oxide or porous silicon nitride), or an ultra-low-k dielectric material (having a dielectric constant of less than 2.5, such as porous SiCOH).
In this embodiment, the dielectric layer 206 is made of silicon oxide; the forming process of the dielectric film is one or more of a Fluid Chemical Vapor Deposition (FCVD) process, a High Density Plasma Deposition (HDP) process and a Plasma enhanced Deposition process.
Referring to fig. 11, the dummy gate layer 205 is removed, a first trench 214 is formed in the dielectric layer 206 of the peripheral region 210, and a second trench 221 is formed in the dielectric layer 206 of the core region 220.
The process for removing the dummy gate layer 205 is one or a combination of a dry etching process and a wet etching process; wherein the dry etching process is an isotropic dry etching process.
In the present embodimentThe dummy gate layer 205 is made of polysilicon, and the process for removing the dummy gate layer 205 is a plasma dry etching process; the parameters of the plasma dry etching process comprise: the gas comprises fluorocarbon gas, HBr and Cl2And a carrier gas, the fluorocarbon gas including CF4、CHF3、CH2F2、CH3And F, the carrier gas is inert gas such as He, the gas flow is 50-400 sccm, and the pressure is 3-8 mTorr.
In the plasma dry etching process, the plasma with energy easily damages the inside of the fin portion 201, and the density and hardness of the protective layer are high, so that the bombardment of the plasma can be blocked in the process of diffusing the dummy gate layer 205, and the damage of the plasma in the fin portion 201 can be avoided.
In another embodiment, the process of removing the dummy gate layer is a wet etching process, and an etching solution of the wet etching process is a hydrofluoric acid solution.
Referring to fig. 12, the passivation layer and the first gate oxide layer 211 at the bottom of the second trench 221 are removed to expose a portion of the sidewalls and the top surface of the fin 201 in the core region 220.
The step of removing the protection layer and the first gate oxide layer 211 at the bottom of the second trench 221 includes: forming a first patterned layer 222 on the surface of the dielectric layer 206 and in the first trench 214; the passivation layer and the first gate oxide layer 211 in the second trench 221 are etched using the first patterned layer 222 as a mask until a portion of the sidewalls and the top surface of the fin 201 in the core region 220 are exposed.
The first patterned layer 222 is a patterned photoresist layer, and the first patterned layer 222 fills the first trench 214. In this embodiment, the first patterned layer 222 is also located on the surface of the dielectric layer 206. The process for etching the protective layer and the first gate oxide layer 211 is a wet etching process or an isotropic dry etching process.
In this embodiment, the protection layer includes a nitrogen-containing layer 212 and a silicon oxide layer 213, and the process of removing the nitrogen-containing layer 212 and the silicon oxide layer 213 is a wet etching process; the etching solution for removing the nitrogen-containing layer 212 is phosphoric acid solution, and the etching solution for removing the silicon oxide layer 213 is hydrofluoric acid solution.
In this embodiment, the isotropic dry etching process for etching the first gate oxide layer 211 can be a SICONI process. The SICONI process has uniform etching rate in different directions, can uniformly remove the first gate oxide layers 211 on the side walls and the top surfaces of the fin portions 201, and has small damage to the side walls and the top surfaces of the fin portions 201.
The parameters of the SICONI process comprise: the power is 10W-100W, the frequency is less than 100kHz, the etching temperature is 40 ℃ to 80 ℃, the pressure is 0.5 Torr to 50 Torr, and the etching gas comprises NH3、NF3He, wherein, NH3The flow rate of (1) is 0sccm to 500sccm, NF3The flow rate of (A) is 20sccm to 200sccm, the flow rate of He is 400sccm to 1200sccm, and NF3And NH3The flow ratio of (A) to (B) is 1: 20-5: 1.
Referring to fig. 13, after the protective layer and the first gate oxide layer 211 are etched, the first patterning layer 222 is removed (as shown in fig. 12).
In this embodiment, the first patterned layer 222 is a patterned photoresist layer, and the process of removing the first patterned layer 222 is a wet stripping process or an ashing process. During the process of removing the first patterned layer 222, the silicon oxide layer 213 is used to protect the protection layer 212, so as to prevent the protection layer 212 from being damaged. After removing the first patterned layer 222, the silicon oxide layer 213 within the first trench 214 is removed. The process for removing the silicon oxide layer 213 is a wet etching process or an isotropic dry etching process.
In this embodiment, after removing the protection layer and the first gate oxide layer 211 at the bottom of the second trench 221 and before forming the second gate oxide layer, the inner wall surfaces of the first trench 214 and the second trench 221 are pre-cleaned to remove impurities attached to the inner wall surfaces of the first trench 214 and the second trench 221.
Referring to fig. 14, a second gate oxide layer 223 is formed on the sidewalls and the top surface of the fin 201 exposed at the bottom of the second trench 221.
The second gate oxide layer 223 is used as a gate oxide layer of a fin transistor formed in the core region 210. The material of the second gate oxide layer 223 is silicon oxide; the second gate oxide layer 223 is formed by a thermal oxidation process or a wet oxidation process.
The thickness of the second gate oxide layer 223 is 3 to 10 nm. In this embodiment, the forming process of the second gate oxide layer 223 is a chemical oxidation process; the steps of the chemical oxidation process include: and oxidizing the exposed side wall and the exposed top surface of the fin portion 201 by adopting an aqueous solution into which ozone is introduced, and forming a second gate oxide layer 223 on the side wall and the top surface of the fin portion 201. Wherein, in the water solution with the ozone, the concentration of the ozone in the water is 1 to 15 percent.
Referring to fig. 15, a first gate structure is formed on the surface of the protection layer to fill the first trench 214 (shown in fig. 14); a second gate structure filling the second trench 221 (as shown in fig. 14) is formed on the surface of the second gate oxide layer 223.
The first gate structure comprises a first gate dielectric layer 215 and a first gate layer 216 located on the first gate dielectric layer 215, wherein the first gate layer 216 fills the first trench 214; the second gate structure includes a second gate dielectric layer 224 and a second gate layer 225 located on the second gate dielectric layer 224, wherein the second gate layer 225 fills the second trench 221.
The forming steps of the first gate structure and the second gate structure comprise: forming a gate dielectric film on the surface of the dielectric layer 206, the surface of the inner wall of the first trench 214 and the surface of the inner wall of the second trench 221; after forming the gate dielectric film, forming a gate film filling the first trench 214 and the second trench 221; and flattening the gate electrode film and the gate dielectric film until the surface of the dielectric layer 206 is exposed, forming a first gate dielectric layer 215 and a first gate layer 216 in the first trench 214, and forming a second gate dielectric layer 224 and a second gate layer 225 in the second trench 221.
The first gate dielectric layer 215 and the second gate dielectric layer 224 are made of high-k dielectric materials (the dielectric coefficient is greater than 3.9); the high-k dielectric material comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide. The forming process of the gate dielectric film is an atomic layer deposition process.
The material of the first gate layer 216 and the second gate layer 225 comprises copper, tungsten, aluminum or silver; the forming process of the gate electrode film comprises a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, an electroplating process or a chemical plating process. And the process for flattening the gate electrode film and the gate dielectric film is a Chemical Mechanical Polishing (CMP) process.
In one embodiment, before forming the gate electrode film, forming a work function film on the surface of the gate dielectric film; forming a gate film on the surface of the work function film; after planarizing the gate film, the work function film is planarized until the surface of the dielectric layer 206 is exposed, forming a work function layer. The material of the work function layer formed in the first trench 214 and the second trench 221 can be the same or different.
In this embodiment, after forming the gate dielectric film and before forming the gate film, an annealing process is further performed. The annealing process is used for eliminating defects or impurities in the fin 201 and in the surface of the fin, and defects or impurities in the first gate oxide layer 211, the second gate oxide layer 223, the first gate dielectric layer 215 and the second gate dielectric layer 224. Also, the annealing process can also be used to activate impurity ions located in the source and drain regions within the fin 201.
In summary, in the embodiment, after the first gate oxide layer is formed on the sidewall and the top surface of the fin, the protection layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the surface of the protection layer. When a dielectric layer is formed subsequently and the pseudo gate layer is removed, the protective layer can be used for protecting the first gate oxide layer from being damaged and preventing the first gate oxide layer from generating a time-dependent breakdown effect, so that the inhibition capability of the formed fin type transistor on a short channel effect is improved, the driving current is improved, the power consumption of the transistor is reduced, and the influence of an unstable bias temperature effect is inhibited. In addition, the protective layer is high in density, and can prevent the damage of an etching process to the fin part when the pseudo gate layer is removed, so that the quality of a channel region of the fin type transistor is improved, the leakage current is reduced, and the performance and the reliability of the fin type transistor are improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A method for forming a fin transistor includes:
providing a substrate, wherein the substrate comprises a core area and a peripheral area, and fin parts are respectively arranged on the surfaces of the substrate in the core area and the peripheral area;
forming an isolation layer on the surface of the substrate, wherein the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part;
forming a first gate oxide layer on the side wall and the top surface of the fin part exposed from the core region and the peripheral region;
forming a protective layer on the surfaces of the first gate oxide layers of the core region and the peripheral region, wherein the protective layer comprises a nitrogen-containing layer and a silicon oxide layer positioned on the surface of the nitrogen-containing layer;
forming a pseudo gate layer on the surface of the protective layer and respectively crossing the fin parts of the core region and the peripheral region, wherein the pseudo gate layer covers partial side walls and the tops of the fin parts;
forming a dielectric layer on the surface of the protective layer, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer;
removing the pseudo gate layer, forming a first groove in the dielectric layer of the peripheral area, and forming a second groove in the dielectric layer of the core area;
removing the protective layer and the first gate oxide layer at the bottom of the second trench to expose partial side wall and top surface of the fin part in the core region;
after the protective layer and the first gate oxide layer at the bottom of the second trench are removed, removing the silicon oxide layer in the first trench;
forming a second gate oxide layer on the side wall of the fin part exposed at the bottom of the second groove and the surface of the top part;
forming a first grid structure which is filled in the first groove on the surface of the nitrogen-containing layer;
and forming a second grid structure filled in the second groove on the surface of the second grid oxide layer.
2. The method of claim 1, wherein the material of the protective layer comprises silicon nitride or silicon oxynitride.
3. The method of claim 1, wherein the formation process of the protective layer is an atomic layer deposition process; the protective layer is also formed on the surface of the isolation layer.
4. The method of claim 1, wherein removing the protective layer and the first gate oxide layer at the bottom of the second trench comprises: forming a first graphical layer in the surface of the dielectric layer and the first groove; etching the protective layer and the first gate oxide layer in the second groove by taking the first patterning layer as a mask until part of the side wall and the top surface of the fin part in the core region are exposed; after the protective layer and the first gate oxide layer are etched, removing the first patterning layer; after removing the first patterned layer, the silicon oxide layer in the first trench is removed.
5. The method of claim 1, wherein the dummy gate layer is removed by one or a combination of a wet etching process and a dry etching process.
6. The method of claim 5, wherein the dry etching process is an isotropic dry etching process.
7. The method of claim 5, wherein the dry etching process is a plasma dry etching process.
8. The method of claim 1, wherein the first gate oxide layer formation process is an in-situ steam generation process.
9. The method of claim 1, wherein the second gate oxide layer is formed by a thermal oxidation process or a wet oxidation process.
10. The method of claim 1, wherein after removing the protective layer and the first gate oxide layer at the bottom of the second trench and before forming the second gate oxide layer, a pre-clean is performed on inner wall surfaces of the first trench and the second trench.
11. The method of claim 1, wherein the first gate structure comprises a first gate dielectric layer and a first gate layer over the first gate dielectric layer, the first gate layer filling the first trench; the second gate structure comprises a second gate dielectric layer and a second gate layer positioned on the second gate dielectric layer, and the second trench is filled with the second gate layer.
12. The method of forming the fin-type transistor of claim 11, wherein the forming of the first and second gate structures comprises: forming a gate dielectric film on the surface of the dielectric layer, the surface of the inner wall of the first groove and the surface of the inner wall of the second groove; after forming the gate dielectric film, forming a gate film which is filled in the first groove and the second groove; and flattening the gate film and the gate dielectric film until the surface of the dielectric layer is exposed, forming a first gate dielectric layer and a first gate layer in the first groove, and forming a second gate dielectric layer and a second gate layer in the second groove.
13. The method of claim 1, wherein a mask layer is further formed on a top surface of the fin.
14. The method of forming the fin-type transistor of claim 13, wherein the forming the substrate and the fin comprises: providing a semiconductor substrate; forming a mask layer on part of the surface of the semiconductor substrate, wherein the mask layer covers the corresponding position and shape of the fin part to be formed; and etching the semiconductor substrate by taking the mask layer as a mask to form the substrate and the fin part.
15. The method of forming the fin-type transistor of claim 13, wherein the forming the isolation layer comprises: forming isolation films on the surfaces of the substrate and the fin part; planarizing the isolation film; and after the isolation film is planarized, etching back the isolation film until part of the fin side wall is exposed.
16. The method of forming the fin-type transistor of claim 15, wherein the mask layer is removed while or after etching back the isolation film.
17. The method of claim 1, wherein a liner oxide layer is formed on the substrate and fin surface prior to forming the isolation layer; after the isolation layer is formed, the exposed pad oxide layer is removed.
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