CN107481933B - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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CN107481933B
CN107481933B CN201610405073.8A CN201610405073A CN107481933B CN 107481933 B CN107481933 B CN 107481933B CN 201610405073 A CN201610405073 A CN 201610405073A CN 107481933 B CN107481933 B CN 107481933B
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isolation layer
fin
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CN107481933A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and method of making the same, the method comprising: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming a first isolation layer lower than the top of the fin parts on the substrate between the fin parts; forming a barrier layer on the side wall of the fin part protruding out of the first isolation layer; after the barrier layer is formed, forming a second isolation layer on the first isolation layer, wherein the first isolation layer and the second isolation layer are used for forming an isolation structure; forming a grid structure which crosses the fin part and covers part of the top and the side wall of the fin part; forming a mask gate structure on the second isolation layer; and removing part of the thickness fin parts on two sides of the grid electrode structure, and forming a groove in the fin parts, wherein the etching rate of the etching process to the fin parts is greater than that to the barrier layer. According to the invention, the barrier layer is formed between the second isolation layer and the fin part, and the over-etching of the isolation structure in the edge region of the fin part by an etching process can be avoided when the groove is formed, so that the problem of groove shape change caused by the loss of the isolation structure can be avoided.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET fets has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip, increasing the switching speed of the MOSFET field effect transistor and the like.
However, as the length of the channel of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effects, is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFET transistors to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the grid electrode can control the ultrathin body (fin part) at least from two sides, the control capability of the grid electrode on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
In the existing semiconductor device manufacturing process, the mobility of a carrier is one of main factors influencing the performance of a transistor, and the effective improvement of the mobility of the carrier becomes one of the key points of the transistor device manufacturing process. Since the energy gap and carrier mobility of silicon materials can be changed by stress, it is becoming a more and more common means to improve the performance of MOS transistors by forming stress layers. Specifically, a stress layer capable of providing tensile stress is formed in the NMOS device to improve electron mobility, and a stress layer capable of providing compressive stress is formed in the PMOS device to improve hole mobility.
However, even with the introduction of stress layers in the FinFET fabrication process, the electrical performance of prior art semiconductor devices remains poor.
Disclosure of Invention
The invention provides a semiconductor structure and a manufacturing method thereof, which can optimize the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and discrete fin parts positioned on the substrate; forming a first isolation layer on the substrate between the fin parts, wherein the top of the first isolation layer is lower than that of the fin parts; forming a barrier layer on the side wall of the fin part protruding out of the first isolation layer; after the barrier layer is formed, forming a second isolation layer on the first isolation layer, wherein the top of the second isolation layer is flush with the top of the fin part, and the first isolation layer and the second isolation layer are used for forming an isolation structure; forming a grid electrode structure which crosses the fin part and covers the top of the fin part and the surface of the side wall; forming a mask gate structure on the second isolation layer; removing fin parts with partial thickness positioned at two sides of the grid electrode structure, and forming a groove in the fin parts, wherein the etching speed of the etching process to the fin parts is greater than that to the barrier layer; forming a stress layer in the groove; and forming a source drain doped region in the stress layer.
Optionally, the material of the barrier layer is different from the material of the second isolation layer.
Optionally, the barrier layer is made of amorphous silicon, amorphous carbon, silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, the thickness of the barrier layer is
Figure BDA0001013104730000021
To
Figure BDA0001013104730000022
Optionally, the process of forming the barrier layer is an atomic layer deposition process.
Optionally, the barrier layer is made of silicon nitride, and the process parameters of the atomic layer deposition process include: the precursor is introduced into the atomic layer deposition chamber and is a precursor containing silicon and nitrogen, the gas flow of the precursor is 500sccm to 5000sccm, the process temperature is 80 ℃ to 300 ℃, the pressure is 0.1 Torr to 20 Torr, and the deposition times are 5 times to 200 times.
Optionally, in the step of forming the blocking layer on the fin portion sidewall protruding from the first isolation layer, the blocking layer further covers the top of the first isolation layer and the top of the fin portion; and in the step of forming the second isolation layer on the first isolation layer, removing the barrier layer protruding out of the top of the fin part.
Optionally, the fin portion protruding from the first isolation layer has a height of
Figure BDA0001013104730000023
To
Figure BDA0001013104730000024
Optionally, after forming the groove and before forming the stress layer in the groove, the manufacturing method further includes: and carrying out a cleaning process on the groove.
Optionally, the cleaning process includes: cleaning the groove by using a SICONI etching process; or, cleaning the groove by adopting a wet etching process, wherein the etching solution adopted by the wet etching process is a hydrofluoric acid solution.
Optionally, the semiconductor structure is an NMOS structure, and a cross-sectional shape of the groove perpendicular to the substrate surface direction is a U shape; or, the semiconductor structure is a PMOS structure, and the cross section of the groove in the direction vertical to the surface of the substrate is Sigma-shaped.
Optionally, the first isolation layer and the second isolation layer are made of the same material.
Optionally, the first isolation layer is made of silicon oxide, silicon nitride or silicon oxynitride, and the second isolation layer is made of silicon oxide, silicon nitride or silicon oxynitride.
Accordingly, the present invention also provides a semiconductor structure comprising: the base comprises a substrate and a discrete fin part positioned on the substrate; the isolation structure is positioned on the substrate between the fin parts, the top of the isolation structure is flush with the top of the fin parts, and the isolation structure comprises a first isolation layer positioned on the substrate and a second isolation layer positioned on the first isolation layer; the barrier layer is positioned between the second isolation layer and the fin part; the grid electrode structure stretches across the fin part and covers the top of the fin part and the surface of the side wall; the mask gate structure is positioned on the second isolation layer; the stress layer is positioned in the fin parts at two sides of the grid structure; and the source and drain doped region is positioned in the stress layer.
Optionally, the material of the barrier layer is different from the material of the second isolation layer.
Optionally, the barrier layer is made of amorphous silicon, amorphous carbon, silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, the thickness of the barrier layer is
Figure BDA0001013104730000031
To
Figure BDA0001013104730000032
Optionally, the semiconductor structure is an NMOS structure, and a cross-sectional shape of the stress layer perpendicular to the substrate surface direction is a U shape; or, the semiconductor structure is a PMOS structure, and the cross section of the stress layer perpendicular to the substrate surface is Sigma-shaped.
Optionally, the first isolation layer and the second isolation layer are made of the same material.
Optionally, the first isolation layer is made of silicon oxide, silicon nitride or silicon oxynitride, and the second isolation layer is made of silicon oxide, silicon nitride or silicon oxynitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after a first isolation layer is formed, a barrier layer is formed on the side wall of the fin portion protruding out of the first isolation layer, and then a second isolation layer with the top being flush with the fin portion is formed on the first isolation layer to form an isolation structure, namely, the barrier layer is formed between the second isolation layer and the fin portion. And in the process of forming the groove in the fin part, the barrier layer can prevent the etching process for forming the groove from over-etching the isolation structure in the edge area of the fin part, so that the problem of groove appearance change caused by the loss of the isolation structure can be avoided, and the electrical performance of the semiconductor device is optimized.
In an alternative, after the groove is formed, before the stress layer is formed in the groove, the method further comprises the following steps: and carrying out a cleaning process on the groove. The barrier layer is used for preventing the isolation structure from being transversely over-etched by the cleaning process, so that the problem of groove shape change caused by the loss of the isolation structure can be solved.
In an alternative, the material of the barrier layer is a material that can be used as an isolation structure, and thus has better process compatibility.
The semiconductor structure provided by the invention comprises the barrier layer positioned between the second isolation layer and the fin part, wherein the barrier layer is used for protecting the isolation structure positioned in the edge area of the fin part and preventing the isolation structure in the area from being lost in the process of forming the stress layer, so that the problem of shape change of the stress layer caused by the loss of the isolation structure is avoided, and the electrical property of a semiconductor device is further optimized.
Drawings
FIGS. 1 and 2 are schematic structural diagrams corresponding to steps in a method of fabricating a semiconductor structure;
fig. 3 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for fabricating a semiconductor structure according to the present invention.
Detailed Description
As is known from the background art, the electrical properties of the semiconductor devices formed by the prior art need to be improved.
The reason is analyzed in conjunction with the manufacturing method of the semiconductor structure, and referring to fig. 1 and fig. 2, a structure diagram corresponding to each step of the manufacturing method of the semiconductor structure is shown, and the manufacturing method of the semiconductor structure comprises the following steps:
referring to fig. 1, a substrate 100 and discrete fins 110 on the substrate 100 are provided; forming an isolation structure 101 on the substrate 100 between the fins 110, wherein the top of the isolation structure 101 is flush with the top of the fins 110; forming a gate structure 111 which crosses the fin 110 and covers the top and the sidewall surface of part of the fin 110, and forming a mask gate structure 121 on the isolation structure 101; and forming a side wall 112 on the side wall of the gate structure 111, and forming a pseudo side wall 122 on the side wall of the mask gate structure 121.
Referring to fig. 2, the fin 110 on both sides of the gate structure 111 is etched, and a groove 130 is formed in the fin 110.
The subsequent process steps further comprise: performing a cleaning process on the groove 130; and forming a stress layer in the groove 130 and forming a source-drain doped region in the stress layer.
It should be noted that, in the process of forming the recess 130 (as shown in fig. 2), the etching process is prone to over-etch the isolation structure 101 located in the edge region (as shown in the region a in fig. 1) of the fin 110, so that the topography of the recess 130 is changed, and the more severe the over-etching is, the more significant the topography of the recess 130 is changed; in addition, when the groove 130 is cleaned, the cleaning process may further over-etch the isolation structure 101 in the region, thereby deteriorating the problem of the shape change of the groove 130.
In order to solve the above problems, a method of forming a mask gate structure 121 on the isolation structure 101 is mainly adopted at present, the pseudo-sidewall 122 is used as an etching mask, the isolation structure 101 can be protected in the process of forming the groove 130, the isolation structure 101 is prevented from being over-etched by the etching process, and therefore the appearance of the groove 130 is prevented from being changed due to the loss of the isolation structure 101.
However, at present, the pseudo sidewall 122 is difficult to completely cover the edge region of the fin 110, that is, in the process of forming the groove 130, the cleaning process still easily causes lateral over-etching on the isolation structure 101 in the edge region of the fin 110, so that the morphology of the groove 130 is changed, and the change of the morphology of the groove 130 deteriorates the stress effect of the stress layer formed subsequently, thereby causing the electrical performance of the semiconductor device to be degraded.
In order to solve the technical problem, the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and discrete fin parts positioned on the substrate; forming a first isolation layer on the substrate between the fin parts, wherein the top of the first isolation layer is lower than that of the fin parts; forming a barrier layer on the side wall of the fin part protruding out of the first isolation layer; after the barrier layer is formed, forming a second isolation layer on the first isolation layer, wherein the top of the second isolation layer is flush with the top of the fin part, and the first isolation layer and the second isolation layer are used for forming an isolation structure; forming a grid electrode structure which crosses the fin part and covers the top of the fin part and the surface of the side wall; forming a mask gate structure on the second isolation layer; removing fin parts with partial thickness positioned at two sides of the grid electrode structure, and forming a groove in the fin parts, wherein the etching speed of the etching process to the fin parts is greater than that to the barrier layer; forming a stress layer in the groove; and forming a source drain doped region in the stress layer.
After a first isolation layer is formed, a barrier layer is formed on the side wall of the fin portion protruding out of the first isolation layer, and then a second isolation layer with the top being flush with the fin portion is formed on the first isolation layer to form an isolation structure, namely, the barrier layer is formed between the second isolation layer and the fin portion. And in the process of forming the groove in the fin part, the barrier layer can prevent the etching process for forming the groove from over-etching the isolation structure in the edge area of the fin part, so that the problem of groove appearance change caused by the loss of the isolation structure can be avoided, and the electrical performance of the semiconductor device is optimized.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for fabricating a semiconductor structure according to the present invention.
Referring to fig. 3 and 4 in combination, fig. 4 is a schematic cross-sectional view taken along direction AA1 of fig. 3, wherein fig. 3 illustrates only first region i, providing substrate 200 and discrete fin 210 on substrate 200.
The substrate 200 provides a process platform for the subsequent formation of semiconductor devices.
The substrate 200 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of fin 210 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 200 is a silicon substrate, and the fin portion 210 is made of silicon.
In this embodiment, the process steps for forming the substrate 200 and the fin portion 210 include: providing an initial substrate; forming a patterned hard mask layer 300 on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer 300 as a mask, wherein the etched initial substrate is taken as the substrate 200, and the protrusion on the substrate 200 is taken as the fin part 210.
In this embodiment, after the formation of fin 210, the hard mask layer 300 on the top surface of fin 210 remains. The hard mask layer 300 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the hard mask layer 300 is used for defining a stop position of the planarization process and protecting the top of the fin 210.
In this embodiment, the substrate 200 includes a first region i and a second region ii. The density of the fin portions 210 in the first region i is greater than the density of the fin portions 210 in the second region ii. In another embodiment, the substrate may also comprise only the first region.
In this embodiment, the first region i and the second region ii are adjacent regions. In another embodiment, the first region and the second region may also be non-adjacent regions.
With reference to fig. 5, it should be noted that after the forming of the fin 210, the manufacturing method further includes: a liner oxide layer 201 is formed on the surface of the fin 210 for repairing the fin 210.
In this embodiment, the process of forming the pad oxide layer 201 is an oxidation process.
Since the fin 210 is formed by etching the initial substrate, the fin 210 typically has a convex corner and a surface defect. In the oxidation treatment process, because the convex edge part of fin portion 210 is bigger than the surface, and is easier to be oxidized, follow-up getting rid of after liner oxide layer 201, not only the defect layer on fin portion 210 surface is got rid of, and protruding edge part is also got rid of, thereby can make fin portion 210's surface is smooth, the crystal lattice quality is improved, avoids fin portion 210 apex angle point discharge problem, is favorable to improving fin field effect transistor's performance.
The oxidation treatment may employ an oxygen plasma oxidation process, or a mixed solution oxidation process of sulfuric acid and hydrogen peroxide. It should be noted that the oxidation process also oxidizes the surface of the substrate 200, so that the formed pad oxide layer 201 is also located on the surface of the substrate 200.
In this embodiment, the fin portion 210 is oxidized by using an ISSG (In-situ steam Generation) oxidation process to form the pad oxide layer 201, and since the fin portion 210 is made of silicon, the correspondingly formed pad oxide layer 201 is made of silicon oxide.
Referring to fig. 6 to 8 in combination, fig. 7 is a schematic cross-sectional view of fig. 6 along a direction BB1 (shown in fig. 3), wherein a first isolation layer 212 (shown in fig. 8) is formed on the substrate 200 between the fins 210, and a top of the first isolation layer 212 is lower than a top of the fins 210.
Referring collectively to fig. 6 and 7, an initial isolation layer 202 is formed on the substrate 200 between the fins 210.
The initial isolation layer 202 provides a process basis for subsequently forming an isolation structure of a semiconductor structure for isolating adjacent devices, and the material of the initial isolation layer 202 is an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the initial isolation layer 202 is silicon oxide.
In order to improve the gap-filling capability of the process of forming the initial isolation layer 202, the initial isolation layer 202 is formed using a Flowable Chemical Vapor Deposition (FCVD) or a high aspect ratio chemical vapor deposition process (HARP CVD). In one embodiment, the process of forming the initial isolation layer 202 includes: forming a precursor isolation film by adopting a flowable chemical vapor deposition process; and carrying out annealing and curing treatment on the precursor isolation film to convert the precursor isolation film into an initial isolation layer 202.
It should be noted that, after the initial isolation layer 202 is formed, a step of performing a planarization process on the top surface of the initial isolation layer 202, for example, by using a chemical mechanical polishing process, is further included.
In this embodiment, after the planarization process, the top of the initial isolation layer 202 is flush with the top of the hard mask layer 300.
Referring to fig. 8, a portion of the thickness of the initial isolation layer 202 is removed to form a first isolation layer 212, wherein the top of the first isolation layer 212 is lower than the top of the fin 210.
In this embodiment, the substrate 200 includes a first region i and a second region ii, and the density of the fins 210 in the first region i is greater than the density of the fins 210 in the second region ii, that is, the first region i is a dense region, and the second region ii is a sparse region. In the subsequent process of forming the stress layer, grooves are formed in the fin parts 210 at two sides of the grid structure of the first area I and the fin parts 210 at two sides of the grid structure of the second area II, and because the distance between the groove positioned in the second area II and the isolation structure is longer, the etching process for forming the groove is not easy to cause loss on the isolation structure of the second area II, and the distance between the groove positioned in the first area I and the isolation structure is closer, the etching process for forming the groove is easy to cause loss on the isolation structure of the first area I; therefore, a space position is provided for the subsequent formation of a barrier layer by removing the initial isolation layer 202 with a partial thickness of the first region i, wherein the barrier layer is used for protecting the isolation structure of the first region i in the subsequent etching process for forming the groove.
Specifically, the step of forming the first isolation layer 212 includes: forming a first pattern layer 310 on the fin portion 210 and the initial isolation layer 202 in the second region ii, where the first pattern layer 310 exposes the initial isolation layer 202 in the first region i (as shown in fig. 7); removing a part of the thickness of the initial isolation layer 202 located in the first region i by using the first pattern layer 310 as a mask, and forming a first isolation layer 212 on the first region i substrate 200; the first graphics layer 310 is removed.
A portion of the thickness of the initial isolation layer 202 is removed using one or both of a dry etch process or a wet etch process.
In this embodiment, a wet etching process is used to remove a portion of the thickness of the initial isolation layer 202. The etching liquid adopted by the wet etching process is hydrofluoric acid solution.
It should be noted that the height H of the fin 210 protruding from the first isolation layer 212 should not be too large or too small, that is, the removal amount of the initial isolation layer 202 in the first region i should not be too large or too small. If the height H of the fin portion 210 protruding from the first isolation layer 212 is too small, that is, the removal amount of the initial isolation layer 202 in the first region i is too small, it is difficult to subsequently form a barrier layer on the sidewall of the fin portion 210 protruding from the first isolation layer 212, so that when the fin portion 210 is subsequently etched to form a groove, the barrier layer has a poor protection effect on the isolation structure, and the shape of the groove is easily changed; if the height H of the fin 210 protruding from the first isolation layer 212 is too large, i.e. the removal amount of the initial isolation layer 202 in the first region i is too large, a second isolation layer is formed on the first isolation layer 212 subsequently, which is likely to cause waste of process materials. Therefore, in the present embodiment, the height H of the fin 210 protruding from the first isolation layer 212 is equal to
Figure BDA0001013104730000091
To
Figure BDA0001013104730000092
I.e. the removal of the initial spacer layer 202 of the first region I is of the amount
Figure BDA0001013104730000093
To
Figure BDA0001013104730000094
Referring to fig. 9, a barrier layer 500 is formed on the sidewalls of the fin 210 protruding from the first isolation layer 212.
The barrier layer 500 is used for preventing the etching process from over-etching the isolation structure in the edge region (e.g., region B in fig. 9) of the fin 210 when the fin 210 in the first region i is subsequently etched to form the recess, so as to prevent the recess from being changed in shape.
For this reason, in the present embodiment, the material of the barrier layer 500 is different from the material of the subsequently formed isolation structure.
In this embodiment, the material of the barrier layer 500 is silicon nitride. In other embodiments, the material of the barrier layer may also be amorphous silicon, amorphous carbon, silicon oxide, or silicon oxynitride.
In this embodiment, the process of forming the barrier layer 500 is an atomic layer deposition process. The process parameters of the atomic layer deposition process comprise: the precursor is introduced into the atomic layer deposition chamber and is a precursor containing silicon and nitrogen, the gas flow of the precursor is 500sccm to 5000sccm, the process temperature is 80 ℃ to 300 ℃, the pressure is 0.1 Torr to 20 Torr, and the deposition times are 5 times to 200 times.
When the process temperature is lower than 80 ℃, the deposition speed of each deposition process is easily caused to be too slow, so that the thickness of the barrier layer 500 is thin, or the process time needs to be increased to reach a target thickness value, so that the formation efficiency of the barrier layer 500 is reduced; when the process temperature is higher than 300 ℃, thermal decomposition of the precursor is easily caused, so that a phenomenon similar to chemical vapor deposition is introduced, the purity and the step coverage of the barrier layer 500 are affected, and the formation quality of the barrier layer 500 is finally reduced.
Based on the set process temperature, the chamber pressure, the gas flow and the deposition times are set within reasonable range values, so that the high purity and the good step coverage of the barrier layer 500 are ensured, and the formation quality of the barrier layer 500 is improved.
It should be noted that the thickness of the barrier layer 500 is not too thick nor too thin. If the thickness of the barrier layer 500 is too thick, the barrier layer 500 formed between adjacent fins 210 has hole defects due to the small space between adjacent fins 210 (i.e., the large vertical width of the opening between adjacent fins 210); if the thickness of the blocking layer 500 is too thin, the blocking layer 500 has a poor protection effect on the isolation structure at the edge of the fin 210 when the fin 210 is subsequently etched to form the groove, which easily results in the isolation at the edge of the fin 210The structure is subject to etch loss, resulting in a change in the topography of the recess. For this reason, in this embodiment, the thickness of the barrier layer 500 is
Figure BDA0001013104730000101
To
Figure BDA0001013104730000102
It should be further noted that, in the present embodiment, the blocking layer 500 further covers the top of the first isolation layer 212 and the top of the fin 210 in the first region i, and is further formed on the top of the fin 210 in the second region ii and the initial isolation layer 202.
With reference to fig. 10 to 12, after the barrier layer 500 is formed, a second isolation layer 214 is formed on the first isolation layer 212 (as shown in fig. 12), the top of the second isolation layer 214 is flush with the top of the fin 210, and the first isolation layer 212 and the second isolation layer 214 are used to form a first isolation structure 216 (as shown in fig. 12).
The first isolation structure 216 is used to isolate the first i-region neighboring devices. The second isolation layer 214 provides a process platform for a mask gate structure to be formed later.
Referring to fig. 10, a second initial isolation layer 213 is formed on the first isolation layer 212, and the top of the second initial isolation layer 213 is flush with the top of the hard mask layer 300.
The second initial isolation layer 213 provides a process foundation for the subsequent formation of the second isolation layer. The material of the second initial isolation layer 213 is an insulating material, such as silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the first isolation layer 212 and the second initial isolation layer 213 are made of the same material, and the second initial isolation layer 213 is made of silicon oxide.
In order to improve a gap-filling capability of the process of forming the second initial isolation layer 213, the second initial isolation layer 213 is formed using a Flowable Chemical Vapor Deposition (FCVD) or a high aspect ratio chemical vapor deposition process (HARP CVD). In one embodiment, the process of forming the second initial isolation layer 213 includes: forming a precursor isolation film by adopting a flowable chemical vapor deposition process; and carrying out annealing and curing treatment on the precursor isolation film to convert the precursor isolation film into a second initial isolation layer 213.
After the second initial isolation layer 213 is formed, the manufacturing method further includes: the top surface of the second initial isolation layer 213 is planarized, for example, by a chemical mechanical polishing process. In this embodiment, after the planarization process, the top of the second initial isolation layer 213 is flush with the top of the hard mask layer 300.
With reference to fig. 11, it should be noted that after the second initial isolation layer 213 is formed, the manufacturing method further includes: the initial isolation layer 202 (shown in fig. 10) is removed in a portion of the thickness of the second region II, so as to form a second isolation structure 215, wherein the top of the second isolation structure 215 is lower than the top of the fin 210.
Specifically, the step of forming the second isolation structure 215 includes: forming a second pattern layer 320 on the second initial isolation layer 213 and the hard mask layer 300 in the first region I, wherein the second pattern layer 320 exposes the initial isolation layer 202 in the second region II (as shown in fig. 10); removing the initial isolation layer 202 located in the second region II with a partial thickness by using the second pattern layer 320 as a mask, and forming a second isolation structure 215 on the second region II substrate 200; the second graphics layer 320 is removed.
And removing the initial isolation layer 202 in the second region II by using one or both of a dry etching process and a wet etching process.
In this embodiment, a wet etching process is adopted to remove the initial isolation layer 202 located in the second region II and having a partial thickness. The etching liquid adopted by the wet etching process is hydrofluoric acid solution.
After the second isolation structure 215 is formed, the manufacturing method further includes: the hard mask layer 300 of the first region I and the second region I is removed.
Specifically, the hard mask layer 300 is removed by a wet etching process; the hard mask layer 300 is made of silicon nitride, and the etching solution adopted by the wet etching process is phosphoric acid solution.
It should be further noted that the material of the blocking layer 500 is silicon nitride, and in the process of removing the hard mask layer 300, the blocking layer 500 protruding from the top of the first region I-fin portion 210 is also removed.
Referring to fig. 12, the second initial isolation layer 213 (as shown in fig. 11) protruding above the first region I-fin 210 is removed to form a second isolation layer 214, and the first isolation layer 212 and the second isolation layer 214 are used to form a first isolation structure 216.
And removing the second initial isolation layer 213 protruding out of the top of the first region I fin portion 210 by using a dry etching process, a wet etching process, a process combining the dry etching process and the wet etching process, or a planarization process. In this embodiment, the second initial isolation layer 213 protruding from the top of the first I-fin 210 is removed by a planarization process.
Referring to fig. 13, a gate structure 220 is formed across fin 210 and covering a portion of the top and sidewall surfaces of fin 210; a mask gate structure 221 is formed on the second isolation layer 214.
In this embodiment, the gate structure 220 is a dummy gate structure, and the gate structure 220 occupies a space for a metal gate structure to be formed subsequently. The gate structure 220 is a single-layer structure or a stacked structure, the gate structure 220 includes a dummy gate layer, or the gate structure 220 includes a dummy oxide layer and a dummy gate layer on the dummy oxide layer, where the dummy gate layer is made of polysilicon or amorphous carbon, and the dummy oxide layer is made of silicon oxide or silicon oxynitride.
In another embodiment, the gate structure may also be a metal gate structure, and the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, wherein the gate dielectric layer is made of silicon oxide or a high-k gate dielectric material, the gate electrode layer is made of polysilicon or a metal material, and the metal material includes one or more of Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag, or Au.
In this embodiment, the gate structure 220 is taken as a dummy gate structure as an example. Specifically, the step of forming the gate structure 220 includes: forming a dummy gate film covering the fin portion 210; forming a third pattern layer (not shown) on the surface of the dummy gate film, wherein the third pattern layer defines a pattern of the gate structure 220 to be formed; patterning the pseudo gate film by taking the third pattern layer as a mask, and forming a gate structure 220 on the surface of the fin portion 210; and removing the third graphic layer.
The mask gate structure 221 is used for performing an etching mask function when the fin portions on the two sides of the gate structure 220 are subsequently etched to form a groove, and over-etching of the first isolation structure 216 by the etching process is reduced, so that the phenomenon that the appearance of the groove is changed due to loss of the first isolation structure 216 can be avoided.
It should be noted that the gate structure 220 and the mask gate structure 221 are formed in the same process step, and the gate structure 220 and the mask gate structure 221 are made of the same material.
With continued reference to fig. 13, it should be noted that after the gate structure 220 and the mask gate structure 221 are formed, the manufacturing method further includes: a first sidewall 230 is formed on the sidewall of the gate structure 220, and a second sidewall 231 is formed on the sidewall of the mask gate structure 221.
The second sidewall 231 is used as an etching mask for subsequently etching the fin portions on the two sides of the gate structure 220 to form a groove, and overetching of the first isolation structure 216 by the etching process is reduced, so that the change of the appearance of the groove due to the loss of the first isolation structure 216 can be avoided.
In this embodiment, the first sidewall 230 and the second sidewall 231 are formed in the same process step, and the material of the first sidewall 230 and the second sidewall 231 is the same.
The first side wall 230 and the second side wall 231 in the second region may be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the first side wall 230 and the second side wall 231 may have a single-layer structure or a stacked-layer structure. In this embodiment, the first sidewall 230 and the second sidewall 231 are single-layer structures, and the material of the first sidewall 230 and the second sidewall 231 is silicon nitride.
Referring to fig. 14, the fin portion 210 located at two sides of the gate structure 220 and having a partial thickness is removed by etching, and a groove 240 is formed in the fin portion 210, wherein an etching rate of the etching process to the fin portion 210 is greater than an etching rate to the barrier layer 500.
The groove 240 provides a spatial position for the subsequent formation of a stress layer.
Specifically, the step of forming the groove 240 includes: forming a fourth pattern layer (not shown) on top of the gate structures 220, the fourth pattern layer exposing the fin portions 210 between adjacent gate structures 220; etching the fin portion 210 by using the fourth pattern layer, the first side wall 230 and the second side wall 231 as masks, and forming a groove 240 in the fin portion 210; and removing the fourth graphic layer.
The groove 240 is formed by one or both of a dry etching process and a wet etching process.
In this embodiment, the fin portion 210 located at two sides of the gate structure 220 and having a partial thickness is removed by etching using a dry etching process. In a specific embodiment, the dry etching process has the following process parameters: etching gas is O2、CH3F and H2The etching gas has a gas flow rate of 50sccm to 400sccm and a pressure of 1mtorr to 100 mtorr.
In this embodiment, the fourth pattern layer is made of a photoresist, and the fourth pattern layer is removed by a wet photoresist removal or ashing process.
In this embodiment, the substrate 200 is used to form a P-type device, and accordingly, the cross-section of the groove 240 perpendicular to the surface of the substrate 200 is Sigma-shaped. In another embodiment, when the substrate can also be used for forming an N-type device, correspondingly, the cross-sectional shape of the groove perpendicular to the substrate surface is U-shaped.
After the groove 240 is formed, the manufacturing method further includes: the groove 240 is subjected to a cleaning process.
Through the cleaning process, impurities and surface defects in the groove 240 can be reduced, and a good interface is provided for forming a stress layer in the groove 240 subsequently.
In this embodiment, the groove 240 is cleaned by a wet etching process, and an etching solution used in the wet etching process is a hydrofluoric acid solution. In another embodiment, the groove can be cleaned by using a SICONI etching process.
It should be noted that, in the process of etching the fin portion 210 located at two sides of the gate structure 220, the barrier layer 500 may protect the first isolation structure 216 in the edge region (as shown in a region B in fig. 14) of the fin portion 210, and prevent the first isolation structure 216 from being over-etched by the etching process for forming the groove 240, so as to avoid a problem that a shape of the groove 240 is changed due to over-etching, and further improve a stress effect of a stress layer formed in the groove 240 subsequently. In addition, the barrier layer 500 may also be used to prevent the first isolation structure 216 from being laterally over-etched by the cleaning process, so as to further protect the first isolation structure 216 in the edge region of the fin 210.
Referring to fig. 15, a stress layer 250 is formed in the recess 240 (shown in fig. 14); source and drain doped regions (not shown) are formed in the stress layer 250.
The stress layer 250 may be SiGe, SeGeB, SiB, SiC, SiCP, or SiP.
In this embodiment, the substrate 200 is used to form a P-type device, and the stress layer 250 is used to apply a compressive stress to a channel region of the P-type device, so as to improve hole mobility of the P-type device, and further improve electrical performance of the P-type device. Correspondingly, the cross section of the stress layer 250 perpendicular to the surface direction of the substrate 200 is Sigma-shaped, and the stress layer 250 is made of SiGe, SeGeB or SiB.
In another embodiment, the substrate is used to form an N-type device, and the stress layer is used to apply a tensile stress to a channel region of the N-type device to improve electron mobility of the N-type device, thereby improving electrical performance of the N-type device. Correspondingly, the substrate is used for forming an N-type device, the cross section of the stress layer perpendicular to the surface direction of the substrate is U-shaped, and the stress layer is made of SiC, SiCP or SiP.
In this embodiment, the stress layer 250 is formed by a selective epitaxy process, and in-situ self-doping is performed during the process of forming the stress layer 250, so as to form source-drain doped regions in the fin portions 210 on both sides of the gate structure 220. Next, a thermal annealing process is performed on the substrate 200.
In other embodiments, after the stress layer is formed, doping treatment may be performed on the stress layer, and a source-drain doped region is formed in the fin portions on both sides of the gate structure.
After forming the first isolation layer 212 (as shown in fig. 9), the invention forms a barrier layer 500 on the sidewall of the fin 210 protruding from the first isolation layer 212, and then forms the second isolation layer 214 (as shown in fig. 12) on the first isolation layer 212, the top of which is flush with the fin 210, for forming the first isolation structure 216 (as shown in fig. 12), that is, the barrier layer 500 is formed between the second isolation layer 214 and the fin 210. The fin portion 210 with a partial thickness on both sides of the gate structure 220 (as shown in fig. 14) is removed by etching, and in the process of forming the recess 240 (as shown in fig. 14) in the fin portion 210, the barrier layer 500 can prevent the etching process for forming the recess 240 from over-etching the first isolation structure 216 in the edge region (as shown in a region B in fig. 14) of the fin portion 210, so that the problem of the change in the topography of the recess 240 caused by the loss of the first isolation structure 216 can be avoided, and the electrical performance of the semiconductor device can be optimized.
Referring to fig. 15, correspondingly, the present invention also provides a semiconductor structure comprising:
a base including a substrate 200 and a discrete fin 210 on the substrate 200;
a first isolation structure 216 on the substrate 200 between the fins 210, a top of the first isolation structure 216 being flush with a top of the fins 210, the first isolation structure 216 comprising a first isolation layer 212 on the substrate 200 and a second isolation layer 214 on the first isolation layer 212;
a barrier layer 500 located between the second isolation layer 214 and the fin 210;
a gate structure 220 spanning fin 210 and covering a portion of the top and sidewall surfaces of fin 210;
a mask gate structure 221 on the second isolation layer 214;
stress layer 250 located in fin portion 210 at two sides of gate structure 220;
and a source/drain doped region (not shown) located in the stress layer 250.
The substrate 200 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of fin 210 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 200 is a silicon substrate, and the fin portion 210 is made of silicon.
In this embodiment, the substrate 200 includes a first region i and a second region ii, wherein the density of the fins 210 in the first region i is greater than the density of the fins 210 in the second region ii. In another embodiment, the substrate may also comprise only the first region.
The first isolation structure 216 is used for isolating the first i-adjacent devices, and the material of the first isolation structure 216 is an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. That is, the material of the first isolation layer 212 and the second isolation layer 214 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the first isolation structure 216 is silicon oxide, and the materials of the first isolation layer 212 and the second isolation layer 214 are the same, that is, the materials of the first isolation layer 212 and the second isolation layer 214 are silicon oxide.
The barrier layer 500 is used for protecting the first isolation structure 216 in the edge region (as shown in a region B in fig. 14) of the fin 210 during the formation of the stress layer 250, so as to prevent the first isolation structure 216 in the region from being etched and damaged, thereby avoiding a problem that the morphology of the stress layer 250 is changed due to the loss of the first isolation structure 216 in the region, and further improving the stress effect of the stress layer 250.
In order to protect the first isolation structure 216, the material of the barrier layer 500 is different from the material of the first isolation structure 216.
In this embodiment, the material of the barrier layer 500 is silicon nitride. In other embodiments, the material of the barrier layer may also be amorphous silicon, amorphous carbon, silicon oxide, or silicon oxynitride.
It should be noted that the thickness of the barrier layer 500 is not too thick nor too thin. If the thickness of the barrier layer 500 is too thick, the barrier layer 500 between adjacent fins 210 has hole defects due to the small distance between adjacent fins 210; if the thickness of the barrier layer 500 is too thin, the barrier layer 500 has a poor protection effect on the first isolation structure 216 in the edge region (as shown in the region B in fig. 14) of the fin 210, which easily causes the first isolation structure 216 in the edge region of the fin 210 to be damaged, thereby causing a change in the profile of the stress layer 250. For this reason, in this embodiment, the thickness of the barrier layer 500 is
Figure BDA0001013104730000171
To
Figure BDA0001013104730000172
The gate structure 220 is a metal gate structure, and the gate structure 220 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, wherein the gate dielectric layer is made of silicon oxide or a high-k gate dielectric material, the gate electrode layer is made of polysilicon or a metal material, and the metal material includes one or more of Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag, or Au.
In this embodiment, the gate structure 220 and the mask gate structure 221 are made of the same material. The mask gate structure 221 is used for performing an etching mask function in the process of forming the stress layer 250, and is also used for protecting the first isolation structure 216 in the edge region (shown as a region B in fig. 14) of the fin 210.
The stress layer 250 may be SiGe, SeGeB, SiB, SiC, SiCP, or SiP.
In this embodiment, the semiconductor structure is a P-type device, and the stress layer 250 is used to apply a compressive stress to a channel region of the P-type device, so as to improve the hole mobility of the P-type device, and further improve the electrical performance of the P-type device. Correspondingly, the cross section of the stress layer 250 perpendicular to the surface direction of the substrate 200 is Sigma-shaped, and the stress layer 250 is made of SiGe, SeGeB or SiB.
In another embodiment, the semiconductor structure is an N-type device, and the stress layer is used for applying a tensile stress effect to a channel region of the N-type device to improve electron mobility of the N-type device, thereby improving electrical performance of the N-type device. Correspondingly, the cross section of the stress layer perpendicular to the surface direction of the substrate is U-shaped, and the stress layer is made of SiC, SiCP or SiP.
In addition, the semiconductor structure further includes: a first sidewall 230 on the sidewall of the gate structure 220, and a second sidewall 231 on the sidewall of the mask gate structure 221.
In this embodiment, the first sidewall 230 and the second sidewall 231 are made of the same material. The first sidewall 230 and the second sidewall 231 are used as an etching mask in an etching process for forming the stress layer 250.
The material of the first and second sidewalls 230 and 231 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the first and second sidewalls 230 and 231 may have a single-layer structure or a stacked-layer structure. In this embodiment, the first sidewall 230 and the second sidewall 231 are single-layer structures, and the material of the first sidewall 230 and the second sidewall 231 is silicon nitride.
It should be further noted that the semiconductor structure further includes: a second isolation structure 215 on the second region II substrate 200.
The second isolation structure 215 is used to isolate adjacent devices in the second region ii, and the material of the second isolation structure 215 is an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the second isolation structure 215 is made of silicon oxide.
The semiconductor structure provided by the invention comprises the barrier layer 500 positioned between the second isolation layer 214 and the fin portion 210, wherein the barrier layer 500 is used for protecting the isolation structure 216 in the edge region (shown as a region B in fig. 14) of the fin portion 210, and the isolation structure 216 in the region is prevented from being subjected to etching loss in the process of forming the stress layer 250, so that the problem of shape change of the stress layer 250 caused by the loss of the isolation structure 216 is avoided, and further, the electrical performance of the semiconductor device is optimized.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A method of fabricating a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and discrete fin parts positioned on the substrate;
forming a first isolation layer on the substrate between the fin parts, wherein the top of the first isolation layer is lower than that of the fin parts;
forming a barrier layer on the side wall of the fin part protruding out of the first isolation layer;
after the barrier layer is formed, forming a second isolation layer on the first isolation layer, wherein the top of the second isolation layer is flush with the top of the fin part, and the first isolation layer and the second isolation layer are used for forming an isolation structure;
forming a grid electrode structure which crosses the fin part and covers the top of the fin part and the surface of the side wall;
forming a mask gate structure on the second isolation layer;
removing fin parts with partial thickness positioned at two sides of the grid electrode structure by using an etching process, forming a groove in the fin parts, wherein the bottom of the groove is higher than the top of the first isolation layer, and the etching rate of the etching process to the fin parts is greater than that to the barrier layer;
forming a stress layer in the groove;
and forming a source drain doped region in the stress layer.
2. The method of fabricating a semiconductor structure according to claim 1, wherein a material of the barrier layer is different from a material of the second isolation layer.
3. The method for manufacturing a semiconductor structure according to claim 1 or 2, wherein a material of the barrier layer is amorphous silicon, amorphous carbon, silicon oxide, silicon nitride, or silicon oxynitride.
4. The method of fabricating a semiconductor structure of claim 1, wherein the barrier layer has a thickness of
Figure FDA0002388188810000011
To
Figure FDA0002388188810000012
5. The method of fabricating a semiconductor structure of claim 1, wherein the process of forming the barrier layer is an atomic layer deposition process.
6. The method of claim 5, wherein the material of the barrier layer is silicon nitride, and the atomic layer deposition process comprises the following process parameters: the precursor is introduced into the atomic layer deposition chamber and is a precursor containing silicon and nitrogen, the gas flow of the precursor is 500sccm to 5000sccm, the process temperature is 80 ℃ to 300 ℃, the pressure is 0.1 Torr to 20 Torr, and the deposition times are 5 times to 200 times.
7. The method of claim 1, wherein in the step of forming a barrier layer on fin sidewalls protruding from the first isolation layer, the barrier layer further covers a top of the first isolation layer and a top of the fin;
and in the step of forming the second isolation layer on the first isolation layer, removing the barrier layer protruding out of the top of the fin part.
8. The method of claim 1, wherein a height of the fin protruding from the first isolation layer is greater than a height of the fin protruding from the first isolation layer
Figure FDA0002388188810000021
To
Figure FDA0002388188810000022
9. The method of fabricating a semiconductor structure according to claim 1, wherein after forming the recess and before forming the stress layer in the recess, the method further comprises: and carrying out a cleaning process on the groove.
10. The method of fabricating a semiconductor structure according to claim 9, wherein the step of cleaning comprises: cleaning the groove by using a SICONI etching process;
or, cleaning the groove by adopting a wet etching process, wherein the etching solution adopted by the wet etching process is a hydrofluoric acid solution.
11. The method according to claim 1, wherein the semiconductor structure is an NMOS structure, and a cross-sectional shape of the recess in a direction perpendicular to the surface of the substrate is a U-shape;
or, the semiconductor structure is a PMOS structure, and the cross section of the groove in the direction vertical to the surface of the substrate is Sigma-shaped.
12. The method of manufacturing a semiconductor structure according to claim 1, wherein the first isolation layer and the second isolation layer are made of the same material.
13. The method of manufacturing a semiconductor structure according to claim 1, wherein a material of the first isolation layer is silicon oxide, silicon nitride, or silicon oxynitride, and a material of the second isolation layer is silicon oxide, silicon nitride, or silicon oxynitride.
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