CN110875186B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110875186B
CN110875186B CN201811016961.6A CN201811016961A CN110875186B CN 110875186 B CN110875186 B CN 110875186B CN 201811016961 A CN201811016961 A CN 201811016961A CN 110875186 B CN110875186 B CN 110875186B
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forming
layer
substrate
groove
mask
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CN110875186A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is higher than that of the first device; etching a substrate of the first region to form a first substrate and a plurality of first fin parts separated from the first substrate, wherein first grooves are formed between adjacent first fin parts; etching the substrate of the second region to form a second substrate and a plurality of second fin parts separated from the second substrate, wherein second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than the depth of the first groove. In the embodiment of the invention, the second substrate in the second device is closer to the external space than the first substrate in the first device, and the depth-to-width ratio of the second groove in the second device is smaller than that of the first groove in the first device, so that the heat dissipation performance of the second device is better than that of the first device.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short-channel effect (SCE), is more likely to occur.
Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; and finfets have better compatibility with existing integrated circuit fabrication than other devices.
In FinFET devices, fin is increasingly smaller in width in order to be able to enhance control of the channel, and silicon germanium channels are employed in order to obtain better device performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which optimize the electrical performance of the semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region and a second region, the first region is used for forming a first device, the second region is used for forming a second device, and the power of the second device is higher than that of the first device; etching a substrate of the first region to form a first substrate and a plurality of first fin parts separated from the first substrate, wherein first grooves are formed between adjacent first fin parts; etching the substrate of the second region to form a second substrate and a plurality of second fin parts separated from the second substrate, wherein second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than that of the first groove.
Correspondingly, the invention also provides a semiconductor structure, which comprises: a substrate comprising a second region for forming a second device and a first region for forming a first device, the second device having a higher power than the first device; the first region comprises a first substrate and a plurality of first fin parts separated from the first substrate, and first grooves are formed between adjacent first fin parts; the second region comprises a second substrate and a plurality of second fin parts separated from the second substrate, and second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than that of the first groove.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a substrate, which comprises a first area and a second area, wherein the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is higher than that of the first device; a first fin part and a first groove positioned between adjacent first fin parts are formed in the first region; a second fin part and a second groove positioned between adjacent second fin parts are formed in the second region; the depth of the second groove is smaller than that of the first groove, the second substrate in the second device is closer to the external space than the first substrate in the first device, and the depth-to-width ratio of the second groove in the second device is smaller than that of the first groove in the first device, so that the heat dissipation performance of the second device is better than that of the first device, even if the power of the second device is higher, the heat dissipation performance is better, the whole semiconductor structure (the first device and the second device) is not easy to generate self-heating effect, and the performance of the semiconductor structure is optimized.
In an alternative scheme, a first isolation layer is formed in the first groove, a second isolation layer is formed in the second groove, the thickness of the second isolation layer is smaller than that of the first isolation layer, the density of the second isolation layer is larger than that of the first isolation layer, in a subsequent process, the etched rate of the second isolation layer is smaller than that of the first isolation layer, therefore, the second isolation layer is not easy to be damaged, and further, the electric leakage problem of devices in the second groove is not easy to occur.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure in a method of forming the same;
fig. 2 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 12 to 17 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, in a FinFET device, in order to enhance control over a channel, the width of Fin is smaller and smaller, and in order to obtain better device performance, the FinFET device adopts a silicon germanium channel, and the reason why the electrical performance of a semiconductor structure needs to be improved is now analyzed in combination with a method for forming the semiconductor structure.
Referring to fig. 1, a schematic structure diagram in a method of forming a semiconductor structure is shown.
Referring to fig. 1, the substrate includes a first region I for forming a first device and a second region II for forming a second device having a higher power than the first device. Etching the base to form a substrate 1 and a plurality of discrete fin portions 2 positioned on the substrate 1, and forming isolation layers 3 on the substrate 1 between the fin portions 2.
In order to enhance the control of the channel, the width of Fin is smaller and smaller, and more Fin is formed in unit area, which makes it difficult to quickly dissipate the heat generated by the FinFET device; on the other hand, in order to obtain better device performance, a silicon germanium channel is used, and the heating power of the silicon germanium channel is higher than that of a conventional silicon channel.
Since the surface heights of the substrate 1 in the first region I and the second region II tend to be the same, that is, the structures of the devices in the first region I and the second region II are the same, the heat dissipation capacities of the first device and the second device are the same. But the power of the second device is higher than that of the first device, the heating value of the second device is higher than that of the first device, and the heat in the second device cannot be timely removed, so that the performance of the device is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region and a second region, the first region is used for forming a first device, the second region is used for forming a second device, and the power of the second device is higher than that of the first device; etching a substrate of the first region to form a first substrate and a plurality of first fin parts separated from the first substrate, wherein first grooves are formed between adjacent first fin parts; etching the substrate of the second region to form a second substrate and a plurality of second fin parts separated from the second substrate, wherein second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than that of the first groove.
The embodiment of the invention provides a substrate, which comprises a first area and a second area, wherein the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is higher than that of the first device; a first fin part and a first groove positioned between adjacent first fin parts are formed in the first region; a second fin part and a second groove positioned between adjacent second fin parts are formed in the second region; the depth of the second groove is smaller than that of the first groove, the second substrate in the second device is closer to the external space than the first substrate in the first device, and the depth-to-width ratio of the second groove in the second device is smaller than that of the first groove in the first device, so that the heat dissipation performance of the second device is better than that of the first device, even if the power of the second device is higher, the heat dissipation performance is better, the whole semiconductor structure (the first device and the second device) is not easy to generate self-heating effect, and the performance of the semiconductor structure is optimized.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 100 is provided, the substrate 100 including a first region I for forming a first device and a second region II for forming a second device having a higher power than the first device.
A substrate 100 is provided, the substrate 100 providing a process platform for the subsequent formation of a first recess and a second recess.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors, etc., can also be formed within the substrate 100. The substrate 100 may further have an interface layer formed on a surface thereof, and the interface layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the first area I and the second area II are adjacent areas. In other embodiments, the first region I and the second region II may also be isolated.
In this embodiment, the first device is a PMOS device, and the second device is an NMOS device. In other embodiments, the first device may be an NMOS device and the second device may be a PMOS device.
Referring to fig. 3 to 7, the base 100 of the second region II is etched to form a second substrate 200 and a plurality of second fin portions separated on the second substrate 200, and second grooves 202 are formed between adjacent second fin portions. The second recess 202 is used to provide a space for filling the isolation layer in a subsequent process.
That is, in this embodiment, the substrate of the second region II is etched first, so as to form the second fin portion and the second recess 202; and after the second fin part is formed, etching the substrate of the first region I to form the first fin part and the first groove.
As shown in fig. 3, the step of forming the second fin portion and the second recess includes: a mask material layer 110 is formed to cover the substrate 100, and a plurality of discrete core layers 120 are formed on the mask material layer 110. The mask material layer 110 is used to prepare for a mask layer to be formed later. The core layer 120 is used for preparing for the subsequent formation of mask sidewalls covering the sidewalls of the core layer 120.
In this embodiment, the mask material layer 110 is a stacked structure, and the mask material layer 110 includes a base protective material layer 1102, a hard mask material layer 1101 formed on the base protective material layer 1102, and a high-performance metal oxide material layer 1103 formed on the hard mask material layer 1101.
The substrate protection material layer 1102 is used to reduce the effect of the stress of the hard mask material layer 1101 on the substrate 100. The high-performance metal oxide material layer 1103 is used for protecting the hard mask material layer 1101, and when the core layer 120 and the mask sidewall 130 are removed in the subsequent process, damage to the hard mask material layer 1101 can be reduced.
In this embodiment, the material of the base protection material layer 1102 is silicon oxide.
In this embodiment, the material of the hard mask material layer 1101 is silicon nitride. In other embodiments, the material of the hard mask material layer 1101 may be silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the material of the high-performance metal oxide layer 1103 is silicon oxide. In other embodiments, the material of the high performance metal oxide material layer 1103 may also be silicon nitride or silicon oxynitride.
In this embodiment, the material of the core layer 120 is polysilicon. In other embodiments, the material of the core layer 120 may also be amorphous carbon, ODL material, DARC material, or BARC material.
The core layer 120 is etched at a rate greater than that of the mask material layer 110, and damage to the mask material layer 110 can be reduced when the core layer 120 is removed.
As shown in fig. 4, a mask sidewall 130 is formed to cover the sidewall of the core layer 120. In the subsequent process, the substrate 100 material is etched using the mask sidewall 130 as a mask, so as to form a second recess.
The material of the mask sidewall 130 is different from the material of the high-performance metal oxide layer 1103, and the material of the mask sidewall 130 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or boron nitride. In this embodiment, the mask sidewall 130 is made of silicon nitride.
As shown in fig. 5, a mask protection layer 140 is formed on the mask material layer 110 exposed by the mask sidewall 130 and the core layer 120. The mask protection layer 140 and the core layer 120 are used to provide a process platform for a subsequently formed barrier layer.
In this embodiment, the material of the mask protection layer 140 is a bottom anti-reflective coating.
As shown in fig. 6, after the mask protection layer 140 is formed, a shielding layer 150 is formed to cover the first region I. The shielding layer 150 is used for etching the substrate 100 material of the second region II in a subsequent process, so as to avoid etching the substrate material of the first region I when forming the second recess.
In this embodiment, the first region I includes the mask protection layer 140 and the core layer 120, and the shielding layer 150 covers the mask sidewall 130, the mask protection layer 140 and the core layer 120. In other embodiments, only the mask protection layer or the core layer is present in the first region I.
In this embodiment, the material of the shielding layer 150 is different from the materials of the mask protection layer 140 and the core layer 120, the material of the shielding layer 150 is amorphous carbon, and in other embodiments, the material of the shielding layer may also be an ODL material or a DARC material.
As shown in fig. 7, in the second region II, the substrate 100 is etched using the mask sidewall 130 as a mask, so as to form a second recess 202.
In this embodiment, in the second area II, only one core layer 120 (as shown in fig. 6), the core layer 120 is removed in the process of forming the second groove 202, and in other embodiments, the mask protection layer may be removed, or the core layer and the mask protection layer may be removed simultaneously, so as to form the second groove.
In this embodiment, the first region I and the second region II are adjacent regions, and fig. 7 illustrates one second recess 202, but does not illustrate the second fin portion, where the second fin portion is formed when the first recess is formed in a subsequent process. The bottom surface of the second recess 202 is the second substrate 200, and in other embodiments, a plurality of second recesses are formed on the second substrate, and second fins are formed between the second recesses. And besides the second grooves between the second fin parts, the second grooves are also arranged on two sides of the second fin parts.
It should be noted that, if the depth of the second groove 202 is too deep, the distance between the second groove 202 and the external space is too far, so that the aspect ratio of the second groove 202 is too large, which is not beneficial to heat dissipation, and if the depth of the second groove 202 is too shallow, the process space reserved for the isolation layer at a later stage is reduced, and the thickness of the isolation layer is thinner, which is not beneficial to reducing the leakage problem of the device. Accordingly, the depth of the second recess 202 is 600 to 900 a.
Referring to fig. 8 to 10, the substrate 100 of the first region I is etched to form a first substrate 300 and a plurality of first fins 301 separated from the first substrate 300, and a first groove 302 is formed between adjacent first fins 301; the depth of the second recess 202 (shown in fig. 7) is less than the depth of the first recess 302. The first recess 302 is used to provide a space for filling the isolation layer in a subsequent process.
As shown in fig. 8 to 9, the step of forming the first fin 301 and the first recess 302 includes: forming a groove protection layer 203 in the second groove 202; in the first region I, removing the shielding layer 150, and removing the core layer 120 and the mask protection layer 140 after removing the shielding layer 150; and etching the substrate 100 material by taking the mask side wall 130 as a mask to form the first groove 302.
In this embodiment, the material of the groove protection layer 203 is bottom anti-reflection coating, silicon oxide, silicon nitride or silicon oxynitride.
It should be further noted that, if the depth of the first groove 302 is too deep, the distance between the first groove 302 and the external space is too far, so that the aspect ratio of the first groove 302 is too large, which is not beneficial to heat dissipation, and if the depth of the first groove 302 is too shallow, the process space reserved for the isolation layer in the later stage is reduced, and the thickness of the isolation layer is thinner, which is not beneficial to reducing the leakage problem of the device. Accordingly, the first recess 302 has a depth of 1000 to 1500 angstroms.
In this embodiment, the step of forming the first recess 302 by using the mask sidewall 130 as a mask to etch the substrate 100 material includes: etching the mask material layer 110 by taking the mask side wall 130 as a mask to form a mask layer 160; and removing the mask side wall 130, and etching the substrate 100 by taking the mask layer 160 as a mask to form the first groove 302. Because the mask material layer 110 is a stacked structure, and accordingly, the mask layer 160 is also a stacked structure, the mask layer 160 includes a base protection layer 1602, a hard mask layer 1601 formed on the base protection layer 1602, and a high performance metal oxide layer 1603 formed on the hard mask layer 1601.
In this embodiment, the bottom surface of the first groove 302 is a first substrate 300, a first fin 301 is formed on the first substrate 300, and the first groove 302 is formed between adjacent first fins 301. The depth of the second groove 202 is smaller than that of the first groove 302, the second substrate 200 in the second device is closer to the external space than the first substrate 300 in the first device, and the depth-to-width ratio of the second groove 202 in the second device is higher than that of the first groove 302 in the first device, so that the heat dissipation performance of the second device is better than that of the first device.
In this embodiment, in the first region I, in addition to the first grooves 302 between the first fin portions 301, the first grooves 302 are also formed on two sides of the first fin portions 301. In other embodiments, the first recess is only present between the first fins.
In this embodiment, the first region I and the second region II are adjacent regions, and the step of forming the first recess 302 by using the mask sidewall 130 as a mask to etch the substrate 100 material further includes: in the second region II, a second fin 201 is formed at a junction between the first region I and the second region II. In other embodiments, the first region I and the second region II are not adjacent regions, and the second fin portion is not formed in the step of etching the mask material layer and the substrate material to form the first recess by using the mask layer as a mask.
The first area I and the second area II are adjacent areas, and in this embodiment, the junction between the first area I and the second area II is just the position of the sidewall of the second groove 202. In other embodiments, the interface between the first region I and the second region II may be a highly arbitrary base material.
As shown in fig. 10, after forming the first recess 302 and the second recess 202, part of the fin portions 301 and 201 are dummy fin portions 303, and the method for forming the semiconductor structure further includes: after the second fin 201 and the first fin 301 are formed, the dummy fin 303 is removed before the isolation layer is formed.
Referring to fig. 11, the method for forming the semiconductor structure includes: after forming the first recess 302 (shown in fig. 9) and the second recess 202 (shown in fig. 7), an isolation layer 204 is formed in the first recess 302 and the second recess 202. The isolation layer 204 is used to isolate adjacent devices from each other.
The step of forming the isolation layer 204 in the first recess 302 and the second recess 202 comprises: forming a first isolation material layer covering the first grooves 302 and a second isolation material layer covering the second grooves 202, and simultaneously performing mechanical planarization treatment on the first isolation material layer and the second isolation material layer; after the first isolation material layer and the second isolation material layer are mechanically planarized, a material with a partial thickness is etched back, and the remaining first isolation material layer and the remaining second isolation material layer after the etching back are used as isolation layers 204.
The step of forming the isolation layer 204 in the first recess 302 and the second recess 202 comprises: a first isolation layer 206 is formed in the first recess 302, and a second isolation layer 205 is formed in the second recess 202, the second isolation layer 205 having a higher density than the first isolation layer 206. The depth of the second groove 202 is smaller than that of the first groove 302, so that the thickness of the second isolation layer 205 is smaller than that of the first isolation layer 206, the density of the second isolation layer 205 is larger than that of the first isolation layer 206, and in the subsequent process, the etched rate of the second isolation layer 205 is smaller than that of the first isolation layer 206, so that the second isolation layer 205 is not easily damaged, and further, the leakage problem of devices in the second groove 202 is not easily generated.
In this embodiment, the material of the first isolation layer 206 is silicon oxide, and the material of the second isolation layer 205 is silicon nitride.
The method for forming the semiconductor structure comprises the following steps: after the first recess 302 is formed, the recess protection layer 203 is removed (as shown in fig. 10). When the material of the groove protection layer 203 (as shown in fig. 10) is silicon oxide, after the first groove 302 is formed, the groove protection layer 203 is etched back to form a second isolation layer 205. When the material of the groove protection layer 203 is bottom anti-reflection coating, silicon nitride or silicon oxynitride, after the first groove 302 is formed, the groove protection layer 203 is removed, then a silicon oxide layer covering the second groove 202 is formed, and then the silicon oxide layer is etched back to obtain a second isolation layer 205.
Fig. 12 to 17 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the embodiment of the present invention.
The point of the present embodiment that is the same as the previous embodiment is not described in detail, and the difference is that: and forming the sequence of the first groove and the second groove. Specifically, in this embodiment, the substrate of the first region is etched first, so as to form a first fin portion and the first groove; and after the first fin part is formed, etching the substrate of the second region to form the second fin part and the second groove.
Referring to fig. 12 to fig. 13, etching the base 400 of the first region I to form a first substrate 500 and a plurality of first fin portions 501 separated from the first substrate 500, and a first groove 502 is formed between adjacent first fin portions 501; the first recess 502 is used to provide a space for filling the isolation layer in a subsequent process.
As shown in fig. 12, the step of forming the first fin portion and the first recess includes: forming a mask material layer 410 covering the substrate 400, and forming a plurality of discrete core layers 420 on the mask material layer 410; forming a mask sidewall 430 covering the sidewall of the core layer 420; forming a mask protection layer 440 on the mask material layer 410 exposed by the mask sidewall 430 and the core layer 420; after forming the mask protection layer 440, a shielding layer 450 covering the second region II is formed. The masking material layer 410 is used to prepare for a subsequently formed masking layer. The core layer 420 is used to prepare for the subsequent formation of mask spacers 430 that cover the sidewalls of the core layer 420.
In this embodiment, the mask material layer 410 has a stacked structure, and the mask material layer 410 includes a base protective material layer 4102, a hard mask material layer 4101 formed on the base protective material layer 4102, and a high-performance metal oxide material layer 4103 formed on the hard mask material layer 4101.
In this embodiment, the material of the core layer 420 is polysilicon. In other embodiments, the material of the core layer 420 may also be amorphous carbon, ODL material, DARC material, or BARC material.
The core layer 420 is etched at a greater rate than the mask material layer 410, and damage to the mask material layer 410 can be reduced when the core layer 420 is removed.
The material of the mask sidewall 430 is different from the material of the high-performance metal oxide material layer 4103, and the material of the mask sidewall 430 is silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or boron nitride. In this embodiment, the mask sidewall 430 is made of silicon nitride.
In this embodiment, the first area I includes the core layer 420. The shielding layer 450 covers the first region I, that is, the shielding layer 450 covers the core layer 420.
In this embodiment, the material of the mask protection layer 440 is a bottom anti-reflective coating.
In this embodiment, the material of the shielding layer 450 is different from the materials of the mask protection layer 440 and the core layer 420, the material of the shielding layer 450 is amorphous carbon, and in other embodiments, the material of the shielding layer may be an ODL material or a DARC material.
As shown in fig. 13, in the first region I, the core layer 420 and the mask protection layer 440 are removed, and the substrate 400 is etched with the mask sidewall 430 as a mask, so as to form a first groove 502.
In this embodiment, during the process of forming the first groove 502, the core layer 420 and the mask protection layer 440 are removed, and in other embodiments, the first groove may be formed by removing the mask protection layer or the core layer.
In this embodiment, the bottom surface of the first groove 502 is the first substrate 500, the first grooves 502 are also formed on two sides of the first fin 501 except for the first grooves 502 formed between the first fin 501, and the bottom surface of the first groove 502 is the first substrate 500. In other embodiments, the first region I and the second region II are adjacent regions, a first recess is formed on the first substrate, and the first fin portion on the first substrate is formed when the base material is etched in a subsequent process to form the second recess.
It should be noted that, if the depth of the first groove 502 is too deep, the distance between the first groove 502 and the external space is too far, so that the aspect ratio of the first groove 502 is too large, which is not beneficial to heat dissipation, and if the depth of the first groove 502 is too shallow, the process space reserved for the isolation layer in the later stage is reduced, and the thickness of the isolation layer is thinner, which is not beneficial to reduce the leakage problem of the device. Accordingly, the first groove 502 has a depth of 1000 to 1500 angstroms.
Referring to fig. 14 to 16, etching the base 400 of the second region II (as shown in fig. 12), to form a second substrate 600 and a plurality of second fins 601 separated from the second substrate 600, and a second groove 602 is formed between adjacent second fins 601; the depth of the second groove 602 is less than the depth of the first groove 502 (shown in fig. 13). The second recess 602 is used to provide a space for filling the isolation layer in a subsequent process.
As shown in fig. 14 to 15, the step of forming the second fin 601 and the second recess 602 includes: a groove protection layer 503 is formed in the first groove 502, in the second region II, the shielding layer 450 is removed, after the shielding layer 450 is removed, the core layer 420 and the mask sidewall 430 are removed, and the mask sidewall 430 (as shown in fig. 14) is used to form the second groove 602 by etching the substrate 400 material with a mask.
In this embodiment, the core layer 420 is removed after removing the shielding layer 450 (as shown in fig. 14), in preparation for forming the second recess 602 in the substrate 400 to be etched later. In other embodiments, the mask protection layer may be removed, or the mask protection layer or core layer may be removed simultaneously, in preparation for subsequent etching of the substrate to form the second recess.
In this embodiment, the step of forming the second recess 602 by etching the substrate 400 material using the mask sidewall 430 (as shown in fig. 14) as a mask includes: etching the mask material layer 410 by taking the mask side wall 430 as a mask to form a mask layer 460; etching the substrate 400 material by using the mask sidewall 430 as a mask to form a second groove 602; after the second recess 602 is formed, the mask sidewall 430 is removed.
In this embodiment, the mask material layer 410 includes a base protective material layer 4102, a hard mask material layer 4101 formed on the base protective material layer 4102, and a high-performance metal oxide material layer 4103 formed on the hard mask material layer 4101. Accordingly, the mask layer 460 is formed to include a base protective layer 4602, a hard mask layer 4601 formed on the base protective layer 4602, and a high performance metal oxide layer 4603 formed on the hard mask layer 4601.
In this embodiment, the second grooves 602 are formed between the second fin portions 601. In other embodiments, a second groove is formed between the second fin portions, and second grooves are also formed on two sides of the second fin portions.
In this embodiment, the material of the recess protection layer 503 is bottom anti-reflection coating, silicon oxide, silicon nitride or silicon oxynitride.
It should be further noted that, if the depth of the second groove 602 is too deep, the distance between the second groove 602 and the external space is too far, so that the aspect ratio of the second groove 602 is too large, which is not beneficial to heat dissipation, and if the depth of the second groove 602 is too shallow, the process space reserved for the isolation layer in the later stage is reduced, and the thickness of the isolation layer is thinner, which is not beneficial to reducing the leakage problem of the device. Accordingly, the depth of the second groove 602 is 600 to 900 a.
In this embodiment, the bottom surface of the second groove 602 is the second substrate 600, the second fin portion 601 is formed on the second substrate 600, and the second groove 602 is between adjacent second fin portions 601. The depth of the second groove 602 is smaller than the depth of the first groove 502 (as shown in fig. 13), and the second substrate 600 in the second device is closer to the external space than the first substrate 500 in the first device, and thus, the heat dissipation performance of the second device is better than that of the first device.
As shown in fig. 16, after forming the first recess 502 (as shown in fig. 13) and the second recess 602, part of the fin portions in the first fin portion 501 and the second fin portion 601 are dummy fin portions 603, and the method for forming a semiconductor structure further includes: after the second fin 601 and the first fin 501 are formed, the dummy fin 603 is removed before the isolation layer is formed.
In this embodiment, the method for forming a semiconductor structure includes: after the first groove 502 and the second groove 602 are formed, the groove protection layer 503 is removed before the dummy fin 603 is removed.
Referring to fig. 17, the method for forming the semiconductor structure includes: after forming the first groove 502 (as shown in fig. 16) and the second groove 602 (as shown in fig. 16), an isolation layer 504 is formed in the first groove 502 and the second groove 602.
The step of forming the isolation layer 504 in the first groove 502 and the second groove 602 is referred to an embodiment, and will not be described herein.
The method for forming the semiconductor structure further comprises the following steps: after the first groove 502 is formed, the groove protection layer 503 is removed, and the specific forming method is the same as that of the previous embodiment, and will not be described herein.
The invention also provides a semiconductor structure. Referring to fig. 11, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
Referring to fig. 11, a semiconductor structure includes a substrate including a second region II for forming a second device and a first region I for forming a first device, the second device II having a higher power than the first device; the first region I includes a first substrate 300 and a plurality of first fin portions 301 separated from the first substrate 300, and first grooves 302 are formed between adjacent first fin portions 301; the second region II includes a second substrate 200 and a plurality of second fin portions 201 separated from the second substrate 200, and second grooves 202 are formed between adjacent second fin portions 201; the depth of the second recess 202 is less than the depth of the first recess 302.
In this embodiment, the substrate is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors, can also be formed within the substrate. The substrate surface can also be formed with an interface layer, and the interface layer is made of silicon oxide, silicon nitride, silicon oxynitride or the like.
In this embodiment, the first area I and the second area II are adjacent areas. In other embodiments, the first region I and the second region II may also be isolated. In this embodiment, the junction between the first region I and the second region II is just the position of the sidewall of the second groove 202. In other embodiments, the interface between the first region I and the second region II may be a highly arbitrary base material.
In this embodiment, the first device is a PMOS device, and the second device is an NMOS device. In other embodiments, the first device is an NMOS device and the second device is a PMOS device.
In this embodiment, the depth of the second groove 202 cannot be too deep or too shallow, if the second groove 202 is too deep, the distance between the second groove 202 and the external space is too far, so that the aspect ratio of the second groove 202 is too large, which is not beneficial to heat dissipation, and if the second groove 202 is too shallow, the process space reserved for the isolation layer in the later stage is reduced, which is not beneficial to reducing the leakage problem of the device. Accordingly, the depth of the second recess 202 is 600 to 900 a.
In this embodiment, the depth of the first groove 302 cannot be too deep or too shallow, if the first groove 302 is too deep, the distance between the first groove 302 and the external space is too far, so that the aspect ratio of the first groove 302 is too large, which is not beneficial to heat dissipation, and if the first groove 302 is too shallow, the process space reserved for the isolation layer in the later stage is reduced, and the thickness of the isolation layer is thinner, which is not beneficial to reducing the leakage problem of the device. Accordingly, the first recess 302 has a depth of 1000 to 1500 angstroms.
In this embodiment, the isolation layer 204 is formed in the first groove 302 and the second groove 202.
Specifically, the isolation layer 204 located in the second groove 202 is a second isolation layer 205, the isolation layer located in the first groove 302 is a first isolation layer 206, and the density of the second isolation layer 205 is higher than that of the first isolation layer 206. The depth of the second recess 202 is less than the depth of the first recess 302, and thus the thickness of the second isolation layer 205 is less than the thickness of the first isolation layer 206. The density of the second isolation layer 205 is greater than that of the first isolation layer 206, in the process of forming the semiconductor structure, the etched rate of the second isolation layer 205 is smaller than that of the first isolation layer 206, the second isolation layer 205 is not easily damaged, and the device in the second groove 202 is not easily subjected to leakage.
Specifically, the material of the first isolation layer 206 is silicon oxide, and the material of the second isolation layer 205 is silicon nitride.
In this embodiment, the depth of the second groove 202 is smaller than the depth of the first groove 302, the second substrate 200 in the second device is closer to the external space than the first substrate 300 in the first device, and the aspect ratio of the second groove 202 in the second device is smaller than the aspect ratio of the first groove 302 in the first device, so that the heat dissipation performance of the second device is better than that of the first device.
The semiconductor structure of this embodiment may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. In this embodiment, for a specific description of the semiconductor structure, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, the first region is used for forming a first device, the second region is used for forming a second device, and the power of the second device is higher than that of the first device;
etching a substrate of the first region to form a first substrate and a plurality of first fin parts separated from the first substrate, wherein first grooves are formed between adjacent first fin parts;
etching the substrate of the second region to form a second substrate and a plurality of second fin parts separated from the second substrate, wherein second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than that of the first groove.
2. The method of forming a semiconductor structure of claim 1, wherein a depth of the second recess is 600 to 900 a.
3. The method of forming a semiconductor structure of claim 1, wherein a depth of the first recess is 1000 to 1500 angstroms.
4. The method of claim 1, wherein the substrate of the second region is etched first to form a second fin and the second recess; and after the second fin part is formed, etching the substrate of the first region to form the first fin part and the first groove.
5. The method of forming a semiconductor structure of claim 4, wherein,
the step of forming the second fin portion and the second groove includes:
forming a mask material layer covering the substrate, and forming a plurality of discrete core layers on the mask material layer;
forming a mask side wall covering the side wall of the core layer;
forming a mask protection layer on the mask material layer exposed by the mask side wall and the core layer;
forming a shielding layer covering the first area after forming the mask protection layer;
in the second region, removing the core layer, and etching the substrate material by taking the mask side wall as a mask to form a second groove;
the step of forming the first fin and the first recess includes:
forming a groove protection layer in the second groove;
removing the shielding layer in the first region;
after removing the shielding layer, removing the core layer and the mask protection layer;
etching a substrate material by taking the mask side wall as a mask to form the first groove;
the method for forming the semiconductor structure comprises the following steps: and removing the groove protection layer after the first groove is formed.
6. The method of claim 1, wherein the first region of the substrate is etched to form a first fin and the first recess; and after the first fin part is formed, etching the substrate of the second region to form the second fin part and the second groove.
7. The method of forming a semiconductor structure of claim 6, wherein,
the step of forming the first fin and the first groove includes:
forming a mask material layer covering the substrate, and forming a plurality of discrete core layers on the mask material layer;
forming a mask side wall covering the side wall of the core layer;
forming a mask protection layer on the mask material layer exposed by the mask side wall and the core layer; forming a shielding layer covering the second area after forming the mask protection layer; removing the core layer and the mask protection layer in the first region, and etching the substrate material by taking the mask side wall as a mask to form a first groove;
the step of forming the second fin and the second recess includes:
forming a groove protection layer in the first groove;
removing the shielding layer in the second region;
after removing the shielding layer, removing the core layer and the mask protection layer;
etching the substrate material by taking the mask side wall as a mask to form the second groove;
the method for forming the semiconductor structure comprises the following steps: and removing the groove protection layer after the second groove is formed.
8. The method of forming a semiconductor structure of claim 1, wherein the method of forming a semiconductor structure comprises: after the first and second grooves are formed, an isolation layer is formed in the first and second grooves.
9. The method of claim 8, wherein a portion of the first fin and the second fin is a dummy fin, the method further comprising: and removing the pseudo fin portions after the second fin portions and the first fin portions are formed and before the isolation layer is formed.
10. The method of forming a semiconductor structure of claim 8, wherein forming an isolation layer in the first recess and the second recess comprises:
forming a first isolation layer in the first groove;
and forming a second isolation layer in the second groove, wherein the density of the second isolation layer is higher than that of the first isolation layer.
11. The method of forming a semiconductor structure of claim 10, wherein the material of the first isolation layer is silicon oxide and the material of the second isolation layer is silicon nitride.
12. The method of claim 5 or 7, wherein the material of the recess protection layer is bottom anti-reflective coating, silicon oxide, silicon nitride or silicon oxynitride.
13. The method of forming a semiconductor structure of claim 1, wherein the first device is a PMOS device and the second device is an NMOS device.
14. A semiconductor structure, comprising:
a substrate comprising a second region for forming a second device and a first region for forming a first device, the second device having a higher power than the first device;
the first region comprises a first substrate and a plurality of first fin parts separated from the first substrate, and first grooves are formed between adjacent first fin parts;
the second region comprises a second substrate and a plurality of second fin parts separated from the second substrate, and second grooves are formed between adjacent second fin parts; the depth of the second groove is smaller than that of the first groove.
15. The semiconductor structure of claim 14, wherein a depth of the second recess is 600 to 900 angstroms.
16. The semiconductor structure of claim 14, wherein a depth of the first recess is 1000 to 1500 angstroms.
17. The semiconductor structure of claim 14, wherein the first device is a PMOS device and the second device is an NMOS device.
18. The semiconductor structure of claim 14, wherein an isolation layer is formed in the first recess and the second recess.
19. The semiconductor structure of claim 18 wherein said isolation layer in said second recess is a second isolation layer and said isolation layer in said first recess is a first isolation layer, said second isolation layer having a higher density than said first isolation layer.
20. The semiconductor structure of claim 19, wherein a material of the first isolation layer is silicon oxide and a material of the second isolation layer is silicon nitride.
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