CN103579074A - Semiconductor structure forming method - Google Patents
Semiconductor structure forming method Download PDFInfo
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- CN103579074A CN103579074A CN201210253734.1A CN201210253734A CN103579074A CN 103579074 A CN103579074 A CN 103579074A CN 201210253734 A CN201210253734 A CN 201210253734A CN 103579074 A CN103579074 A CN 103579074A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000000463 material Substances 0.000 claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 238000005530 etching Methods 0.000 claims abstract description 70
- 238000001020 plasma etching Methods 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims description 48
- 230000015572 biosynthetic process Effects 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 126
- 230000005669 field effect Effects 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure forming method comprises the step of providing a semiconductor substrate provided with a first area and a second area; the step of forming a first material layer covering the surface of the semiconductor substrate; the step of forming a second material layer on the surface of the first material layer in the first area, wherein a stacking structure is formed by the first material layer and the second material layer in the first area; the step of forming mask layers on the stacking structure and the surface of the first material layer in the second area; the step of etching the first material layer through the first plasma etching technology to form a third opening through which the surface of the semiconductor substrate is exposed, and etching the stacking structure by certain thickness to form a plurality of fourth openings; the step of etching the semiconductor substrate through the second plasma etching technology to form first grooves and etching the stacking structure and the semiconductor substrate to form a plurality of second grooves, wherein the depth of the second grooves is smaller than that of the first grooves. The first grooves and the second grooves are formed in the same etching process, and the working process is simple.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of formation method of semiconductor structure.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But the characteristic size (CD when device, while Critical Dimension) further declining, even grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and multiple-grid device is paid close attention to widely as alternative having obtained of conventional device.
Fin formula field effect transistor (Fin FET) is a kind of common multiple-grid device, and Fig. 1 ~ Fig. 4 is the cross-sectional view of existing fin formula field effect transistor forming process.
With reference to figure 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 comprises first area I and second area II; In described Semiconductor substrate 100, form the first hard mask layer 101, the first hard mask layer 101 of second area II has the first opening 102, along Semiconductor substrate 100 described in the first opening 102 etched portions, forms the first groove 103.
With reference to figure 2, at described the first hard mask layer 101(with reference to figure 1) surface forms the first spacer material layer (scheming not shown), described the first spacer material layer is filled full the first opening 102 and the first groove 103(with reference to figure 1); The first spacer material layer and the first hard mask layer 101 described in cmp, take Semiconductor substrate 100 surfaces is stop-layer, forms the first isolation structure 104 in the first groove 103, described the first isolation structure 104 is for isolating adjacent active area.
With reference to figure 3, in described Semiconductor substrate 100, form the second hard mask layer 105, the hard mask layer 105 of first area I has some the second openings 106, along Semiconductor substrate described in described the second opening 106 etchings 100, form some fins 108, between adjacent fin 108 and between fin and Semiconductor substrate 100, there is the second groove 107, the position of the second groove 107 is corresponding with the position of the second opening 106, the degree of depth of the second groove 107 is less than the first groove 103(with reference to figure 1) the degree of depth, follow-uply in the second groove 107, fill the second spacer material layer and form the second isolation structure, for the electrical isolation between adjacent fin.
With reference to figure 4, at described the second hard mask layer 105(with reference to figure 3) the upper second spacer material layer (not shown) that forms, described the second spacer material layer is filled full described the second opening 106 and the second groove 107(with reference to figure 3); The second spacer material layer and the second hard mask layer 105 described in cmp form the second isolation structure 109 in the second groove 107, and described the second isolation structure 109 is for the adjacent fin 108 of electrical isolation.
When existing technique forms the first isolation structure 104 and the second isolation structure 109, the first isolation structure 104 and the second isolation structure 109 and first groove 103 of answering and the second groove 107, all form technical process relative complex in different process step.
More introductions about fin formula field effect transistor please refer to the United States Patent (USP) that publication number is US2011/0068431A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, and technical process is simple.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has the first area second area adjacent with first area; Form the first material layer that covers described semiconductor substrate surface; The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer form stacked structure; The first material surface at stacked structure and second area forms mask layer, and the mask layer of first area has first opening on some exposure stacked structures surface, and the mask layer of second area has the second opening that exposes the first material surface; Adopt the first plasma etch process along the first material layer described in the second opening etching, form to expose the 3rd opening of described semiconductor substrate surface, simultaneously along some the first openings, stacked structure described in etched portions thickness, forms some the 4th openings; Adopt the second plasma etch process along Semiconductor substrate described in the 3rd opening etching, in Semiconductor substrate, form the first groove, simultaneously along stacked structure and Semiconductor substrate described in some the 4th opening etchings, in Semiconductor substrate, form some the second grooves, between adjacent the second groove, be fin, the second depth of groove is less than the degree of depth of the first groove.
Optionally, the material of described the first material layer and the second material layer is not identical, and the first material layer is greater than 1:1 with respect to the etching selection ratio of the second material layer and is less than or equal to 5:1.
Optionally, described Semiconductor substrate is with respect to the etching selection ratio 2:1 ~ 15:1 of the first material layer and the second material layer.
Optionally, the material of described the first material layer is silicon dioxide, and the material of the second material layer is silicon nitride.
Optionally, the thickness of described the first material layer is 20 ~ 100 nanometers, and the thickness of the second material layer is 20 ~ 100 nanometers.
Optionally, the gas of described the first plasma etching industrial employing is CHF
3and Ar, etch chamber pressure is 5 ~ 20 millitorrs, and radio-frequency power is 200 ~ 400 watts, and bias power is 20 ~ 40 watts, and etching temperature is 5 ~ 30 degrees Celsius.
Optionally, the gas of described the second plasma etch process employing is CCl
4and Ar, etch chamber pressure is 5 ~ 20 millitorrs, and radio-frequency power is 500 ~ 700 watts, and bias power is 20 ~ 40 watts, and etching temperature is 5 ~ 30 degrees Celsius.
Optionally, the degree of depth of described the first groove is 100 ~ 500 nanometers.
Optionally, the degree of depth of described the second groove is 50 ~ 300 nanometers.
Optionally, the width of described fin is 10 ~ 50 nanometers, and the distance between adjacent fin is 10 ~ 60 nanometers.
Optionally, also comprise: the opening of the first groove is carried out to circular arc processing.
Optionally, the technique of described circular arcization processing employing is isotropic dry microwave etching power.
Optionally, the frequency of described dry microwave etching technics is 2.3 ~ 2.5 GHzs, and power is 900 ~ 1100 watts, and etching gas is CF
4, O
2and N
2.
Optionally, also comprise: in the first groove and the second groove, fill full isolated material, form the first isolation structure and the second isolation structure.
Optionally, described mask material is photoresist.
Compared with prior art, technical solution of the present invention has the following advantages:
Utilize the first material layer and the second material layer, it in the Semiconductor substrate of first area, is the stacked structure of the first material layer and the second material layer, second area is the single layer structure of the first material layer, the first material layer of the first plasma etching industrial etching second area, while forming the 3rd opening that exposes described semiconductor substrate surface, the stacked structure of the described first area removal segment thickness that only can be etched simultaneously, adopt the second plasma etch process along the described Semiconductor substrate of the 3rd opening etching first area, in Semiconductor substrate, form the first groove, the while remaining stacked structure in etching first area and Semiconductor substrate, in Semiconductor substrate, form some the second grooves, during the second plasma etch process, due to stopping of remaining stacked structure, make the second depth of groove be less than the degree of depth of the first groove, the first groove and the second groove form in same etching technics simultaneously, with respect to existing repeatedly hard mask, etching and photoetching process, technical process is simple.
Further, when the material of described the first material layer and the second material layer is not identical, described the first material layer is less than or equal to 5:1 with respect to the etching selection ratio of the second material layer for being greater than 1:1, when carrying out the first plasma etching, control more accurately the first material layer of first area I and the remaining thickness of stacked structure of the second material layer, thereby when the second plasma etching industrial, control more accurately the interior difference forming between the degree of depth of the second groove and the degree of depth of interior the first groove forming of the Semiconductor substrate of second area II of Semiconductor substrate of first area I.
Further, the opening of the first groove is carried out to circular arc processing, form circular arc opening, when fin formula field effect transistor is worked, the electric charge gathering can be uniformly distributed along the radian of circular arc opening, the density of the electric charge of the Semiconductor substrate inner accumulated of circular arc opening part is less, thereby avoids the generation of leakage current.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of existing fin formula field effect transistor forming process;
Fig. 5 is the schematic flow sheet of the formation method of embodiment of the present invention semiconductor structure;
Fig. 6 ~ Figure 11 is the cross-sectional view of the forming process of semiconductor structure of the present invention.
Embodiment
When existing the first isolation structure in the adjacent active area of making and the second isolation structure between the fin of fin formula field effect transistor, in order to reach the better isolation effect between adjacent active area, the degree of depth of the first groove that the first isolation structure is corresponding is greater than the degree of depth of the second groove that the second isolation structure is corresponding, due to the degree of depth of the first groove and the degree of depth of the second groove different, therefore need twice hard masking process, corresponding photoetching process and twice depositing operation of mask patternization firmly, processing step is comparatively complicated, has increased cost of manufacture.
For addressing the above problem, inventor proposes a kind of formation method of semiconductor structure, utilize the first material layer and the second material layer, it in the Semiconductor substrate of first area, is the stacked structure of the first material layer and the second material layer, second area is the single layer structure of the first material layer, the first material layer of the first plasma etching industrial etching second area, while forming the 3rd opening that exposes described semiconductor substrate surface, the stacked structure of the described first area removal segment thickness that only can be etched simultaneously, adopt the second plasma etch process along the described Semiconductor substrate of the 3rd opening etching first area, in Semiconductor substrate, form the first groove, the while remaining stacked structure in etching first area and Semiconductor substrate, in Semiconductor substrate, form some the second grooves, during the second plasma etch process, due to stopping of remaining stacked structure, make the second depth of groove be less than the degree of depth of the first groove, the first groove and the second groove form in same etching technics simultaneously, with respect to existing repeatedly hard mask, etching and photoetching process, technical process is simple.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
With reference to figure 5, Fig. 5 is the schematic flow sheet of the formation method of embodiment of the present invention semiconductor structure, comprising:
Step S201, provides Semiconductor substrate, and described Semiconductor substrate has the first area second area adjacent with first area;
Step S202, forms the first material layer that covers described semiconductor substrate surface; The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer form stacked structure;
Step S203, at the first material surface formation mask layer of stacked structure and second area, the mask layer of first area has first opening on some exposure stacked structures surface, and the mask layer of second area has the second opening that exposes the first material surface;
Step S204, adopt the first plasma etch process along the first material layer described in the second opening etching, form the 3rd opening that exposes described semiconductor substrate surface, simultaneously along some the first openings, stacked structure described in etched portions thickness, forms some the 4th openings;
Step S205, adopt the second plasma etch process along Semiconductor substrate described in the 3rd opening etching, in Semiconductor substrate, form the first groove, simultaneously along stacked structure and Semiconductor substrate described in some the 4th opening etchings, in Semiconductor substrate, form some the second grooves, between adjacent the second groove, be fin, the second depth of groove is less than the degree of depth of the first groove;
Step S206, carries out circular arc processing to the opening of the first groove;
Step S207 fills full isolated material in the first groove and the second groove, forms the first isolation structure and the second isolation structure.
Fig. 6 ~ Figure 11 is the cross-sectional view of the forming process of semiconductor structure of the present invention.
With reference to figure 6, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 has the adjacent second area II of ⅠHe first area, first area I; Form the first material layer 301 that covers described Semiconductor substrate 300 surfaces; The first material layer 301 surfaces in first area I form the second material layer 302, and the first material layer 301 of first area I and the second material layer 302 form stacked structure.
The material of described Semiconductor substrate 300 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be for other material, such as III-V compounds of group such as GaAs.
The material of Semiconductor substrate described in the present embodiment 300 is monocrystalline silicon, the Semiconductor substrate 300 of first area I is used to form fin formula field effect transistor, the Semiconductor substrate 300 of second area II is used to form the first isolation structure, the first isolation structure, for isolating adjacent active area, prevents that the fin formula field effect transistor forming in adjacent active area is electrically connected to.
Described the first material layer 301 and the second material layer 302 are when subsequent etching, for controlling the first groove of Semiconductor substrate 300 formation and the degree of depth of the second groove, make the degree of depth of the first groove and the second groove different, due to the first groove of subsequent etching and the degree of depth of the second groove darker, when the photoresist layer as mask layer consumes, mask when the first material layer 301 and all right conduct of the second material layer 302 continue etching.
The material of described the first material layer 301 and the second material layer 302 is not identical, described the first material layer is less than or equal to 5:1 with respect to the etching selection ratio of the second material layer for being greater than 1:1, when carrying out the first plasma etching, control more accurately the first material layer 301 of first area I and the remaining thickness of stacked structure of the second material layer 302, thereby when the second plasma etching industrial, control more accurately the interior difference forming between the degree of depth of the second groove and the degree of depth of interior the first groove forming of the Semiconductor substrate of second area II of Semiconductor substrate of first area I.
Described Semiconductor substrate is with respect to the etching selection ratio 2:1 ~ 15:1 of the first material layer and the second material layer, when therefore the second plasma etch process starts the Semiconductor substrate 300 of etching first area I, the groove that the etching of second area II forms has had certain degree of depth, and this degree of depth is greater than the remaining thickness of stacked structure, thereby make the final degree of depth that forms the second groove in the Semiconductor substrate of first area I be less than the degree of depth of the first groove forming in the Semiconductor substrate of second area II.
In the present embodiment, the material of the first material layer 301 is silica, the material of the second material layer 302 is silicon nitride, the thickness of the first material layer 301 is 20 ~ 100 nanometers, the thickness of the second material layer is 20 ~ 100 nanometers, when the first plasma etching, the first material layer 301 of first area I and the stacked structure of the second material layer 302 remain enough thickness, thereby when the second plasma etching, the degree of depth that makes to form the second groove in the Semiconductor substrate of first area I is less than the degree of depth of the first groove forming in the Semiconductor substrate of second area II, and make the difference of the first depth of groove and the second depth of groove be more than or equal to 50 nanometers.
The formation technique of the first material layer 301 is thermal oxidation technology or chemical vapor deposition method, and the formation technique of the second material layer 302 is chemical vapor deposition method.
With reference to figure 7, the first material layer 301 surfaces in stacked structure and second area II form mask layer 303, the mask layer 303 of first area I has first opening 304 on some exposure stacked structures surface, and the mask layer 303 of second area II has the second opening 305 that exposes the first material layer 301 surfaces.The position of the first opening 304 is corresponding with the position of the second groove of the follow-up Semiconductor substrate 300 interior formation in first area I, and the second opening 305 is corresponding with the position of the first groove of the follow-up Semiconductor substrate 300 interior formation in second area II.
The material of described mask layer 303 is photoresist layer, by exposure and developing process, forms the first opening 304 and the second opening 305 in mask layer 303.
With reference to figure 8, adopt the first plasma etch process along the first material layer 301 described in the second opening 305 etchings, form the 3rd opening 306 that exposes described semiconductor substrate surface 300, simultaneously along some the first openings 304, stacked structure described in etched portions thickness, forms some the 4th openings 307.
The gas that described the first plasma etching industrial adopts is CHF
3and Ar, etch chamber pressure is 5 ~ 20 millitorrs, radio-frequency power is 200 ~ 400 watts, bias power is 20 ~ 40 watts, etching temperature is 5 ~ 30 degrees Celsius, by regulating etching temperature, make the first material layer 301 there is different etching selection ratio with respect to the second material layer 302, described the first material layer 301 is greater than 1:1 with respect to the etching selection ratio of the second material layer 302 and is less than or equal to 5:1, when forming the 3rd opening 306, can control very accurately the degree of depth of the 4th opening 307, make the degree of depth of the 4th opening 307 can be less than the thickness of the second material layer 302, also can equal the thickness of the second material layer 302, can also be greater than the thickness of the second material layer 302, can control accurately the thickness of the 4th opening 307 remaining stacked structures in bottom, the depth difference of the 4th thickness of the opening 307 remaining stacked structures in bottom and the first groove of follow-up formation and the second groove is directly relevant, the thickness of remaining stacked structure is thicker, the depth difference of the first groove and the second groove is larger, the thickness of remaining stacked structure is thinner, the depth difference of the first groove and the second groove is less, thereby can control accurately the depth difference of the first groove and the second groove, to improve the performance of the semiconductor structure forming.In the present embodiment, the degree of depth of described the 4th opening 307 equals the thickness of the second material layer.
With reference to figure 9, adopt the second plasma etch process along Semiconductor substrate 300 described in the 3rd opening 306 etchings, in Semiconductor substrate, form the first groove 308, simultaneously along stacked structure and Semiconductor substrate 300 described in some the 4th opening 307 etchings, in Semiconductor substrate 300, form some the second grooves 309, between adjacent the second groove 309, be fin, second groove 309 degree of depth are less than the degree of depth of the first groove 308.
Because the 4th opening 307 bottoms also have the stacked structure of segment thickness, when the Semiconductor substrate 300 of the second plasma etch process etching second area II, stacked structure that simultaneously can the remaining segment thickness of etching first area I, stacked structure at the complete remaining segment thickness of etching, while exposing the Semiconductor substrate 300 of first area I, in the Semiconductor substrate 300 of second area II, formed the groove of certain depth, then continue the Semiconductor substrate 300 of etching first area I and second area II, until at interior formation the second groove 309 of first area I Semiconductor substrate 300, interior formation the first groove 308 of Semiconductor substrate 300 in second area II, the degree of depth of the second groove 309 is less than the degree of depth of the first groove 308.Follow-uply in the first groove 308, fill isolated material and form the first isolation structure, the first isolation structure is for isolating adjacent active area, in the second groove 309, fill isolated material and form the second isolation structure, the second isolation structure is for isolation and the grid of fin formula field effect transistor and the isolation between Semiconductor substrate 300 between adjacent fin, the degree of depth of the first isolation structure is greater than the degree of depth of the second isolation structure, better to isolate adjacent active area.
The gas that described the second plasma etch process adopts is CCl
4and Ar, etch chamber pressure is 5 ~ 20 millitorrs, radio-frequency power is 500 ~ 700 watts, bias power is 20 ~ 40 watts, etching temperature is 5 ~ 30 degrees Celsius, by regulate etching temperature can so that Semiconductor substrate with respect to the etching selection ratio 2:1 ~ 15:1 of the first material and the second material, in the situation that the thickness of the 4th opening 307 remaining stacked structures in bottom is certain, can regulate the depth difference of the first groove 308 and the second groove 309, and with the size of the thickness of the 4th opening 307 remaining stacked structures in bottom, thereby control accurately the depth difference of the first groove 308 and the second groove 309.
The degree of depth of described the first groove 309 is 100 ~ 500 nanometers, and the degree of depth of the second groove 308 is 50 ~ 300 nanometers, and the width of the fin between adjacent the second groove 308 is 10 ~ 50 nanometers, and the distance between adjacent fin is 10 ~ 60 nanometers.
With reference to Figure 10, at the second material surface 302 formation photoresist layers 310 of first area I, described photoresist layer 310 is filled the first openings, the 4th opening, the second groove; The first groove 308(in the Semiconductor substrate 300 of described second area II be please refer to Fig. 9) opening carry out circular arc processing, form first groove 314 with circular arc opening 311.
When the opening of the first groove 308 is right angle opening, when fin formula field effect transistor is worked, electric charge can be collected in the Semiconductor substrate at place, right angle, the density of electric charge is larger, during follow-up formation the first isolation structure, the electric charge that the first groove 308 opening two ends are gathered easily forms leakage current by the surface of the first isolation structure between adjacent active area, the effect of the electrical isolation of the first isolation structure is weakened, the opening of the first groove 308 is carried out to circular arc processing, form circular arc opening 311, when fin formula field effect transistor is worked, the electric charge gathering can be uniformly distributed along the radian of circular arc opening 311, the density of the electric charge of the Semiconductor substrate inner accumulated at circular arc opening 311 places is less, thereby avoid the generation of leakage current.
It is isotropic dry microwave etching power that described circular arcization is processed the technique adopting, and the frequency of dry microwave etching technics is 2.3 ~ 2.5 GHzs, and power is 900 ~ 1100 watts, and etching gas is CF
4, O
2and N
2, to control preferably the radian of opening, the electric charge that opening part is gathered is more even.
With reference to Figure 11, remove photoresist layer 310(and please refer to Figure 10); Form to cover described the second material layer 302(and please refer to Figure 10) and the first material layer 301(please refer to Figure 10) spacer material layer on surface, isolated material is filled completely the first groove and the second groove; Spacer material layer, the second material layer 302 and the first material layer 301 described in cmp, take semiconductor substrate surface 300 as stop-layer, at interior formation second isolation structure 312 of Semiconductor substrate 300 of first area I, at interior formation first isolation structure 313 of Semiconductor substrate 300 of second area.
The degree of depth of the second isolation structure 312 is less than the degree of depth of the first isolation structure 313, the second isolation structure 313 is for the grid of the fin formula field effect transistor of the isolation between fin and follow-up formation and the electrical isolation between Semiconductor substrate 300, and the first isolation structure 313 is for the electrical isolation between active area.
After forming the first isolation structure 313 and the second isolation structure 312, also comprise: return described second isolation structure 312 of etched portions thickness, the fin of expose portion height; Formation is across the grid structure of described some fins, and described grid structure comprises the gate oxide that is positioned at fin surface and sidewall and the gate electrode that is positioned at gate oxide surface; At fin two ends, form the source/drain region of fin formula field effect transistor.
To sum up, the formation method of the semiconductor structure that the embodiment of the present invention provides, utilize the first material layer and the second material layer, it in the Semiconductor substrate of first area, is the stacked structure of the first material layer and the second material layer, second area is the single layer structure of the first material layer, the first material layer of the first plasma etching industrial etching second area, while forming the 3rd opening that exposes described semiconductor substrate surface, the stacked structure of the described first area removal segment thickness that only can be etched simultaneously, adopt the second plasma etch process along the described Semiconductor substrate of the 3rd opening etching first area, in Semiconductor substrate, form the first groove, the while remaining stacked structure in etching first area and Semiconductor substrate, in Semiconductor substrate, form some the second grooves, during the second plasma etch process, due to stopping of remaining stacked structure, make the second depth of groove be less than the degree of depth of the first groove, the first groove and the second groove form in same etching technics simultaneously, with respect to existing repeatedly hard mask, etching and photoetching process, technical process is simple.
Further, when the material of described the first material layer and the second material layer is not identical, described the first material layer is less than or equal to 5:1 with respect to the etching selection ratio of the second material layer for being greater than 1:1, when carrying out the first plasma etching, control more accurately the first material layer of first area I and the remaining thickness of stacked structure of the second material layer, thereby when the second plasma etching industrial, control more accurately the interior difference forming between the degree of depth of the second groove and the degree of depth of interior the first groove forming of the Semiconductor substrate of second area of Semiconductor substrate of first area.
Further, the opening of the first groove is carried out to circular arc processing, form circular arc opening, when fin formula field effect transistor is worked, the electric charge gathering can be uniformly distributed along the radian of circular arc opening, the density of the electric charge of the Semiconductor substrate inner accumulated of circular arc opening part is less, thereby avoids the generation of leakage current.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (16)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has the first area second area adjacent with first area;
Form the first material layer that covers described semiconductor substrate surface;
The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer form stacked structure;
The first material surface at stacked structure and second area forms mask layer, and the mask layer of first area has first opening on some exposure stacked structures surface, and the mask layer of second area has the second opening that exposes the first material surface;
Adopt the first plasma etch process along the first material layer described in the second opening etching, form to expose the 3rd opening of described semiconductor substrate surface, simultaneously along some the first openings, stacked structure described in etched portions thickness, forms some the 4th openings;
Adopt the second plasma etch process along Semiconductor substrate described in the 3rd opening etching, in Semiconductor substrate, form the first groove, simultaneously along stacked structure and Semiconductor substrate described in some the 4th opening etchings, in Semiconductor substrate, form some the second grooves, between adjacent the second groove, be fin, the second depth of groove is less than the degree of depth of the first groove.
2. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the material of described the first material layer and the second material layer is not identical, and the first material layer is greater than 1:1 with respect to the etching selection ratio of the second material layer and is less than or equal to 5:1.
3. the formation method of semiconductor structure as claimed in claim 2, is characterized in that, described Semiconductor substrate is with respect to the etching selection ratio 2:1 ~ 15:1 of the first material layer and the second material layer.
4. the formation method of semiconductor structure as claimed in claim 2, is characterized in that, the material of described the first material layer is silicon dioxide, and the material of the second material layer is silicon nitride.
5. the formation method of semiconductor structure as claimed in claim 4, is characterized in that, the thickness of described the first material layer is 20 ~ 100 nanometers, and the thickness of the second material layer is 20 ~ 100 nanometers.
6. the formation method of the semiconductor structure as described in claim 3 or 4, is characterized in that, the gas that described the first plasma etching industrial adopts is CHF
3and Ar, etch chamber pressure is 5 ~ 20 millitorrs, and radio-frequency power is 200 ~ 400 watts, and bias power is 20 ~ 40 watts, and etching temperature is 5 ~ 30 degrees Celsius.
7. the formation method of the semiconductor structure as described in claim 3 or 4, is characterized in that, the gas that described the second plasma etch process adopts is CCl
4and Ar, etch chamber pressure is 5 ~ 20 millitorrs, and radio-frequency power is 500 ~ 700 watts, and bias power is 20 ~ 40 watts, and etching temperature is 5 ~ 30 degrees Celsius.
8. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the degree of depth of described the first groove is 100 ~ 500 nanometers.
9. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the degree of depth of described the second groove is 50 ~ 300 nanometers.
10. the formation method of semiconductor structure as claimed in claim 8 or 9, is characterized in that, the difference of described the first depth of groove and the second depth of groove is more than or equal to 50 nanometers.
The formation method of 11. semiconductor structures as claimed in claim 1, is characterized in that, the width of described fin is 10 ~ 50 nanometers, and the distance between adjacent fin is 10 ~ 60 nanometers.
The formation method of 12. semiconductor structures as claimed in claim 1, is characterized in that, also comprises: the opening of the first groove is carried out to circular arc processing.
The formation method of 13. semiconductor structures as claimed in claim 12, is characterized in that, it is isotropic dry microwave etching power that described circular arcization is processed the technique adopting.
The formation method of 14. semiconductor structures as claimed in claim 13, is characterized in that, the frequency of described dry microwave etching technics is 2.3 ~ 2.5 GHzs, and power is 900 ~ 1100 watts, and etching gas is CF
4, O
2and N
2.
The formation method of 15. semiconductor structures as claimed in claim 1, is characterized in that, also comprises: in the first groove and the second groove, fill full isolated material, form the first isolation structure and the second isolation structure.
The formation method of 16. semiconductor structures as claimed in claim 1, is characterized in that, described mask material is photoresist.
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| CN105655286A (en) * | 2016-02-04 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor structure |
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| CN110416151A (en) * | 2019-06-06 | 2019-11-05 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
| CN110875186A (en) * | 2018-08-31 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN111295742B (en) * | 2017-12-22 | 2024-05-03 | 德州仪器公司 | Selective etching for reducing taper formation in shallow trench isolation |
| CN110875186A (en) * | 2018-08-31 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110875186B (en) * | 2018-08-31 | 2023-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| FR3102296A1 (en) * | 2019-10-16 | 2021-04-23 | Stmicroelectronics (Rousset) Sas | Integrated circuit manufacturing method comprising a phase of forming trenches in a substrate and corresponding integrated circuit. |
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| CN112992899A (en) * | 2021-02-08 | 2021-06-18 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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