CN103579074B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN103579074B CN103579074B CN201210253734.1A CN201210253734A CN103579074B CN 103579074 B CN103579074 B CN 103579074B CN 201210253734 A CN201210253734 A CN 201210253734A CN 103579074 B CN103579074 B CN 103579074B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 238000000034 method Methods 0.000 title claims abstract description 87
- 239000000463 material Substances 0.000 claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 238000005530 etching Methods 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims description 43
- 238000001020 plasma etching Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VZGDMQKNWNREIO-UHFFFAOYSA-N carbon tetrachloride Substances ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 126
- 230000005669 field effect Effects 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of forming method of semiconductor structure, including: providing Semiconductor substrate, described Semiconductor substrate has first area and second area；Form the first material layer covering described semiconductor substrate surface；The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer constitute stacked structure；The first material surface at stacked structure and second area forms mask layer；Adopting the first plasma etch process to etch described first material layer, form the 3rd opening exposing described semiconductor substrate surface, stacked structure described in etching segment thickness, forms some 4th openings simultaneously；Adopting the second plasma etch process to etch described Semiconductor substrate, form the first groove, etch described stacked structure and Semiconductor substrate simultaneously, form some second grooves, the second depth of groove is less than the degree of depth of the first groove.First groove and the same etch step of the second groove are formed, and technical process is simple.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly to the forming method of a kind of semiconductor structure.
Background technology
Along with the development of semiconductor process technique, process node is gradually reduced, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But the characteristic size (CD when device, when CriticalDimension) declining further, even if grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and multi-gate device obtains as the replacement of conventional device and pays close attention to widely.
Fin formula field effect transistor (FinFET) is a kind of common multi-gate device, and Fig. 1 ~ Fig. 4 is the cross-sectional view of existing fin formula field effect transistor forming process.
With reference to Fig. 1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 includes first area I and second area II；Forming the first hard mask layer 101 in described Semiconductor substrate 100, the first hard mask layer 101 of second area II has the first opening 102, along Semiconductor substrate 100 described in the first opening 102 etched portions, forms the first groove 103.
With reference to Fig. 2, at described first hard mask layer 101(with reference to Fig. 1) surface forms the first spacer material layer (not shown go out), described first spacer material layer fills full first opening 102 and the first groove 103(with reference to Fig. 1)；First spacer material layer described in cmp and the first hard mask layer 101, with Semiconductor substrate 100 surface for stop-layer, form the first isolation structure 104 in the first groove 103, and described first isolation structure 104 is for isolating adjacent active area.
With reference to Fig. 3, described Semiconductor substrate 100 is formed the second hard mask layer 105, the hard mask layer 105 of first area I has some second openings 106, etch described Semiconductor substrate 100 along described second opening 106 and form some fins 108, there is between adjacent fin 108 and between fin and Semiconductor substrate 100 second groove 107, the position of the second groove 107 is corresponding with the position of the second opening 106, the degree of depth of the second groove 107 less than the first groove 103(with reference to Fig. 1) the degree of depth, follow-up in the second groove 107, fill the second spacer material layer form the second isolation structure, for electrically isolating between adjacent fin.
With reference to Fig. 4, at described second hard mask layer 105(with reference to Fig. 3) the upper second spacer material layer (not shown) that formed, described second spacer material layer fills full described second opening 106 and the second groove 107(with reference to Fig. 3)；Second spacer material layer described in cmp and the second hard mask layer 105, form the second isolation structure 109 in the second groove 107, and described second isolation structure 109 is for electrically isolating adjacent fin 108.
When existing technique forms the first isolation structure 104 and the second isolation structure 109, the first isolation structure 104 and the second isolation structure 109 and the first groove 103 and the second groove 107 answered thereof, all formed in different process step, technical process relative complex.
More introductions about fin formula field effect transistor refer to the United States Patent (USP) that publication number is US2011/0068431A1.
Summary of the invention
The problem that this invention address that is to provide the forming method of a kind of semiconductor structure, and technical process is simple.
For solving the problems referred to above, the invention provides the forming method of a kind of semiconductor structure, including:
Thering is provided Semiconductor substrate, described Semiconductor substrate has the adjacent second area in first area and first area；Form the first material layer covering described semiconductor substrate surface；The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer constitute stacked structure；The first material surface at stacked structure and second area forms mask layer, and the mask layer of first area has first opening on some exposure stacked structure surfaces, and the mask layer of second area has the second opening exposing the first material surface；Adopt the first plasma etch process to etch described first material layer along the second opening, form the 3rd opening exposing described semiconductor substrate surface, simultaneously along some first openings, stacked structure described in etched portions thickness, form some 4th openings；The second plasma etch process is adopted to etch described Semiconductor substrate along the 3rd opening, form the first groove in the semiconductor substrate, etch described stacked structure and Semiconductor substrate along some 4th openings simultaneously, form some second grooves in the semiconductor substrate, being fin between adjacent second groove, the second depth of groove is less than the degree of depth of the first groove.
Optionally, the material of described first material layer and the second material layer differs, the first material layer relative to the etching selection ratio of the second material layer more than 1:1 less than or equal to 5:1.
Optionally, described Semiconductor substrate is relative to the etching selection ratio 2:1 ~ 15:1 of the first material layer and the second material layer.
Optionally, the material of described first material layer is silicon dioxide, and the material of the second material layer is silicon nitride.
Optionally, the thickness of described first material layer is 20 ~ 100 nanometers, and the thickness of the second material layer is 20 ~ 100 nanometers.
Optionally, the gas that described first plasma etching industrial adopts is CHF3And Ar, etch chamber pressure is 5 ~ 20 millitorrs, and radio-frequency power is 200 ~ 400 watts, and bias power is 20 ~ 40 watts, and etching temperature is 5 ~ 30 degrees Celsius.
Optionally, the gas that described second plasma etch process adopts is CCl4And Ar, etch chamber pressure is 5 ~ 20 millitorrs, and radio-frequency power is 500 ~ 700 watts, and bias power is 20 ~ 40 watts, and etching temperature is 5 ~ 30 degrees Celsius.
Optionally, the degree of depth of described first groove is 100 ~ 500 nanometers.
Optionally, the degree of depth of described second groove is 50 ~ 300 nanometers.
Optionally, the width of described fin is 10 ~ 50 nanometers, and the distance between adjacent fin is 10 ~ 60 nanometers.
Optionally, also include: the opening of the first groove is carried out radiused process.
Optionally, the described radiused technique adopted that processes is isotropic dry microwave etching power.
Optionally, the frequency of described dry microwave etching technics is 2.3 ~ 2.5 GHzs, and power is 900 ~ 1100 watts, and etching gas is CF4、O2And N2。
Optionally, also include: in the first groove and the second groove, fill full isolated material, form the first isolation structure and the second isolation structure.
Optionally, described mask material is photoresist.
Compared with prior art, technical solution of the present invention has the advantage that
nullUtilize the first material layer and the second material layer，It the Semiconductor substrate of first area is the stacked structure of the first material layer and the second material layer，Second area is the single layer structure of the first material layer，First material layer of the first plasma etching industrial etching second area，When forming three opening exposing described semiconductor substrate surface，The stacked structure of described first area only can be etched removal segment thickness simultaneously，The second plasma etch process is adopted to etch the described Semiconductor substrate of first area along the 3rd opening，Form the first groove in the semiconductor substrate，The etching remaining stacked structure in first area and Semiconductor substrate simultaneously，Form some second grooves in the semiconductor substrate，During the second plasma etch process，Stop due to remaining stacked structure，Make second depth of groove degree of depth less than the first groove，First groove and the second groove concurrently form in same etching technics，Relative to existing repeatedly hard mask、Etching and photoetching process，Technical process is simple.
Further, when the material of described first material layer and the second material layer differs, described first material layer is less than or equal to 5:1 more than 1:1 relative to the etching selection ratio of the second material layer, when carrying out the first plasma etching, first material layer of accurate control first area I and the remaining thickness of stacked structure of the second material layer, thus when the second plasma etching industrial, forming the difference between the degree of depth of the first groove formed in the degree of depth of the second groove and the Semiconductor substrate of second area II in the Semiconductor substrate of accurate control first area I.
Further, the opening of the first groove is carried out radiused process, form circular arc opening, when fin formula field effect transistor works, the electric charge gathered can be uniformly distributed along the radian of circular arc opening, the density of the electric charge of the Semiconductor substrate inner accumulated of circular arc opening part is less, thus avoiding the generation of leakage current.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of existing fin formula field effect transistor forming process；
Fig. 5 is the schematic flow sheet of the forming method of embodiment of the present invention semiconductor structure；
Fig. 6 ~ Figure 11 is the cross-sectional view of the forming process of semiconductor structure of the present invention.
Detailed description of the invention
Existing make adjacent active regions the first isolation structure and the fin of fin formula field effect transistor between the second isolation structure time, in order to reach the better isolation effect between adjacent active regions, the degree of depth of the first groove that the first isolation structure is corresponding is greater than the degree of depth of the second groove corresponding to the second isolation structure, owing to the degree of depth of the first groove and the degree of depth of the second groove are different, it is thus desirable to photoetching process corresponding to twice hard masking process, hard mask patternization and twice depositing operation, processing step is complex, adds cost of manufacture.
nullFor solving the problems referred to above，Inventors suggest that the forming method of a kind of semiconductor structure，Utilize the first material layer and the second material layer，It the Semiconductor substrate of first area is the stacked structure of the first material layer and the second material layer，Second area is the single layer structure of the first material layer，First material layer of the first plasma etching industrial etching second area，When forming three opening exposing described semiconductor substrate surface，The stacked structure of described first area only can be etched removal segment thickness simultaneously，The second plasma etch process is adopted to etch the described Semiconductor substrate of first area along the 3rd opening，Form the first groove in the semiconductor substrate，The etching remaining stacked structure in first area and Semiconductor substrate simultaneously，Form some second grooves in the semiconductor substrate，During the second plasma etch process，Stop due to remaining stacked structure，Make second depth of groove degree of depth less than the first groove，First groove and the second groove concurrently form in same etching technics，Relative to existing repeatedly hard mask、Etching and photoetching process，Technical process is simple.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
With reference to the schematic flow sheet of the forming method that Fig. 5, Fig. 5 are embodiment of the present invention semiconductor structure, including:
Step S201, it is provided that Semiconductor substrate, described Semiconductor substrate has the adjacent second area in first area and first area；
Step S202, forms the first material layer covering described semiconductor substrate surface；The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer constitute stacked structure；
Step S203, the first material surface at stacked structure and second area forms mask layer, and the mask layer of first area has first opening on some exposure stacked structure surfaces, and the mask layer of second area has the second opening exposing the first material surface；
Step S204, adopts the first plasma etch process to etch described first material layer along the second opening, forms the 3rd opening exposing described semiconductor substrate surface, simultaneously along some first openings, stacked structure described in etched portions thickness, form some 4th openings；
Step S205, the second plasma etch process is adopted to etch described Semiconductor substrate along the 3rd opening, form the first groove in the semiconductor substrate, etch described stacked structure and Semiconductor substrate along some 4th openings simultaneously, form some second grooves in the semiconductor substrate, being fin between adjacent second groove, the second depth of groove is less than the degree of depth of the first groove；
Step S206, carries out radiused process to the opening of the first groove；
Step S207, fills full isolated material in the first groove and the second groove, forms the first isolation structure and the second isolation structure.
Fig. 6 ~ Figure 11 is the cross-sectional view of the forming process of semiconductor structure of the present invention.
With reference to Fig. 6, it is provided that Semiconductor substrate 300, described Semiconductor substrate 300 has the adjacent second area II in first area I and first area I；Form the first material layer 301 covering described Semiconductor substrate 300 surface；Forming the second material layer 302 on the first material layer 301 surface of first area I, the first material layer 301 of first area I and the second material layer 302 constitute stacked structure.
The material of described Semiconductor substrate 300 can be monocrystal silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC)；Can also be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be other material, for instance GaAs etc. III-V compounds of group.
The material of Semiconductor substrate 300 described in the present embodiment is monocrystal silicon, the Semiconductor substrate 300 of first area I is used for forming fin formula field effect transistor, the Semiconductor substrate 300 of second area II is used for forming the first isolation structure, first isolation structure is for isolating adjacent active area, it is prevented that the fin formula field effect transistor electrical connection formed in adjacent active regions.
Described first material layer 301 and the second material layer 302 are when subsequent etching, for controlling the degree of depth of the first groove and the second groove formed in Semiconductor substrate 300, the degree of depth making the first groove and the second groove is different, owing to the first groove of subsequent etching and the degree of depth of the second groove are deeper, when the photoresist layer as mask layer consumes, the first material layer 301 and the second material layer 302 are also used as continuing mask during etching.
The material of described first material layer 301 and the second material layer 302 differs, described first material layer is less than or equal to 5:1 more than 1:1 relative to the etching selection ratio of the second material layer, when carrying out the first plasma etching, first material layer 301 of accurate control first area I and the remaining thickness of stacked structure of the second material layer 302, thus when the second plasma etching industrial, forming the difference between the degree of depth of the first groove formed in the degree of depth of the second groove and the Semiconductor substrate of second area II in the Semiconductor substrate of accurate control first area I.
Described Semiconductor substrate is relative to the etching selection ratio 2:1 ~ 15:1 of the first material layer and the second material layer, therefore when the second plasma etch process starts the Semiconductor substrate 300 etching first area I, the groove that the etching of second area II is formed has had certain degree of depth, and this degree of depth is greater than the remaining thickness of stacked structure, so that finally forming the degree of depth degree of depth less than the first groove formed in the Semiconductor substrate of second area II of the second groove in the Semiconductor substrate of first area I.
In the present embodiment, the material of the first material layer 301 is silicon oxide, the material of the second material layer 302 is silicon nitride, the thickness of the first material layer 301 is 20 ~ 100 nanometers, the thickness of the second material layer is 20 ~ 100 nanometers, when the first plasma etching, first material layer 301 of first area I and the stacked structure of the second material layer 302 remain enough thickness, thus when the second plasma etching, make the degree of depth forming the second groove in the Semiconductor substrate of first area I degree of depth less than the first groove formed in the Semiconductor substrate of second area II, and make first depth of groove difference with the second depth of groove be more than or equal to 50 nanometers.
The formation process of the first material layer 301 is thermal oxidation technology or chemical vapor deposition method, and the formation process of the second material layer 302 is chemical vapor deposition method.
With reference to Fig. 7, mask layer 303 is formed on the first material layer 301 surface of stacked structure and second area II, the mask layer 303 of first area I has first opening 304 on some exposure stacked structure surfaces, and the mask layer 303 of second area II has the second opening 305 exposing the first material layer 301 surface.The position of the first opening 304 is corresponding with the position of follow-up the second groove formed in the Semiconductor substrate 300 of first area I, and the second opening 305 is corresponding with the position of follow-up the first groove formed in the Semiconductor substrate 300 of second area II.
The material of described mask layer 303 is photoresist layer, forms the first opening 304 and the second opening 305 by exposed and developed technique in mask layer 303.
With reference to Fig. 8, adopt the first plasma etch process to etch described first material layer 301 along the second opening 305, form the 3rd opening 306 exposing described semiconductor substrate surface 300, simultaneously along some first openings 304, stacked structure described in etched portions thickness, forms some 4th openings 307.
The gas that described first plasma etching industrial adopts is CHF3nullAnd Ar，Etch chamber pressure is 5 ~ 20 millitorrs，Radio-frequency power is 200 ~ 400 watts，Bias power is 20 ~ 40 watts，Etching temperature is 5 ~ 30 degrees Celsius，By regulating etching temperature，The first material layer 301 is made to have different etching selection ratio relative to the second material layer 302，Described first material layer 301 relative to the etching selection ratio of the second material layer 302 more than 1:1 less than or equal to 5:1，When forming three openings 306，The degree of depth of the 4th opening 307 can be controlled very accurately，The degree of depth making the 4th opening 307 can less than the thickness of the second material layer 302，The thickness of the second material layer 302 can also be equal to，Can also more than the thickness of the second material layer 302，Namely the thickness of remaining stacked structure bottom the 4th opening 307 can be controlled accurately，Bottom 4th opening 307, the thickness of remaining stacked structure is directly relevant with the depth difference of the first groove being subsequently formed and the second groove，The thickness of remaining stacked structure is more thick，The depth difference of the first groove and the second groove is more big，The thickness of remaining stacked structure is more thin，The depth difference of the first groove and the second groove is more little，Such that it is able to control the first groove and the depth difference of the second groove accurately，To improve the performance of the semiconductor structure formed.In the present embodiment, the degree of depth of described 4th opening 307 is equal to the thickness of the second material layer.
With reference to Fig. 9, the second plasma etch process is adopted to etch described Semiconductor substrate 300 along the 3rd opening 306, form the first groove 308 in the semiconductor substrate, etch described stacked structure and Semiconductor substrate 300 along some 4th openings 307 simultaneously, Semiconductor substrate 300 is formed some second grooves 309, being fin between adjacent second groove 309, second groove 309 degree of depth is less than the degree of depth of the first groove 308.
Owing to also having the stacked structure of segment thickness bottom the 4th opening 307, when the second plasma etch process etches the Semiconductor substrate 300 of second area II, the stacked structure of the remaining segment thickness in first area I can be etched simultaneously, at the stacked structure having etched remaining segment thickness, when exposing the Semiconductor substrate 300 of first area I, the groove of certain depth has been formed in the Semiconductor substrate 300 of second area II, then continue to the Semiconductor substrate 300 of etching first area I and second area II, until forming the second groove 309 in first area I Semiconductor substrate 300, the first groove 308 is formed in the Semiconductor substrate 300 of second area II, the degree of depth of the second groove 309 is less than the degree of depth of the first groove 308.Follow-up isolated material of filling in the first groove 308 forms the first isolation structure, first isolation structure is for isolating adjacent active area, second groove 309 is filled isolated material and forms the second isolation structure, second isolation structure is for the isolation between isolation and grid and the Semiconductor substrate 300 of fin formula field effect transistor between adjacent fin, the degree of depth of the first isolation structure is more than the degree of depth of the second isolation structure, better to isolate adjacent active area.
The gas that described second plasma etch process adopts is CCl4And Ar, etch chamber pressure is 5 ~ 20 millitorrs, radio-frequency power is 500 ~ 700 watts, bias power is 20 ~ 40 watts, etching temperature is 5 ~ 30 degrees Celsius, can so that Semiconductor substrate be relative to the etching selection ratio 2:1 ~ 15:1 of the first material and the second material by regulating the temperature of etching, bottom the 4th opening 307, the thickness of remaining stacked structure is certain, the depth difference of the first groove 308 and the second groove 309 can be regulated, and with the 4th opening 307 bottom the size of thickness of remaining stacked structure, thus controlling the depth difference of the first groove 308 and the second groove 309 accurately.
The degree of depth of described first groove 309 is 100 ~ 500 nanometers, and the degree of depth of the second groove 308 is 50 ~ 300 nanometers, and the width of the fin between adjacent second groove 308 is 10 ~ 50 nanometers, and the distance between adjacent fin is 10 ~ 60 nanometers.
With reference to Figure 10, the second material surface 302 in first area I forms photoresist layer 310, and described photoresist layer 310 fills the first opening, the 4th opening, the second groove；The first groove 308(in the Semiconductor substrate 300 of described second area II be refer to Fig. 9) opening carry out radiused process, form first groove 314 with circular arc opening 311.
When the opening of the first groove 308 is always open, when fin formula field effect transistor works, electric charge can be collected in the Semiconductor substrate of right angle, the density of electric charge is bigger, when being subsequently formed the first isolation structure, the electric charge that first groove 308 opening two ends are gathered easily forms leakage current by the surface of the first isolation structure between adjacent active area, make the decreased effectiveness electrically isolated of the first isolation structure, the opening of the first groove 308 is carried out radiused process, form circular arc opening 311, when fin formula field effect transistor works, the electric charge gathered can be uniformly distributed along the radian of circular arc opening 311, the density of the electric charge of the Semiconductor substrate inner accumulated at circular arc opening 311 place is less, thus avoiding the generation of leakage current.
The described radiused technique adopted that processes is isotropic dry microwave etching power, and the frequency of dry microwave etching technics is 2.3 ~ 2.5 GHzs, and power is 900 ~ 1100 watts, and etching gas is CF4、O2And N2, to control the radian of opening preferably, make the electric charge that opening part gathers evenly.
With reference to Figure 11, remove photoresist layer 310(and refer to Figure 10)；Formed and cover described second material layer 302(and refer to Figure 10) and the first material layer 301(refer to Figure 10) spacer material layer on surface, isolated material is filled expires the first groove and the second groove；Spacer material layer, the second material layer 302 and the first material layer 301 described in cmp, with semiconductor substrate surface 300 for stop-layer, in the Semiconductor substrate 300 of first area I, form the second isolation structure 312, in the Semiconductor substrate 300 of second area, form the first isolation structure 313.
The degree of depth of the second isolation structure 312 is less than the degree of depth of the first isolation structure 313, second isolation structure 313 is for electrically isolating between the isolation between fin and grid and the Semiconductor substrate 300 of fin formula field effect transistor that are subsequently formed, and the first isolation structure 313 is for electrically isolating between active area.
After forming the first isolation structure 313 and the second isolation structure 312, also include: be etched back to described second isolation structure 312 of segment thickness, the fin of expose portion height；Being developed across the grid structure of described some fins, described grid structure includes being positioned at the gate oxide of fin portion surface and sidewall and being positioned at the gate electrode on gate oxide surface；The source/drain region of fin formula field effect transistor is formed at fin two ends.
nullTo sum up，The forming method of the semiconductor structure that the embodiment of the present invention provides，Utilize the first material layer and the second material layer，It the Semiconductor substrate of first area is the stacked structure of the first material layer and the second material layer，Second area is the single layer structure of the first material layer，First material layer of the first plasma etching industrial etching second area，When forming three opening exposing described semiconductor substrate surface，The stacked structure of described first area only can be etched removal segment thickness simultaneously，The second plasma etch process is adopted to etch the described Semiconductor substrate of first area along the 3rd opening，Form the first groove in the semiconductor substrate，The etching remaining stacked structure in first area and Semiconductor substrate simultaneously，Form some second grooves in the semiconductor substrate，During the second plasma etch process，Stop due to remaining stacked structure，Make second depth of groove degree of depth less than the first groove，First groove and the second groove concurrently form in same etching technics，Relative to existing repeatedly hard mask、Etching and photoetching process，Technical process is simple.
Further, when the material of described first material layer and the second material layer differs, described first material layer is less than or equal to 5:1 more than 1:1 relative to the etching selection ratio of the second material layer, when carrying out the first plasma etching, first material layer of accurate control first area I and the remaining thickness of stacked structure of the second material layer, thus when the second plasma etching industrial, forming the difference between the degree of depth of the first groove formed in the degree of depth of the second groove and the Semiconductor substrate of second area in the Semiconductor substrate of accurate control first area.
Further, the opening of the first groove is carried out radiused process, form circular arc opening, when fin formula field effect transistor works, the electric charge gathered can be uniformly distributed along the radian of circular arc opening, the density of the electric charge of the Semiconductor substrate inner accumulated of circular arc opening part is less, thus avoiding the generation of leakage current.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (15)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate has the adjacent second area in first area and first area；
Form the first material layer covering described semiconductor substrate surface；
The first material surface in first area forms the second material layer, and the first material layer of first area and the second material layer constitute stacked structure, and the material of described first material layer is silicon dioxide, and the material of the second material layer is silicon nitride；
The first material surface at stacked structure and second area forms mask layer, and the mask layer of first area has first opening on some exposure stacked structure surfaces, and the mask layer of second area has the second opening exposing the first material surface；
Adopt the first plasma etch process to etch described first material layer along the second opening, form the 3rd opening exposing described semiconductor substrate surface, simultaneously along some first openings, stacked structure described in etched portions thickness, form some 4th openings；
The second plasma etch process is adopted to etch described Semiconductor substrate along the 3rd opening, form the first groove in the semiconductor substrate, etch described stacked structure and Semiconductor substrate along some 4th openings simultaneously, form some second grooves in the semiconductor substrate, being fin between adjacent second groove, the second depth of groove is less than the degree of depth of the first groove.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of described first material layer and the second material layer differs, the first material layer relative to the etching selection ratio of the second material layer more than 1:1 less than or equal to 5:1.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that described Semiconductor substrate is relative to the etching selection ratio 2:1～15:1 of the first material layer and the second material layer.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness of described first material layer is 20～100 nanometers, and the thickness of the second material layer is 20～100 nanometers.
5. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that the gas that described first plasma etching industrial adopts is CHF3And Ar, etch chamber pressure is 5～20 millitorrs, and radio-frequency power is 200～400 watts, and bias power is 20～40 watts, and etching temperature is 5～30 degrees Celsius.
6. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that the gas that described second plasma etch process adopts is CCl4And Ar, etch chamber pressure is 5～20 millitorrs, and radio-frequency power is 500～700 watts, and bias power is 20～40 watts, and etching temperature is 5～30 degrees Celsius.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the degree of depth of described first groove is 100～500 nanometers.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the degree of depth of described second groove is 50～300 nanometers.
9. the forming method of semiconductor structure as claimed in claim 7 or 8, it is characterised in that the difference of described first depth of groove and the second depth of groove is be more than or equal to 50 nanometers.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the width of described fin is 10～50 nanometers, and the distance between adjacent fin is 10～60 nanometers.
11. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include: the opening of the first groove is carried out radiused process.
12. the forming method of semiconductor structure as claimed in claim 11, it is characterised in that the described radiused technique adopted that processes is isotropic dry microwave etching power.
13. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that the frequency of described dry microwave etching technics is 2.3～2.5 GHzs, and power is 900～1100 watts, and etching gas is CF4、O2And N2。
14. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include: fill full isolated material in the first groove and the second groove, form the first isolation structure and the second isolation structure.
15. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described mask material is photoresist.
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| CN105655286A (en) * | 2016-02-04 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor structure |
| CN107293491A (en) * | 2016-04-12 | 2017-10-24 | 北大方正集团有限公司 | The preparation method of VDMOS device |
| US10453738B2 (en) | 2017-12-22 | 2019-10-22 | Texas Instruments Incorporated | Selective etches for reducing cone formation in shallow trench isolations |
| CN110875186B (en) * | 2018-08-31 | 2023-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110416151A (en) * | 2019-06-06 | 2019-11-05 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
| CN112420722B (en) * | 2019-08-22 | 2022-06-10 | 长鑫存储技术有限公司 | Embedded grid structure and method for forming semiconductor memory |
| FR3102296A1 (en) * | 2019-10-16 | 2021-04-23 | Stmicroelectronics (Rousset) Sas | Integrated circuit manufacturing method comprising a phase of forming trenches in a substrate and corresponding integrated circuit. |
| CN112992899B (en) * | 2021-02-08 | 2023-02-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN114623777B (en) * | 2022-02-21 | 2022-11-18 | 武汉大学 | Construction method and measurement method of measurement model of stacked nanosheet structure |
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| US4660068A (en) * | 1982-08-24 | 1987-04-21 | Nippon Telegraph & Telephone Corporation | Substrate structure of semiconductor device and method of manufacturing the same |
| CN1606146A (en) * | 2003-10-10 | 2005-04-13 | 旺宏电子股份有限公司 | Methods of simultaneously fabricating isolation structures having varying dimensions |
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| US4660068A (en) * | 1982-08-24 | 1987-04-21 | Nippon Telegraph & Telephone Corporation | Substrate structure of semiconductor device and method of manufacturing the same |
| CN1606146A (en) * | 2003-10-10 | 2005-04-13 | 旺宏电子股份有限公司 | Methods of simultaneously fabricating isolation structures having varying dimensions |
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