CN104425275B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN104425275B CN104425275B CN201310398623.4A CN201310398623A CN104425275B CN 104425275 B CN104425275 B CN 104425275B CN 201310398623 A CN201310398623 A CN 201310398623A CN 104425275 B CN104425275 B CN 104425275B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000000463 material Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000012774 insulation material Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 225
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000004576 sand Substances 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 229910003978 SiClx Inorganic materials 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 3
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 230000005669 field effect Effects 0.000 abstract description 46
- 238000005530 etching Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- -1 ion Ion Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of forming method of semiconductor structure, including：Semiconductor substrate is provided, the Semiconductor substrate has first area and second area；The first pseudo- fin is formed on the first area surface of Semiconductor substrate, the second pseudo- fin is formed on the second area surface of Semiconductor substrate；Insulation material layer is formed in the semiconductor substrate surface, the surface of the insulation material layer is flushed with the top surface of the first pseudo- fin, the second pseudo- fin；The described first pseudo- fin is removed, forms the first groove；The first semi-conducting material is filled in first groove, forms the first fin, the top surface of first fin is flushed with insulation material layer top surface；The described second pseudo- fin is removed, forms the second groove；The second semiconductor material layer is filled in second groove, forms the second fin, the top surface of second fin is flushed with insulation material layer top surface.The above method can form the fin formula field effect transistor with different fin materials, so as to improve the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
With the continuous development of semiconductor process technique, process node is gradually reduced, rear grid（gate-last）Technique obtains
Extensive use to obtain ideal threshold voltage, improves device performance.But when the characteristic size of device further declines
When, even if using rear grid technique, the structure of conventional metal-oxide-semiconductor field effect transistor also can not meet the needs of to device performance, fin
Formula field-effect transistor（Fin FET）Extensive concern has been obtained as a kind of multi-gate device.
Fin formula field effect transistor is a kind of common multi-gate device, and Fig. 1 shows a kind of fin field effect of the prior art
Answer the dimensional structure diagram of transistor.As shown in Figure 1, including：Semiconductor substrate 10 is formed in the Semiconductor substrate 10
The fin 11 of protrusion, fin 11 after being etched to Semiconductor substrate 10 generally by obtaining；Dielectric layer 12, covering is described partly to be led
The surface of body substrate 10 and a part for the side wall of fin 11；Gate structure 13, across on the fin 11, described in covering
The atop part and side wall of fin 11, gate structure 13 include gate dielectric layer（It is not shown in figure）With the grid on gate dielectric layer
Electrode（It is not shown in figure）.For fin formula field effect transistor, the top of fin 11 and the side wall of both sides and gate structure 13
The part being in contact all becomes channel region, i.e., with multiple grid, is conducive to increase driving current, improves device performance.
The performance for the fin formula field effect transistor that the prior art is formed needs further to be improved.
Invention content
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor structure have different fin materials using being formed
The N-type fin formula field effect transistor of material and p-type fin formula field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Semiconductor lining is provided
Bottom, the Semiconductor substrate have first area and second area；The is formed on the first area surface of the Semiconductor substrate
One pseudo- fin forms the second pseudo- fin on the second area surface of the Semiconductor substrate；In the semiconductor substrate surface shape
Into insulation material layer, the surface of the insulation material layer is flushed with the top surface of the first pseudo- fin, the second pseudo- fin；Remove described
One pseudo- fin, forms the first groove；It fills the first semi-conducting material in first groove, forms the first fin, described the
The top surface of one fin is flushed with insulation material layer top surface；The described second pseudo- fin is removed, forms the second groove；It is recessed described second
The second semiconductor material layer of filling in slot, forms the second fin, the top surface of second fin is flushed with insulation material layer top surface.
Optionally, the described first pseudo- fin and the second pseudo- fin are formed using Dual graphing technique or multiple graphical technique
Portion.
Optionally, the method for forming the described first pseudo- fin and the second pseudo- fin includes：In the semiconductor substrate surface
Form sacrificial layer, the mask layer positioned at the sacrificial layer surface, the photoresist layer positioned at the mask layer surface, the photoresist
Layer covering part mask layer；Side wall is formed in the photoresist layer sidewall surfaces, positioned at the side wall position of the photoresist layer side
Above the first area of Semiconductor substrate, the opposite side side wall positioned at the photoresist layer is located at the secondth area of Semiconductor substrate
Above domain；Remove the photoresist layer；Using the side wall as mask, the mask layer and sacrificial layer are etched to Semiconductor substrate table
Face, forms the first pseudo- fin on the first region, and the described first pseudo- fin includes the first part's sacrifice being located on first area
First part's mask layer at the top of layer and first part's sacrificial layer forms the second pseudo- fin on second area surface, described
Second pseudo- fin includes second at the top of second part sacrificial layer and the second part sacrificial layer on second area
Divide mask layer；Remove the side wall.
Optionally, the material of the side wall is one kind in silica, silicon nitride, silicon oxynitride, silicon carbide, fire sand
It is or a variety of；The material of the mask layer is silica, in silicon nitride, silicon oxynitride, silicon carbide, fire sand, amorphous silicon
One or more, the material of mask layer is different from the material of side wall；The material of the sacrificial layer is silica, silicon nitride, nitrogen oxygen
One or more in SiClx, silicon carbide, fire sand, amorphous silicon, the material of the sacrificial layer and the material of mask layer are not
Together.
Optionally, the material of the sacrificial layer is silicon nitride, and the material of the mask layer is amorphous silicon, the side wall
Material is silica.
Optionally, it further includes：After the insulation material layer is formed, in the described first pseudo- fin and the second pseudo- fin top
Portion surface forms protective layer.
Optionally, the method for forming the protective layer is oxidation technology.
Optionally, the described first pseudo- fin is removed, the method for forming the first groove includes：It is rectangular on the second area
It is pseudo- using wet-etching technology removal described first into covering part insulation material layer and the second hard mask layer of the second pseudo- fin
Fin forms the first groove on the first area surface of Semiconductor substrate.
Optionally, the material of second hard mask layer is silicon nitride.
Optionally, the first semi-conducting material is filled in first groove using selective deposition technique.
Optionally, the material of first semi-conducting material is Si, GaAs or GaN.
Optionally, in first fin one kind in P, As, Sb is included at least doped with N-type ion, the N-type ion
Ion.
Optionally, it is doping process in situ to the method that first fin is doped.
Optionally, the described second pseudo- fin is removed, the method for forming the second groove includes：It is rectangular on the first area
Into covering part insulation material layer and the first hard mask layer of the first fin, using the described second pseudo- fin of wet-etching technology removal
Portion forms the second groove on the second area surface of Semiconductor substrate.
Optionally, the material of second hard mask layer is silicon nitride.
Optionally, the second semiconductor material layer is filled in second groove using selective deposition technique.
Optionally, the material of second semiconductor material layer is SiGe or Ge.
Optionally, in second fin one kind in B, Ga, In is included at least doped with p-type ion, the p-type ion
Ion.
Optionally, it is doping process in situ to the method that second fin is doped.
Optionally, it further includes, etches the insulation material layer and form insulating layer, the surface of the insulating layer is less than the first fin
Portion, the top surface of the second fin；Surface of insulating layer on the first area be developed across and the first fin of covering part the
One gate structure；Surface of insulating layer on the second area is developed across and the second grid knot of the second fin of covering part
Structure；The first source/drain is formed in the first fin of the first grid structure both sides；In the second grid structure both sides
The second source/drain is formed in second fin.
Compared with prior art, technical scheme of the present invention has the following advantages：
In technical scheme of the present invention, the first pseudo- fin is formed on the first area of Semiconductor substrate, in second area
It is upper to form the second pseudo- fin and the insulation material layer positioned at semiconductor substrate surface, the described first pseudo- fin is then removed respectively
Portion forms the first groove, and the first semi-conducting material is filled in first groove, forms the first fin；Remove described
Two pseudo- fins, form the second groove, and the second semi-conducting material is filled in first groove, form the second fin.It can be with
According to the type that fin formula field effect transistor to be formed is needed on the first fin and the second fin, using corresponding first semiconductor
Material and the second semi-conducting material form the first fin and the second fin, so as to be formed simultaneously with different fin materials
Fin formula field effect transistor.
Further, first semi-conducting material is Si, GaAs or GaN, first semi-conducting material formed the
The electron mobility of one fin is higher, can improve the performance of N-type fin formula field effect transistor；Second semi-conducting material is
SiGe or Ge, the mobility in the hole in the second fin that second semi-conducting material is formed is higher, can improve p-type fin
The performance of field-effect transistor.
Description of the drawings
Fig. 1 is the structure diagram of the fin formula field effect transistor transistor of the formation of the prior art of the present invention；
Fig. 2 to Figure 13 is the structure diagram of the forming process of the semiconductor structure of the embodiment of the present invention.
Specific embodiment
As described in the background art, the performance for the fin formula field effect transistor that the prior art is formed needs further to be carried
It is high.
The study found that N-type fin formula field effect transistor that the prior art is usually formed and p-type fin formula field effect transistor
Fin divides using identical fin material in the N-type fin formula field effect transistor and p-type fin formula field effect transistor
Migration rate of the not corresponding carrier, that is, electrons and holes in same material is different, this results in the N-type to be formed
The saturation current of fin formula field effect transistor and p-type fin formula field effect transistor differs.With process node further under
Drop, this otherness can be protruded more.The study found that for p-type fin formula field effect transistor, the material of the fin can be
Ge or SiGe can improve the mobility of the holoe carrier in p-type fin formula field effect transistor, so as to improve p-type fin field
The performance of effect transistor；For N-type fin formula field effect transistor, the material of the fin can be Si or GaN, enable to
N-type fin formula field effect transistor has higher electronic carrier mobility, so as to improve the property of N-type fin formula field effect transistor
Energy.How N-type fin formula field effect transistor and p-type fin field effect crystalline substance with different fin materials are formed simultaneously on substrate
Body pipe becomes urgent problem to be solved.
The forming method of the semiconductor structure of the embodiment of the present invention can be formed simultaneously the N with different fin materials
Type fin formula field effect transistor and p-type fin formula field effect transistor can improve the N-type fin formula field effect transistor and p-type
The performance of fin formula field effect transistor.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
It please refers to Fig.2, Semiconductor substrate 100 is provided, the Semiconductor substrate has first area 101 and second area
102。
The Semiconductor substrate 100 can be silicon or silicon-on-insulator（SOI）, the Semiconductor substrate 100 can also
It is germanium, germanium silicon, GaAs or germanium on insulator, the material of Semiconductor substrate 100 described in the present embodiment is silicon.
Different types of fin formula field effect transistor is subsequently respectively formed on the first area 101 and second area 102.
In the present embodiment, N-type fin formula field effect transistor is formed on the first area 101, is formed on the second area 102
P-type fin formula field effect transistor.
It please refers to Fig.3, sacrificial layer 200 is formed on 100 surface of Semiconductor substrate, positioned at 200 surface of sacrificial layer
Mask layer 201.
The material of the mask layer 201 is silica, silicon nitride, silicon oxynitride, silicon carbide, fire sand, amorphous silicon
In it is one or more；The material of the sacrificial layer is silica, silicon nitride, silicon oxynitride, silicon carbide, fire sand, without fixed
One or more in shape silicon, the material of the sacrificial layer is different from the material of mask layer.In the present embodiment, the sacrificial layer
200 material is silicon nitride, and the material of the mask layer 201 is amorphous silicon.
The sacrificial layer 200 and mask layer 201, the sacrificial layer 200 and mask are formed using chemical vapor deposition method
The overall thickness of layer 201 is identical with the first fin and the thickness of the second fin being subsequently formed, and the thickness of the sacrificial layer 200 is
50nm~200nm, the thickness of the mask layer 201 is 10nm~50nm.
It please refers to Fig.4, photoresist layer 300 is formed on 201 surface of mask layer and positioned at the photoresist layer both sides
Side wall 301.
The 300 covering part first area 101 of photoresist layer and the surface of the mask layer 201 on second area 102, institute
The size for stating photoresist layer 300 defines spacing between the first fin and the second fin being subsequently formed.
The material of the side wall 301 is silica, silicon nitride, silicon oxynitride, silicon carbide, one kind in fire sand or more
Kind, the material of the side wall 301 is different from the material of mask layer 201, and in the present embodiment, the material of the side wall 301 is oxidation
Silicon.
The method for forming the side wall 301 includes：Form the side wall material for covering the mask layer 201 and photoresist layer 300
The bed of material carries out the spacer material layer without mask etching, and removal is positioned at 300 top of 201 surface of mask layer and photoresist layer
Part spacer material layer forms the side wall 301 positioned at the 300 both sides sidewall surfaces of photoresist layer.Positioned at the photoresist layer
The side wall 301 of 300 sides is located at 101 top of first area of Semiconductor substrate 100, positioned at the another of the photoresist layer 300
The side wall 301 of side is located at 102 top of second area of Semiconductor substrate 100.
The width of the side wall 201 is 10nm~40nm, and the width of the side wall 301 defines the first fin being subsequently formed
Portion and the width of the second fin.
Fig. 5 is please referred to, removes the photoresist layer 300.
In the present embodiment, the photoresist layer 300 is removed using the plasma ash process containing oxygen, in the present invention
Other embodiment in, wet-etching technology can also be used to remove the photoresist layer 300.
After removing the photoresist layer 300,201 surface of mask layer has discrete side wall 301, the side wall
301 is follow-up as etching mask layer 201 and the mask of sacrificial layer 200.
Fig. 6 is please referred to, with the side wall 301（Please refer to Fig. 5）For mask, the mask layer 201 is etched（Please refer to Fig. 5）
With sacrificial layer 200（Please refer to Fig. 5）To 100 surface of Semiconductor substrate, the first pseudo- fin 231, institute are formed on first area 101
It states the first pseudo- fin 231 and includes the first part's sacrificial layer 211 being located on first area 101 and first part's sacrificial layer
First part's mask layer 221 at 211 tops forms the second pseudo- fin 232, the described second pseudo- fin on 102 surface of second area
232 include the second of 212 top of the second part sacrificial layer 212 being located on second area 102 and the second part sacrificial layer
Then part mask layer 222 removes the side wall 301.
The described first pseudo- pseudo- fin 232 of fin 231 and second is formed using dry etch process, using side wall 301 as quarter
Mask is lost, by 301 pattern transfer of side wall to mask layer 201（Please refer to Fig. 5）After upper, with mask layer 201 for described in mask etching
Sacrificial layer 200（Please refer to Fig. 5）.The mask layer 201 can make the to be formed first pseudo- pseudo- fin 232 of fin 231 and second
Side wall keeps vertical, reduces etching error.
In the present embodiment, the method for the pseudo- fin 232 of the above-mentioned pseudo- fin 231 and second of formation first is double-pattern chemical industry
Skill in other embodiments of the invention, can also form the described first pseudo- fin and the second puppet using multiple graphical technique
Fin.The adjacent spacing that can be obtained using Dual graphing technique or multiple graphical technique is smaller, and width smaller first is pseudo-
Fin and the second pseudo- fin.
In other embodiments of the invention, can also the sacrificial layer surface directly formed Patterned masking layer it
Afterwards, the sacrificial layer is etched, forms the first pseudo- fin and the second pseudo- fin.
Fig. 7 is please referred to, insulation material layer 400, the insulation material layer 400 are formed on 100 surface of Semiconductor substrate
Surface flushed with the top surface of the first pseudo- pseudo- fin 232 of fin 231, second.
The material of the insulation material layer 400 and first part's sacrificial layer 211, second part sacrificial layer 212, first part
Mask layer 221, the material of second part mask layer 222 are different.In the present embodiment, the material of the insulation material layer is oxidation
Silicon.In other embodiments of the invention, the insulation material layer 400 can also be silicon nitride, silicon oxynitride, silicon oxide carbide etc.
Dielectric material.
The method for forming the insulation material layer 400 includes：Using chemical vapor deposition method in the Semiconductor substrate
100 surface deposition of insulative material, the pseudo- fin 232 of the described first pseudo- fin 231 and second of insulating materials covering；With described
A part of mask layer 221, second part mask layer 222 are stop-layer, using chemical machinery masking process, to the insulating materials
Planarization process is carried out, forms insulation material layer 400, makes the surface of the insulation material layer 400 and the first pseudo- fin 231, the
The top surface of two pseudo- fins 232 flushes.
In the present embodiment, it is formed after the insulation material layer, also in the described first pseudo- pseudo- fin of fin 231, second
232 surfaces form protective layer 202.In the present embodiment, due to first part's mask layer 221, second part mask layer 222
Material is amorphous type silicon, can be to first part's mask layer 221,222 surface of second part mask layer using oxidation work
Skill forms the protective layer 201, and the oxidation technology can make thermal oxide or wet process oxidation technology.
The thickness of the protective layer 202 is 0.5nm~10nm.The protective layer 202 is in subsequent selective epitaxial technique
Play the role of protecting first part's mask layer 221 or second part mask layer 222 in the process, avoid covering in the first part
Film layer 221 or second part mask layer 222 form epitaxial layer.
In other embodiments of the invention, the material of first part's mask layer and second part mask layer is not half
Conductor material can not carry out selective epitaxial growth semiconductor in first part's mask layer and second part mask layer surface
Material, it may not be necessary to form protective layer at the top of first part's mask layer and second part mask layer.
Fig. 8 is please referred to, 401 and second pseudo- fin of covering part insulation material layer is formed above the first area 102
The protective layer 202 at 232 the second hard mask layer 502, the described first pseudo- fin 231 of removal and its top（Please refer to Fig. 7）, formed
First groove 401.
The material of second hard mask layer 502 is silicon nitride, using the described first pseudo- fin of wet-etching technology removal
231（Please refer to Fig. 7）, the first groove 401 is formed on 101 surface of the first area of Semiconductor substrate 100.Using wet etching
The first pseudo- fin 231 of technique removal and its protective layer 202 at top（Please refer to Fig. 7）When need according to different material selections not
For example, after HF solution removal protective layer 202 may be used, removal first part is etched using KOH solution for same etching solution
Mask layer 221 removes first part's sacrificial layer 211 using phosphoric acid solution again.
In other embodiments of the invention, the described first pseudo- fin 231 of dry etch process removal can also be used（Please
With reference to figure 7）.Mask layer is formed on 400 surface of insulation material layer, the mask layer exposes the on first area 101
The surface of the protective layer 202 at one pseudo- 231 top of fin, then removes 202 He of protective layer using dry etch process etching
First pseudo- fin 231.
Removing the described first pseudo- fin 231（Please refer to Fig. 7）During, second on the second area 102 is pseudo-
232 surface of fin has the second hard mask layer 502 to protect, and is not damaged.
Fig. 9 is please referred to, removes second hard mask layer 502（Please refer to Fig. 8）, in first groove 401（It please refers to
Fig. 8）The first semi-conducting material of interior filling forms the first fin 601, top surface and the insulation material layer 400 of first fin 601
Top surface flushes.
First semi-conducting material is Si or III-V group semi-conductor material, and the III-V group semi-conductor material can be
GaN or GaAs.N-type fin formula field effect transistor is formed subsequently on first area 101, what first semi-conducting material was formed
The electron mobility of first fin 601 is higher, the N-type fin formula field effect transistor subsequently formed on first fin 601
Performance.
The method for specifically forming first fin 601 includes：Using selective deposition technique, in first groove
401（Please refer to Fig. 8）The first semi-conducting material of interior filling.Since the second pseudo- 232 top of fin on the second area 102 has
Matcoveredn, so, growth regulation semiconductor material will not be formed on 302 surface of second part mask layer.
The temperature that the selective epitaxial process forms the first semi-conducting material is 600 DEG C~1100 DEG C, 1 support of pressure~
500 supports, silicon source gas are SiH4Or SiH2Cl2, further include HCl gases and H2, wherein silicon source gas, HCl flow be
1sccm~1000sccm, H2Flow be 0.1slm~50slm.
After full first semi-conducting material is filled in first groove, with the insulation material layer 400 to stop
Only layer planarizes first semi-conducting material, forms the first fin 601, the top surface of first fin 601
It is flushed with the surface of insulation material layer 400.
It can also be doped with N-type ion, including at least a kind of ion in P, As, Sb in first fin 601.It can be with
While filling the first semi-conducting material in first groove, doping process in situ is carried out, to the first semiconductor material
Material is doped, so as to form the first fin 601 of n-type doping.Can by adjust the N-type in first fin 601 from
The doping concentration of son, adjusts the threshold voltage of N-type fin formula field effect transistor being subsequently formed.In the other embodiment of the present invention
In, N-type ion implanting can also be carried out to first fin 601, mixed so as to form N-type after the first fin 601 is formed
The first miscellaneous fin 601.
0 is please referred to Fig.1, covering part insulation material layer 400 and the first fin are formed above the first area 101
The protective layer 202 at 601 the first hard mask layer 501, the described second pseudo- fin 232 of removal and its top（Please refer to Fig. 9）, formed
Second groove 402.
The material of first hard mask layer 501 is silicon nitride, using the described second pseudo- fin of wet-etching technology removal
232（Please refer to Fig. 9）, the second groove 402 is formed on 102 surface of second area of Semiconductor substrate 100.Using wet etching
The second pseudo- fin 232 of technique removal and its protective layer 202 at top（Please refer to Fig. 9）When need according to different material selections not
For example, after HF solution removal protective layer 202 may be used, removal second part is etched using KOH solution for same etching solution
Mask layer 222 removes the second part sacrificial layer 212 using phosphoric acid solution again.
In other embodiments of the invention, the described second pseudo- fin 232 of dry etch process removal can also be used（Please
With reference to figure 9）.Mask layer is formed on 400 surface of insulation material layer, the mask layer exposes the on second area 102
The surface of the protective layer 202 at two pseudo- 232 tops of fin, then removes 202 He of protective layer using dry etch process etching
Second pseudo- fin 232.
Removing the described second pseudo- fin 232（Please refer to Fig. 9）During, the first fin on the first area 101
601 surface of portion has the first hard mask layer 501 to protect, and is not damaged.
1 is please referred to Fig.1, removes first hard mask layer 501（Please refer to Fig.1 0）, in second groove 402（It please join
Examine Figure 10）The second semi-conducting material of interior filling, forms the second fin 602, the top surface of second fin 602 and insulation material layer
400 top surfaces flush.
Second semi-conducting material is SiGe or Ge, and p-type fin field effect crystal is formed subsequently on second area 102
Pipe, the hole mobility for the second fin 602 that second semi-conducting material is formed is higher, can improve p-type fin field effect
The performance of transistor.
The specific method for forming the second fin 602 includes：Using selective deposition technique, in second groove 402
（Please refer to Fig.1 0）The second semi-conducting material of interior filling.In the present embodiment, second semi-conducting material be SiGe, the choosing of use
The reaction temperature of selecting property epitaxy technique is 600 DEG C~1100 DEG C, and pressure is the support of 1 support~500, and silicon source gas is SiH4Or
SiH2Cl2, ge source gas is GeH4, further include HCl gases and H2, wherein silicon source gas, ge source gas, HCl flow be
1sccm~1000sccm, H2Flow be 0.1slm~50slm.
After full second semi-conducting material is filled in second groove, with the insulation material layer 400 to stop
Only layer planarizes second semi-conducting material, forms the second fin 602, the top surface of second fin 602
It is flushed with the surface of insulation material layer 400.
It can also be doped with p-type ion, including at least a kind of ion in B, Ga, In in second fin 602.It can be with
While filling the second semi-conducting material in second groove, doping process in situ is carried out, to the second semiconductor material
Material is doped, so as to form the second fin 602 of p-type doping.Can by adjust the p-type in second fin 602 from
The doping concentration of son, adjusts the threshold voltage of p-type fin formula field effect transistor being subsequently formed.In the other embodiment of the present invention
In, p-type ion implanting can also be carried out to second fin 602, mixed so as to form p-type after the second fin 602 is formed
The second miscellaneous fin 602.
2 are please referred to Fig.1, etches the insulating materials 400（Please refer to Fig.1 1）Form insulating layer 401, the insulating layer 401
Surface less than the first fin 601, the second fin 602 top surface.
The insulating materials 400 is etched using dry etch process（Please refer to Fig.1 1）, insulating layer 401 is formed, it is described exhausted
Edge layer 401 is as the first grid structure subsequently formed on first area 101, the second gate formed on second area 102
Isolation structure between pole structure and Semiconductor substrate 100, and the insulating layer 401 is also used as subsequently respectively first
Between the N-type fin formula field effect transistor and p-type fin formula field effect transistor that are formed on 601 and second fin 602 of fin every
From structure.
3 are please referred to Fig.1,401 surface of insulating layer on the first area 101 is developed across and the first fin of covering part
The first grid structure 701 in portion 601；Surface of insulating layer on the second area is developed across and the second fin of covering part
Second grid structure 702.
The first grid structure 701 includes 401 surface of partial insulative layer being located on first area 101 and part first
First gate dielectric layer 711 on 601 surface of fin and the first grid 721 positioned at 711 surface of the first gate dielectric layer；It is described
Second grid structure 702 includes 602 surface of 401 surface of partial insulative layer and the second fin of part being located on second area 102
The second gate dielectric layer 712 and the second grid 722 positioned at 712 surface of the second gate dielectric layer.The first grid knot
It is mutually disconnected between structure 701 and second grid structure 702.
In the present embodiment, after the first grid structure 701 and second grid structure 702 is formed, described first
The first source/drain is formed in first fin 601 of 701 both sides of gate structure（It is not shown in figure）；In the second grid structure
The second source/drain is formed in second fin 602 of 702 both sides（It is not shown in figure）.
In the present embodiment, further include to be formed positioned at 601 He of 401 surface of insulating layer and the first fin of covering part
Second fin 602, the dielectric layer 700 that surface is flushed with first grid structure 701 and second grid structure 702, the first grid knot
It is isolated between structure 701 and second grid structure 702 by dielectric layer 700.
In the present embodiment, the first fin and the second fin of formation are respectively different semi-conducting materials, wherein the first fin
The material in portion is Si or III-V group semi-conductor material, and the III-V group semi-conductor material can be GaN or GaAs, described first
The material of fin can improve the mobility of electronics, brilliant so as to improve the N-type fin field effect subsequently formed on the first fin
The performance of body pipe；The material of second fin is SiGe or Ge, and the material of second fin can improve the mobility in hole, from
And improve the performance of p-type fin formula field effect transistor subsequently formed on the second fin.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Semiconductor substrate is provided, the Semiconductor substrate has first area and second area；
The semiconductor substrate surface formed sacrificial layer, positioned at the mask layer of the sacrificial layer surface, positioned at the mask layer
The overall thickness of the photoresist layer on surface, the photoresist layer covering part mask layer, the sacrificial layer and mask layer and follow-up shape
Into the first fin and the second fin thickness it is identical；
Side wall is formed in the photoresist layer sidewall surfaces, the side wall positioned at the photoresist layer side is located at Semiconductor substrate
Above first area, the opposite side side wall positioned at the photoresist layer is located above the second area of Semiconductor substrate, the side
The width of wall defines the width of the first fin being subsequently formed and the second fin；
Remove the photoresist layer；
Using the side wall as mask, the mask layer and sacrificial layer are etched to semiconductor substrate surface, is formed on the first region
First pseudo- fin, the described first pseudo- fin include the first part's sacrificial layer being located on first area and first part's sacrifice
First part's mask layer at layer top, forms the second pseudo- fin on second area surface, and the described second pseudo- fin includes being located at the
The second part mask layer at the top of second part sacrificial layer and the second part sacrificial layer on two regions；
Remove the side wall；
Insulation material layer, the surface of the insulation material layer and the first pseudo- fin, second are formed in the semiconductor substrate surface
The top surface of pseudo- fin flushes；
The described first pseudo- fin is removed, forms the first groove；
The first semi-conducting material is filled in first groove, forms the first fin, the top surface of first fin and insulation
Material layer top surface flushes；
The described second pseudo- fin is removed, forms the second groove；
Fill the second semiconductor material layer in second groove, form the second fin, the top surface of second fin with absolutely
Edge material layer top surface flushes；
It etches the insulation material layer and forms insulating layer, the surface of the insulating layer is less than the top surface of the first fin, the second fin；
Surface of insulating layer on the first area is developed across and the first grid structure of the first fin of covering part；Described
Surface of insulating layer on two regions is developed across and the second grid structure of the second fin of covering part；In the first grid knot
The first source/drain is formed in first fin of structure both sides；Second is formed in the second fin of the second grid structure both sides
Source/drain.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that the material of the side wall is oxidation
It is one or more in silicon, silicon nitride, silicon oxynitride, silicon carbide, fire sand；The material of the mask layer is silica, nitrogen
It is one or more in SiClx, silicon oxynitride, silicon carbide, fire sand, amorphous silicon, the material of mask layer and the material of side wall
It is different；The material of the sacrificial layer is one in silica, silicon nitride, silicon oxynitride, silicon carbide, fire sand, amorphous silicon
Kind is a variety of, and the material of the sacrificial layer is different from the material of mask layer.
3. the forming method of semiconductor structure according to claim 2, which is characterized in that the material of the sacrificial layer is nitrogen
SiClx, the material of the mask layer is amorphous silicon, and the material of the side wall is silica.
4. the forming method of semiconductor structure according to claim 3, which is characterized in that further include：It is described exhausted being formed
After edge material layer, protective layer is formed in the described first pseudo- fin and the second pseudo- fin top surface.
5. the forming method of semiconductor structure according to claim 4, which is characterized in that the method for forming the protective layer
For oxidation technology.
6. the forming method of semiconductor structure according to claim 1, which is characterized in that the described first pseudo- fin of removal,
The method for forming the first groove includes：Covering part insulation material layer and the second pseudo- fin are formed above the second area
Second hard mask layer, using the described first pseudo- fin of wet-etching technology removal, in the first area surface shape of Semiconductor substrate
Into the first groove.
7. the forming method of semiconductor structure according to claim 6, which is characterized in that the material of second hard mask layer
Expect for silicon nitride.
8. the forming method of semiconductor structure according to claim 1, which is characterized in that existed using selective deposition technique
The first semi-conducting material of filling in first groove.
9. the forming method of semiconductor structure according to claim 8, which is characterized in that first semi-conducting material
Material is Si, GaAs or GaN.
10. the forming method of semiconductor structure according to claim 9, which is characterized in that adulterated in first fin
There is N-type ion, the N-type ion includes at least a kind of ion in P, As, Sb.
11. the forming method of semiconductor structure according to claim 10, which is characterized in that carried out to first fin
The method of doping is doping process in situ.
12. the forming method of semiconductor structure according to claim 1, which is characterized in that the described second pseudo- fin of removal,
The method for forming the second groove includes：The of covering part insulation material layer and the first fin is formed above the first area
One hard mask layer using the described second pseudo- fin of wet-etching technology removal, is formed on the second area surface of Semiconductor substrate
Second groove.
13. the forming method of semiconductor structure according to claim 12, which is characterized in that first hard mask layer
Material is silicon nitride.
14. the forming method of semiconductor structure according to claim 1, which is characterized in that using selective deposition technique
The second semiconductor material layer is filled in second groove.
15. the forming method of semiconductor structure according to claim 14, which is characterized in that second semi-conducting material
The material of layer is SiGe or Ge.
16. the forming method of semiconductor structure according to claim 15, which is characterized in that adulterated in second fin
There is p-type ion, the p-type ion includes at least a kind of ion in B, Ga, In.
17. the forming method of semiconductor structure according to claim 16, which is characterized in that carried out to second fin
The method of doping is doping process in situ.
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| CN109285875B (en) | 2017-07-20 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Fin type transistor and forming method thereof |
| CN110875186B (en) * | 2018-08-31 | 2023-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN103187418A (en) * | 2011-12-30 | 2013-07-03 | 台湾积体电路制造股份有限公司 | A cmos finfet device and a method of forming the cmos finfet device |
| CN103199019A (en) * | 2012-01-05 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Finfets with vertical fins and methods for forming the same |
| CN104380443A (en) * | 2012-07-27 | 2015-02-25 | 英特尔公司 | Self-aligned 3-d epitaxial structures for MOS device fabrication |
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| CN103187418A (en) * | 2011-12-30 | 2013-07-03 | 台湾积体电路制造股份有限公司 | A cmos finfet device and a method of forming the cmos finfet device |
| CN103199019A (en) * | 2012-01-05 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Finfets with vertical fins and methods for forming the same |
| CN104380443A (en) * | 2012-07-27 | 2015-02-25 | 英特尔公司 | Self-aligned 3-d epitaxial structures for MOS device fabrication |
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