CN104425275A - Forming method of semiconductor structure - Google Patents
Forming method of semiconductor structure Download PDFInfo
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- CN104425275A CN104425275A CN201310398623.4A CN201310398623A CN104425275A CN 104425275 A CN104425275 A CN 104425275A CN 201310398623 A CN201310398623 A CN 201310398623A CN 104425275 A CN104425275 A CN 104425275A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000000034 method Methods 0.000 title claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000010410 layer Substances 0.000 claims description 212
- 230000015572 biosynthetic process Effects 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 239000012774 insulation material Substances 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 239000011241 protective layer Substances 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 239000004576 sand Substances 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 47
- 239000011810 insulating material Substances 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 239000007789 gas Substances 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a forming method of a semiconductor structure. The forming method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region; forming a first pseudo fin part on the surface of the first region of the semiconductor substrate and forming a second pseudo fin part on the surface of the second region of the semiconductor substrate; forming an insulating material layer on the surface of the semiconductor substrate layer, wherein the surface of the insulating material layer is flush with the top surfaces of the first pseudo fin part and the second pseudo fin part; removing the first pseudo fin part to form a first groove; filling the first groove with a first semiconductor material to form a first fin part, wherein the top surface of the first fin part is flush with the top surface of the insulating material layer; removing the second pseudo fin part to form a second groove; filling the second groove with a second semiconductor material layer to form a second fin part, wherein the top surface of the second fin part is flush with the top surface of the insulating material layer. According to the method, a fin field effect transistor with different fin materials can be formed, so that the performance of the fin field effect transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But when the characteristic size of device declines further, even if grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and fin formula field effect transistor (Fin FET) obtains as a kind of multi-gate device and pays close attention to widely.
Fin formula field effect transistor is a kind of common multi-gate device, and Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, described Semiconductor substrate 10 is formed with the fin 11 of protrusion, fin 11 generally obtains after etching Semiconductor substrate 10; Dielectric layer 12, covers a part for the surface of described Semiconductor substrate 10 and the sidewall of fin 11; Grid structure 13, across on described fin 11, covers atop part and the sidewall of described fin 11, and grid structure 13 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.For fin formula field effect transistor, the part that the top of fin 11 and the sidewall of both sides contact with grid structure 13 all becomes channel region, namely has multiple grid, is conducive to increasing drive current, improves device performance.
The performance of the fin formula field effect transistor that prior art is formed needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, adopts the N-type fin formula field effect transistor and the P type fin formula field effect transistor that are formed and have different fin material.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: provide Semiconductor substrate, described Semiconductor substrate has first area and second area; Form the first pseudo-fin on surface, the first area of described Semiconductor substrate, form the second pseudo-fin on the second area surface of described Semiconductor substrate; Form insulation material layer at described semiconductor substrate surface, the surface of described insulation material layer flushes with the end face of the first pseudo-fin, the second pseudo-fin; Remove described first pseudo-fin, form the first groove; In described first groove, fill the first semi-conducting material, form the first fin, the end face of described first fin flushes with insulation material layer end face; Remove described second pseudo-fin, form the second groove; In described second groove, fill the second semiconductor material layer, form the second fin, the end face of described second fin flushes with insulation material layer end face.
Optionally, double-pattern metallization processes or multiple graphics metallization processes is adopted to form described first pseudo-fin and the second pseudo-fin.
Optionally, the method forming described first pseudo-fin and the second pseudo-fin comprises: form sacrifice layer at described semiconductor substrate surface, be positioned at the mask layer of described sacrificial layer surface, be positioned at the photoresist layer on described mask layer surface, described photoresist layer cover part mask layer; Form side wall in described photoresist layer sidewall surfaces, the side wall being positioned at described photoresist layer side is positioned at above the first area of Semiconductor substrate, and the opposite side side wall being positioned at described photoresist layer is positioned at above the second area of Semiconductor substrate; Remove described photoresist layer; With described side wall for mask, etch described mask layer and sacrifice layer to semiconductor substrate surface, form the first pseudo-fin on the first region, described first pseudo-fin comprises the Part I mask layer being positioned at Part I sacrifice layer on first area and described Part I sacrifice layer top, form the second pseudo-fin on second area surface, described second pseudo-fin comprises the Part II mask layer being positioned at Part II sacrifice layer on second area and described Part II sacrifice layer top; Remove described side wall.
Optionally, the material of described side wall is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand; The material of described mask layer is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, amorphous silicon, and the material of mask layer is different from the material of side wall; The material of described sacrifice layer is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, amorphous silicon, and the material of described sacrifice layer is different from the material of mask layer.
Optionally, the material of described sacrifice layer is silicon nitride, and the material of described mask layer is amorphous silicon, and the material of described side wall is silica.
Optionally, also comprise: after the described insulation material layer of formation, form protective layer at described first pseudo-fin and the second pseudo-fin top surface.
Optionally, the method forming described protective layer is oxidation technology.
Optionally, remove described first pseudo-fin, the method forming the first groove comprises: the second hard mask layer forming cover part insulation material layer and the second pseudo-fin above described second area, adopt wet-etching technology to remove described first pseudo-fin, form the first groove on surface, the first area of Semiconductor substrate.
Optionally, the material of described second hard mask layer is silicon nitride.
Optionally, selectivity depositing operation is adopted to fill the first semi-conducting material in described first groove.
Optionally, the material of described first semi-conducting material is Si, GaAs or GaN.
Optionally, doped with N-type ion in described first fin, described N-type ion at least comprises a kind of ion in P, As, Sb.
Optionally, the method for adulterating to described first fin is in-situ doped technique.
Optionally, remove described second pseudo-fin, the method forming the second groove comprises: the first hard mask layer forming cover part insulation material layer and the first fin above described first area, adopt wet-etching technology to remove described second pseudo-fin, form the second groove on the second area surface of Semiconductor substrate.
Optionally, the material of described second hard mask layer is silicon nitride.
Optionally, selectivity depositing operation is adopted to fill the second semiconductor material layer in described second groove.
Optionally, the material of described second semiconductor material layer is SiGe or Ge.
Optionally, doped with P type ion in described second fin, described P type ion at least comprises a kind of ion in B, Ga, In.
Optionally, the method for adulterating to described second fin is in-situ doped technique.
Optionally, also comprise, etch described insulation material layer and form insulating barrier, the surface of described insulating barrier is lower than the end face of the first fin, the second fin; Surface of insulating layer on described first area formed across and the first grid structure of cover part first fin; Surface of insulating layer on described second area formed across and the second grid structure of cover part second fin; The first source/drain is formed in the first fin of described first grid structure both sides; The second source/drain is formed in the second fin of described second grid structure both sides.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, the first area of Semiconductor substrate forms the first pseudo-fin, form the second pseudo-fin on the second region and be positioned at the insulation material layer of semiconductor substrate surface, then described first pseudo-fin is removed respectively, form the first groove, and the first semi-conducting material is filled in described first groove, form the first fin; Remove described second pseudo-fin, form the second groove, and fill the second semi-conducting material in described first groove, form the second fin.Can according to the type the first fin and the second fin needing the fin formula field effect transistor formed, adopt corresponding first semi-conducting material and the second semi-conducting material to form the first fin and the second fin, thus the fin formula field effect transistor with different fin materials can be formed simultaneously.
Further, described first semi-conducting material is Si, GaAs or GaN, and the electron mobility of the first fin that described first semi-conducting material is formed is higher, can improve the performance of N-type fin formula field effect transistor; Described second semi-conducting material is SiGe or Ge, and the mobility in the hole in the second fin that described second semi-conducting material is formed is higher, can improve the performance of P type fin formula field effect transistor.
Accompanying drawing explanation
Fig. 1 is the structural representation of the fin formula field effect transistor transistor of the formation of prior art of the present invention;
Fig. 2 to Figure 13 is the structural representation of the forming process of the semiconductor structure of embodiments of the invention.
Embodiment
As described in the background art, the performance of the fin formula field effect transistor of prior art formation needs further to be improved.
Research finds, what the fin of the N-type fin formula field effect transistor that prior art is formed usually and P type fin formula field effect transistor adopted is identical fin material, and described N-type fin formula field effect transistor and charge carrier corresponding respectively in P type fin formula field effect transistor and electronics are not identical with the migration rate of hole in same material, this just causes the N-type fin formula field effect transistor that formed not identical with the saturation current of P type fin formula field effect transistor.Along with the further decline of process node, this otherness can be more outstanding.Research finds, for P type fin formula field effect transistor, the material of described fin can be Ge or SiGe, can improve the mobility of the holoe carrier in P type fin formula field effect transistor, thus improves the performance of P type fin formula field effect transistor; For N-type fin formula field effect transistor, the material of described fin can be Si or GaN, and N-type fin formula field effect transistor can be made to have higher electronic carrier mobility, thus improves the performance of N-type fin formula field effect transistor.How on substrate, form the N-type fin formula field effect transistor with different fin material and P type fin formula field effect transistor becomes problem demanding prompt solution simultaneously.
The formation method of the semiconductor structure of embodiments of the invention, the N-type fin formula field effect transistor and P type fin formula field effect transistor with different fin material can be formed simultaneously, the performance of described N-type fin formula field effect transistor and P type fin formula field effect transistor can be improved.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 2, provide Semiconductor substrate 100, described Semiconductor substrate has first area 101 and second area 102.
Described Semiconductor substrate 100 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 100 also can be germanium, germanium silicon, GaAs or germanium on insulator, and the material of Semiconductor substrate 100 described in the present embodiment is silicon.
Follow-uply on described first area 101 and second area 102 form dissimilar fin formula field effect transistor respectively.In the present embodiment, described first area 101 forms N-type fin formula field effect transistor, described second area 102 is formed P type fin formula field effect transistor.
Please refer to Fig. 3, form sacrifice layer 200 on described Semiconductor substrate 100 surface, be positioned at the mask layer 201 on described sacrifice layer 200 surface.
The material of described mask layer 201 is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, amorphous silicon; The material of described sacrifice layer is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, amorphous silicon, and the material of described sacrifice layer is different from the material of mask layer.In the present embodiment, the material of described sacrifice layer 200 is silicon nitride, and the material of described mask layer 201 is amorphous silicon.
Chemical vapor deposition method is adopted to form described sacrifice layer 200 and mask layer 201, described sacrifice layer 200 is identical with the thickness of the second fin with the first fin of follow-up formation with the gross thickness of mask layer 201, the thickness of described sacrifice layer 200 is 50nm ~ 200nm, and the thickness of described mask layer 201 is 10nm ~ 50nm.
Please refer to Fig. 4, form photoresist layer 300 on described mask layer 201 surface and be positioned at the side wall 301 of described photoresist layer both sides.
The surface of the mask layer 201 on first area, described photoresist layer 300 cover part 101 and second area 102, the spacing between the first fin of the follow-up formation of the dimension definitions of described photoresist layer 300 and the second fin.
The material of described side wall 301 is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, and the material of described side wall 301 is different from the material of mask layer 201, and in the present embodiment, the material of described side wall 301 is silica.
The method forming described side wall 301 comprises: form the spacer material layer covering described mask layer 201 and photoresist layer 300, described spacer material layer is carried out without mask etching, remove the part spacer material layer being positioned at mask layer 201 surface and photoresist layer 300 top, form the side wall 301 being positioned at described photoresist layer 300 both sides sidewall surfaces.The side wall 301 being positioned at described photoresist layer 300 side is positioned at above the first area 101 of Semiconductor substrate 100, and the side wall 301 being positioned at the opposite side of described photoresist layer 300 is positioned at above the second area 102 of Semiconductor substrate 100.
The width of described side wall 201 is 10nm ~ 40nm, and the width of described side wall 301 defines the first fin of follow-up formation and the width of the second fin.
Please refer to Fig. 5, remove described photoresist layer 300.
In the present embodiment, adopt the plasma ash process containing oxygen to remove described photoresist layer 300, in other embodiments of the invention, wet-etching technology also can be adopted to remove described photoresist layer 300.
After removing described photoresist layer 300, described mask layer 201 surface has discrete side wall 301, the follow-up mask as etching mask layer 201 and sacrifice layer 200 of described side wall 301.
Please refer to Fig. 6, Fig. 5 is please refer to described side wall 301() for mask, etch described mask layer 201(and please refer to Fig. 5) and sacrifice layer 200(please refer to Fig. 5) to Semiconductor substrate 100 surface, first area 101 forms the first pseudo-fin 231, described first pseudo-fin 231 comprises the Part I mask layer 221 being positioned at Part I sacrifice layer 211 on first area 101 and described Part I sacrifice layer 211 top, the second pseudo-fin 232 is formed on second area 102 surface, described second pseudo-fin 232 comprises the Part II mask layer 222 being positioned at Part II sacrifice layer 212 on second area 102 and described Part II sacrifice layer 212 top, then described side wall 301 is removed.
Dry etch process is adopted to form described first pseudo-fin 231 and the second pseudo-fin 232, using side wall 301 as etch mask, side wall 301 Graphic transitions be please refer to Fig. 5 to mask layer 201() upper after, with mask layer 201 for sacrifice layer 200(described in mask etching please refer to Fig. 5).Described mask layer 201 can make first of formation the pseudo-fin 231 keep vertical with the sidewall of the second pseudo-fin 232, reduces etching error.
In the present embodiment, the method for the pseudo-fin of above-mentioned formation first 231 and the second pseudo-fin 232 is double-pattern metallization processes, in other embodiments of the invention, multiple graphics metallization processes can also be adopted to form described first pseudo-fin and the second pseudo-fin.The adjacent spacing adopting double-pattern metallization processes or multiple graphics metallization processes to obtain is less, the first pseudo-fin that width is less and the second pseudo-fin.
In other embodiments of the invention, also after described sacrificial layer surface directly forms Patterned masking layer, described sacrifice layer can be etched, form the first pseudo-fin and the second pseudo-fin.
Please refer to Fig. 7, form insulation material layer 400 on described Semiconductor substrate 100 surface, the surface of described insulation material layer 400 flushes with the end face of the pseudo-fin 232 of the first pseudo-fin 231, second.
The material of described insulation material layer 400 is different from the material of Part I sacrifice layer 211, Part II sacrifice layer 212, Part I mask layer 221, Part II mask layer 222.In the present embodiment, the material of described insulation material layer is silica.In other embodiments of the invention, described insulation material layer 400 can also be the dielectric materials such as silicon nitride, silicon oxynitride, silicon oxide carbide.
The method forming described insulation material layer 400 comprises: adopt chemical vapor deposition method at described Semiconductor substrate 100 surface deposition insulating material, described insulating material covers described first pseudo-fin 231 and the second pseudo-fin 232; With described Part I mask layer 221, Part II mask layer 222 for stop-layer, adopt chemical machinery masking process, planarization is carried out to described insulating material, form insulation material layer 400, the surface of described insulation material layer 400 is flushed with the top surface of the pseudo-fin 232 of the first pseudo-fin 231, second.
In the present embodiment, after forming described insulation material layer, also form protective layer 202 on described first pseudo-fin 232 surface of pseudo-fin 231, second.In the present embodiment; material due to described Part I mask layer 221, Part II mask layer 222 is amorphous type silicon; oxidation technology can be adopted to form described protective layer 201 to described Part I mask layer 221, Part II mask layer 222 surface, described oxidation technology can make thermal oxidation or wet process oxidation technology.
The thickness of described protective layer 202 is 0.5nm ~ 10nm.Described protective layer 202 is the effects playing protection Part I mask layer 221 or Part II mask layer 222 in subsequent selective epitaxial technical process, avoids forming epitaxial loayer at described Part I mask layer 221 or Part II mask layer 222.
In other embodiments of the invention; the material of described Part I mask layer and Part II mask layer is not semi-conducting material; selective epitaxial growth semi-conducting material cannot be carried out at described Part I mask layer and Part II mask layer surface, can not need to form protective layer at the top of described Part I mask layer and Part II mask layer.
Please refer to Fig. 8; the second hard mask layer 502 of cover part insulation material layer 401 and the second pseudo-fin 232 is formed above described first area 102; the protective layer 202(removing described first pseudo-fin 231 and top thereof please refer to Fig. 7), form the first groove 401.
The material of described second hard mask layer 502 is silicon nitride, adopts wet-etching technology to remove described first pseudo-fin 231(and please refer to Fig. 7), form the first groove 401 on surface, the first area 101 of Semiconductor substrate 100.Please refer to Fig. 7 at the protective layer 202(adopting wet-etching technology to remove the first pseudo-fin 231 and top thereof) time need the etching solution different according to different Material selec-tion; such as; after can adopting HF solution removal protective layer 202, KOH solution etching is adopted to remove Part I mask layer 221, adopt phosphoric acid solution to remove described Part I sacrifice layer 211 again.
In other embodiments of the invention, dry etch process also can be adopted to remove described first pseudo-fin 231(and to please refer to Fig. 7).Form mask layer on described insulation material layer 400 surface, described mask layer exposes the surface of the protective layer 202 at the first pseudo-fin 231 top on first area 101, then adopts dry etch process etching to remove described protective layer 202 and the first pseudo-fin 231.
Remove described first pseudo-fin 231(please refer to Fig. 7) process in, the on described second area 102 second pseudo-fin 232 surface has the second hard mask layer 502 to protect, and can not sustain damage.
Please refer to Fig. 9, remove described second hard mask layer 502(and please refer to Fig. 8), please refer to Fig. 8 at described first groove 401() in fill the first semi-conducting material, form the first fin 601, the end face of described first fin 601 flushes with insulation material layer 400 end face.
Described first semi-conducting material is Si or III-V group semi-conductor material, and described III-V group semi-conductor material can be GaN or GaAs.Follow-uply on first area 101, form N-type fin formula field effect transistor, the electron mobility of the first fin 601 that described first semi-conducting material is formed is higher, the performance of the follow-up N-type fin formula field effect transistor formed on described first fin 601.
The method of described first fin 601 of concrete formation comprises: adopt selectivity depositing operation, please refer to Fig. 8 at described first groove 401() in filling the first semi-conducting material.Because pseudo-fin 232 top of second on described second area 102 has protective layer, so, growth regulation semiconductor material can not be formed on described Part II mask layer 302 surface.
The temperature that described selective epitaxial process forms the first semi-conducting material is 600 DEG C ~ 1100 DEG C, and pressure 1 holds in the palm ~ 500 holders, and silicon source gas is SiH
4or SiH
2cl
2, also comprise HCl gas and H
2, wherein the flow of silicon source gas, HCl is 1sccm ~ 1000sccm, H
2flow be 0.1slm ~ 50slm.
Fill full described first semi-conducting material in described first groove after, with described insulation material layer 400 for stop-layer, carry out planarization to described first semi-conducting material, form the first fin 601, the top surface of described first fin 601 flushes with the surface of insulation material layer 400.
Doped with N-type ion, a kind of ion in P, As, Sb can also be at least comprised in described first fin 601.While can filling the first semi-conducting material in described first groove, carry out in-situ doped technique, described first semi-conducting material is adulterated, thus form the first fin 601 of N-type doping.By regulating the doping content of the N-type ion in described first fin 601, the threshold voltage of the N-type fin formula field effect transistor of follow-up formation can be regulated.In other embodiments of the invention, also after formation first fin 601, N-type ion implantation can be carried out to described first fin 601, thus form the first fin 601 of N-type doping.
Please refer to Figure 10, form the first hard mask layer 501 of cover part insulation material layer 400 and the first fin 601 above described first area 101, the protective layer 202(removing described second pseudo-fin 232 and top thereof please refer to Fig. 9), form the second groove 402.
The material of described first hard mask layer 501 is silicon nitride, adopts wet-etching technology to remove described second pseudo-fin 232(and please refer to Fig. 9), form the second groove 402 on second area 102 surface of Semiconductor substrate 100.Please refer to Fig. 9 at the protective layer 202(adopting wet-etching technology to remove the second pseudo-fin 232 and top thereof) time need the etching solution different according to different Material selec-tion; such as; after can adopting HF solution removal protective layer 202, KOH solution etching is adopted to remove Part II mask layer 222, adopt phosphoric acid solution to remove described Part II sacrifice layer 212 again.
In other embodiments of the invention, dry etch process also can be adopted to remove described second pseudo-fin 232(and to please refer to Fig. 9).Form mask layer on described insulation material layer 400 surface, described mask layer exposes the surface of the protective layer 202 at the second pseudo-fin 232 top on second area 102, then adopts dry etch process etching to remove described protective layer 202 and the second pseudo-fin 232.
Remove described second pseudo-fin 232(please refer to Fig. 9) process in, the first fin 601 surface on described first area 101 has the first hard mask layer 501 to protect, and can not sustain damage.
Please refer to Figure 11, remove described first hard mask layer 501(and please refer to Figure 10), please refer to Figure 10 at described second groove 402() in fill the second semi-conducting material, form the second fin 602, the end face of described second fin 602 flushes with insulation material layer 400 end face.
Described second semi-conducting material is SiGe or Ge, follow-uply on second area 102, forms P type fin formula field effect transistor, and the hole mobility of the second fin 602 that described second semi-conducting material is formed is higher, can improve the performance of P type fin formula field effect transistor.
The method of concrete formation second fin 602 comprises: adopt selectivity depositing operation, please refer to Figure 10 at described second groove 402() in filling the second semi-conducting material.In the present embodiment, described second semi-conducting material is SiGe, and the reaction temperature of the selective epitaxial process of employing is 600 DEG C ~ 1100 DEG C, and pressure is that 1 holder ~ 500 are held in the palm, and silicon source gas is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, also comprise HCl gas and H
2, wherein the flow of silicon source gas, germanium source gas, HCl is 1sccm ~ 1000sccm, H
2flow be 0.1slm ~ 50slm.
Fill full described second semi-conducting material in described second groove after, with described insulation material layer 400 for stop-layer, carry out planarization to described second semi-conducting material, form the second fin 602, the top surface of described second fin 602 flushes with the surface of insulation material layer 400.
Doped with P type ion, a kind of ion in B, Ga, In can also be at least comprised in described second fin 602.While can filling the second semi-conducting material in described second groove, carry out in-situ doped technique, described second semi-conducting material is adulterated, thus form the second fin 602 of P type doping.By regulating the doping content of the P type ion in described second fin 602, the threshold voltage of the P type fin formula field effect transistor of follow-up formation can be regulated.In other embodiments of the invention, also after formation second fin 602, P type ion implantation can be carried out to described second fin 602, thus form the second fin 602 of P type doping.
Please refer to Figure 12, etch described insulating material 400(and please refer to Figure 11) form insulating barrier 401, the surface of described insulating barrier 401 is lower than the end face of the first fin 601, second fin 602.
Adopt dry etch process to etch described insulating material 400(and please refer to Figure 11), form insulating barrier 401, described insulating barrier 401 is as the first grid structure of follow-up formation on first area 101, the isolation structure between the second grid structure formed on second area 102 and Semiconductor substrate 100, and described insulating barrier 401 can also as the isolation structure between the N-type fin formula field effect transistor of follow-up formation on the first fin 601 and the second fin 602 respectively and P type fin formula field effect transistor.
Please refer to Figure 13, insulating barrier 401 on described first area 101 surface formed across and the first grid structure 701 of cover part first fin 601; Surface of insulating layer on described second area formed across and the second grid structure 702 of cover part second fin.
Described first grid structure 701 comprises the first grid dielectric layer 711 that is positioned at partial insulative layer 401 surface on first area 101 and part first fin 601 surface and is positioned at the first grid 721 on described first grid dielectric layer 711 surface; Described second grid structure 702 comprises the second gate dielectric layer 712 that is positioned at partial insulative layer 401 surface on second area 102 and part second fin 602 surface and is positioned at the second grid 722 on described second gate dielectric layer 712 surface.Mutually disconnect between described first grid structure 701 and second grid structure 702.
In the present embodiment, after the described first grid structure 701 of formation and second grid structure 702, in the first fin 601 of described first grid structure 701 both sides, form the first source/drain (not shown); The second source/drain (not shown) is formed in the second fin 602 of described second grid structure 702 both sides.
In the present embodiment, also comprise formation and be positioned at described insulating barrier 401 surface, and cover part first fin 601 and the second fin 602, isolated by dielectric layer 700 between dielectric layer 700, the first grid structure 701 that surface flushes with first grid structure 701 and second grid structure 702 and second grid structure 702.
In the present embodiment, the first fin formed and the second fin are respectively different semi-conducting materials, wherein the material of the first fin is Si or III-V group semi-conductor material, described III-V group semi-conductor material can be GaN or GaAs, the material of described first fin can improve the mobility of electronics, thus improves the performance of the follow-up N-type fin formula field effect transistor formed on the first fin; The material of the second fin is SiGe or Ge, and the material of described second fin can improve the mobility in hole, thus improves the performance of the follow-up P type fin formula field effect transistor formed on the second fin.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate has first area and second area;
Form the first pseudo-fin on surface, the first area of described Semiconductor substrate, form the second pseudo-fin on the second area surface of described Semiconductor substrate;
Form insulation material layer at described semiconductor substrate surface, the surface of described insulation material layer flushes with the end face of the first pseudo-fin, the second pseudo-fin;
Remove described first pseudo-fin, form the first groove;
In described first groove, fill the first semi-conducting material, form the first fin, the end face of described first fin flushes with insulation material layer end face;
Remove described second pseudo-fin, form the second groove;
In described second groove, fill the second semiconductor material layer, form the second fin, the end face of described second fin flushes with insulation material layer end face.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, adopts double-pattern metallization processes or multiple graphics metallization processes to form described first pseudo-fin and the second pseudo-fin.
3. the formation method of semiconductor structure according to claim 2, it is characterized in that, the method forming described first pseudo-fin and the second pseudo-fin comprises: form sacrifice layer at described semiconductor substrate surface, be positioned at the mask layer of described sacrificial layer surface, be positioned at the photoresist layer on described mask layer surface, described photoresist layer cover part mask layer; Form side wall in described photoresist layer sidewall surfaces, the side wall being positioned at described photoresist layer side is positioned at above the first area of Semiconductor substrate, and the opposite side side wall being positioned at described photoresist layer is positioned at above the second area of Semiconductor substrate; Remove described photoresist layer; With described side wall for mask, etch described mask layer and sacrifice layer to semiconductor substrate surface, form the first pseudo-fin on the first region, described first pseudo-fin comprises the Part I mask layer being positioned at Part I sacrifice layer on first area and described Part I sacrifice layer top, form the second pseudo-fin on second area surface, described second pseudo-fin comprises the Part II mask layer being positioned at Part II sacrifice layer on second area and described Part II sacrifice layer top; Remove described side wall.
4. the formation method of semiconductor structure according to claim 3, is characterized in that, the material of described side wall is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand; The material of described mask layer is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, amorphous silicon, and the material of mask layer is different from the material of side wall; The material of described sacrifice layer is one or more in silica, silicon nitride, silicon oxynitride, carborundum, fire sand, amorphous silicon, and the material of described sacrifice layer is different from the material of mask layer.
5. the formation method of semiconductor structure according to claim 4, is characterized in that, the material of described sacrifice layer is silicon nitride, and the material of described mask layer is amorphous silicon, and the material of described side wall is silica.
6. the formation method of semiconductor structure according to claim 5, is characterized in that, also comprise: after the described insulation material layer of formation, forms protective layer at described first pseudo-fin and the second pseudo-fin top surface.
7. the formation method of semiconductor structure according to claim 6, is characterized in that, the method forming described protective layer is oxidation technology.
8. the formation method of semiconductor structure according to claim 1, it is characterized in that, remove described first pseudo-fin, the method forming the first groove comprises: the second hard mask layer forming cover part insulation material layer and the second pseudo-fin above described second area, adopt wet-etching technology to remove described first pseudo-fin, form the first groove on surface, the first area of Semiconductor substrate.
9. the formation method of semiconductor structure according to claim 8, is characterized in that, the material of described second hard mask layer is silicon nitride.
10. the formation method of semiconductor structure according to claim 1, is characterized in that, adopts selectivity depositing operation to fill the first semi-conducting material in described first groove.
The formation method of 11. semiconductor structures according to claim 10, is characterized in that, the material of described first semi-conducting material is Si, GaAs or GaN.
The formation method of 12. semiconductor structures according to claim 11, is characterized in that, doped with N-type ion in described first fin, described N-type ion at least comprises a kind of ion in P, As, Sb.
The formation method of 13. semiconductor structures according to claim 12, is characterized in that, the method for adulterating to described first fin is in-situ doped technique.
The formation method of 14. semiconductor structures according to claim 1, it is characterized in that, remove described second pseudo-fin, the method forming the second groove comprises: the first hard mask layer forming cover part insulation material layer and the first fin above described first area, adopt wet-etching technology to remove described second pseudo-fin, form the second groove on the second area surface of Semiconductor substrate.
The formation method of 15. semiconductor structures according to claim 14, is characterized in that, the material of described second hard mask layer is silicon nitride.
The formation method of 16. semiconductor structures according to claim 1, is characterized in that, adopts selectivity depositing operation to fill the second semiconductor material layer in described second groove.
The formation method of 17. semiconductor structures according to claim 16, is characterized in that, the material of described second semiconductor material layer is SiGe or Ge.
The formation method of 18. semiconductor structures according to claim 17, is characterized in that, doped with P type ion in described second fin, described P type ion at least comprises a kind of ion in B, Ga, In.
The formation method of 19. semiconductor structures according to claim 18, is characterized in that, the method for adulterating to described second fin is in-situ doped technique.
The formation method of 20. semiconductor structures according to claim 1, is characterized in that, also comprise, and etch described insulation material layer and form insulating barrier, the surface of described insulating barrier is lower than the end face of the first fin, the second fin; Surface of insulating layer on described first area formed across and the first grid structure of cover part first fin; Surface of insulating layer on described second area formed across and the second grid structure of cover part second fin; The first source/drain is formed in the first fin of described first grid structure both sides; The second source/drain is formed in the second fin of described second grid structure both sides.
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