CN103515420B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN103515420B CN103515420B CN201210214114.7A CN201210214114A CN103515420B CN 103515420 B CN103515420 B CN 103515420B CN 201210214114 A CN201210214114 A CN 201210214114A CN 103515420 B CN103515420 B CN 103515420B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 142
- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000000463 material Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000011010 flushing procedure Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 abstract description 25
- 230000006872 improvement Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 13
- 238000005530 etching Methods 0.000 description 7
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- KXCAEQNNTZANTK-UHFFFAOYSA-N stannane Chemical compound [SnH4] KXCAEQNNTZANTK-UHFFFAOYSA-N 0.000 description 1
- 229910000083 tin tetrahydride Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor device and forming method thereof, wherein, described semiconductor device includes: Semiconductor substrate, has some grooves in described Semiconductor substrate；Being positioned at the insulating barrier of described groove, the surface of described insulating barrier flushes with semiconductor substrate surface；The fin of the semiconductor substrate surface between adjacent trenches, described fin includes: being positioned at the first sub-fin of outer layer and the second sub-fin by the first sub-fin parcel, the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin.The performance improvement of described semiconductor device and fin field effect pipe.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor device and forming method thereof.
Background technology
Along with developing rapidly of semiconductor fabrication, semiconductor device is towards higher component density, and the direction of higher integrated level is developed.Transistor is currently widely used as most basic semiconductor device, and therefore along with the raising of the component density of semiconductor device and integrated level, the grid size of transistor is also shorter and shorter.But, the grid size of transistor shortens and transistor can be made to produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.
In order to overcome the short-channel effect of transistor, it is suppressed that leakage current, prior art proposes fin formula field effect transistor (FinFET), refer to Fig. 1, is the structural representation of the fin field effect pipe of prior art, including:
Semiconductor substrate 10；Being positioned at the fin 14 that described Semiconductor substrate 10 protrudes above, described fin 14 obtains generally by after Semiconductor substrate 10 is etched；Covering the dielectric layer 11 of a part for described Semiconductor substrate 10 surface and fin 14 sidewall, the surface of described dielectric layer 11 is lower than the top of described fin 14；Across the grid structure 12 at the top of described fin 14 and sidewall, described grid structure 12 includes gate dielectric layer (not shown) and the gate electrode (not shown) being positioned on described gate dielectric layer.It should be noted that the part contacted with grid structure 12 for fin field effect pipe, the top of fin 14 and the sidewall of both sides becomes channel region.
Reducing further however as process node, the leakage current of the fin field effect pipe of prior art is relatively big, electric current is less, performance is not good in driving.
More fin field effect pipe refer to the U.S. patent documents that the patent No. is US7317230B2.
Summary of the invention
The problem that this invention address that is to provide a kind of semiconductor device and forming method, to improve driving electric current, reduces the leakage current of fin field effect pipe, improves device performance.
For solving the problems referred to above, the present invention provides a kind of semiconductor device, including: Semiconductor substrate, there is in described Semiconductor substrate some grooves；Being positioned at the insulating barrier of described groove, the surface of described insulating barrier flushes with semiconductor substrate surface；The fin of the semiconductor substrate surface between adjacent trenches, described fin includes: being positioned at the first sub-fin of outer layer and the second sub-fin by the first sub-fin parcel, the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin.
Alternatively, the material of described first sub-fin is silicon or SiGe.
Alternatively, when the material of described first sub-fin is silicon, the material of described second sub-fin is SiGe or SiGe stannum；When the material of described first sub-fin is SiGe, the material of described second sub-fin is germanium or germanium stannum.
Alternatively, the thickness of described first sub-fin isThe thickness of described second sub-fin is
Alternatively, the material of described insulating barrier is silicon oxide or silicon nitride.
Alternatively, also include: across the grid structure at the top of described fin and sidewall；It is positioned at the source/drain region of the fin of described grid structure both sides.
Alternatively, described grid structure includes across the described top of the first sub-fin and the gate dielectric layer of sidewall and the gate electrode layer being positioned at described gate dielectric layer surface.
Alternatively, the material of described gate dielectric layer is silicon oxide or high K dielectric, and the material of described gate electrode layer is polysilicon or metal.
The present invention also provides for the forming method of a kind of semiconductor device, including: Semiconductor substrate is provided, there is in described Semiconductor substrate some grooves, in described groove, there is insulating barrier, the surface of described insulating barrier flushes with semiconductor substrate surface, and the semiconductor substrate surface between adjacent described groove has the first sub-fin layer；Form mask layer on described Semiconductor substrate, insulating barrier and the first sub-fin layer surface, described mask layer exposes the first sub-fin layer surface needing to form the correspondence position of the second sub-fin；With described mask layer for mask, remove the first sub-fin layer of segment thickness, form opening；Forming the second sub-fin in described opening, the surface of described second sub-fin is lower than the top of described first sub-fin layer, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin layer；Covering semi-conducting material until flushing with the first sub-fin layer top in described second sub-fin portion surface, the semi-conducting material covered and the first sub-fin layer form the first sub-fin, and described semi-conducting material is consistent with the material of described first sub-fin layer；After forming the first sub-fin, remove mask layer.
Alternatively, the material of described first sub-fin is silicon or SiGe.
Alternatively, when the material of described first sub-fin is silicon, the material of described second sub-fin is SiGe or SiGe stannum；When the material of described first sub-fin is SiGe, the material of described second sub-fin is germanium or germanium stannum.
Alternatively, the thickness of described first sub-fin isThe thickness of described second sub-fin is
Alternatively, described second sub-fin and the formation process at described second sub-fin portion surface covering semi-conducting material are selective epitaxial depositing operation.
Alternatively, the described selective epitaxial growth process covering semi-conducting material in described second sub-fin portion surface is temperature is 500～800 DEG C, and air pressure is 1 holder～100 holder, and reacting gas includes: silicon source gas, HCl, B2H6、H2, wherein silicon source gas, HCl and B2H6Flow be 1sccm～1000sccm, H2Flow be 0.1slm～50slm.
Alternatively, the material of described mask layer is silicon nitride.
Alternatively, the material of described insulating barrier is silicon oxide or silicon nitride.
Alternatively, also include: be developed across the top of described first sub-fin and the grid structure of sidewall in described first sub-fin portion surface；Source/drain region is formed in the first sub-fin and the second fin of described grid structure both sides.
Alternatively, described grid structure includes across the described top of the first sub-fin and the gate dielectric layer of sidewall and the gate electrode layer being positioned at described gate dielectric layer surface.
Alternatively, the material of described gate dielectric layer is silicon oxide or high K dielectric, and the material of described gate electrode layer is polysilicon or metal.
Compared with prior art, technical scheme has the advantage that
Described semiconductor device includes the first sub-fin of the semiconductor substrate surface between adjacent trenches and by the second sub-fin of described first sub-fin parcel, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin, then between described first sub-fin and the second sub-fin, because of lattice mismatch, stress increases, carrier is made to improve at the mobility of the first sub-fin, thus improve the driving electric current of device, reduce the generation of leakage current, improve device performance.
Further, described semiconductor device includes the grid structure with fin top and sidewall across above-mentioned semiconductor device, owing between described first sub-fin and the second sub-fin, because of lattice mismatch, stress increases, stress in the channel region that then described fin contacts with grid structure increases, carrier mobility in channel region improves, thus decreasing the leakage current of device, improve the performance of fin field effect pipe.
The technique of the forming method of described semiconductor device is simple, the second sub-fin is formed in the first sub-fin layer, described first sub-fin wraps up the second sub-fin, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin layer, between the first sub-fin and the second sub-fin that are then formed, because of lattice mismatch, stress increases, the device carriers formed mobility in the first sub-fin is made to improve, it is thus possible to improve the driving electric current of device, and reduce the generation of device creepage, improve device performance.
Further, on the forming method basis of described semiconductor device, it is developed across the top of described fin and the grid structure of sidewall, between the first sub-fin and the second sub-fin owing to being formed, because of lattice mismatch, stress increases, the fin then formed increases with the stress in the channel region contacted with described grid structure, then make the carrier mobility in channel region improve, and the driving electric current of the fin field effect pipe formed increases, leakage current reduces, and performance improves.
Accompanying drawing explanation
Fig. 1 is the structural representation of the fin field effect pipe of prior art；
Fig. 2 is the schematic flow sheet of the forming method of semiconductor device described in first embodiment of the invention；
Fig. 3 to Fig. 8 is the cross-sectional view of the forming process of semiconductor device described in first embodiment；
Fig. 9 and Figure 11 is the cross-sectional view of the forming process of fin field effect pipe described in the second embodiment；
Figure 10 is Fig. 9 cross-sectional view on AA ' direction.
Detailed description of the invention
As stated in the Background Art, the driving electric current of the fin field effect pipe of prior art is less, leakage current is relatively big, performance is not good.
Find through the research of inventor, the driving electric current of the fin field effect pipe of prior art is less, leakage current is more greatly due to reducing along with process node, the size of the channel region that fin contacts to grid structure is also corresponding to be reduced, but operating current will not reduce accordingly；Therefore, when keeping operating current size constant, carrier easily spreads at fin, thus producing leakage current, driving electric current is made to reduce, bias temperature unstable (BTI, BiasTemperatureInstability), the degradation of device.
Further research through inventor, inventors herein propose the fin of a kind of fin field effect pipe, described fin includes: be positioned at the first sub-fin of outer layer, and the second sub-fin by the first sub-fin parcel, the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin layer, the stress that then there is lattice mismatch between described first sub-fin and the second sub-fin and produce, makes the carrier mobility in described first sub-fin and the second sub-fin improve；The mobility of the fin field effect pipe formed by described fin improves, thus driving electric current to improve, leakage current reduces, the performance improvement of device.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
First embodiment
Fig. 2 is the schematic flow sheet of the forming method of semiconductor device described in first embodiment of the invention, including step:
Step S101, it is provided that Semiconductor substrate, has some grooves in described Semiconductor substrate, have insulating barrier in described groove, and the surface of described insulating barrier flushes with semiconductor substrate surface, and the semiconductor substrate surface between adjacent described groove has the first sub-fin layer；
Step S102, forms mask layer on described Semiconductor substrate, insulating barrier and the first sub-fin layer surface, and described mask layer exposes the first sub-fin layer surface needing to form the correspondence position of the second sub-fin；
Step S103, with described mask layer for mask, removes the first sub-fin layer of segment thickness, forms opening；
Step S104, forms the second sub-fin in described opening, and the surface of described second sub-fin is lower than the top of described first sub-fin layer, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin layer；
Step S105, covers semi-conducting material until flushing with the first sub-fin layer top in described second sub-fin portion surface, and the semi-conducting material covered and the first sub-fin layer form the first sub-fin, and described semi-conducting material is consistent with the material of described first sub-fin layer；
Step S106, after forming the first sub-fin, removes mask layer.
The forming method of semiconductor device described in the present embodiment, formed in described first sub-fin layer in opening and form the second sub-fin, semi-conducting material is covered until flushing with the first sub-fin layer top in described second sub-fin portion surface, form the first sub-fin, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin, the stress that there is lattice mismatch between the first sub-fin and the second sub-fin that are then formed and produce, so that the mobility that carrier is in the first sub-fin and the second sub-fin improves；And then improve the driving electric current of the semiconductor device formed, reduce the generation of leakage current, make the device performance formed good.
Below with reference to accompanying drawing, the forming method of fin field effect pipe described in the present embodiment being illustrated, Fig. 3 to Fig. 8 is the cross-sectional view of the forming process of semiconductor device described in the present embodiment.
Refer to Fig. 3, Semiconductor substrate 100 is provided, there is in described Semiconductor substrate 100 some grooves 101, in described groove 101, there is insulating barrier 102, the surface of described insulating barrier 102 flushes with Semiconductor substrate 100 surface, and Semiconductor substrate 100 surface between adjacent described groove 101 has the first sub-fin layer 103.
Described Semiconductor substrate 100 is for providing work platforms for subsequent technique, and the material of described Semiconductor substrate 100 is silicon, SiGe, carborundum, silicon-on-insulator or III-V (silicon nitride or GaAs etc.).
The formation process of described groove 101 is etching technics；The material of described insulating barrier 102 is silicon oxide or silicon nitride, and the formation process of described insulating barrier 102 is depositing operation, it is preferred that chemical vapor deposition method；The first sub-fin and the second sub-fin that Semiconductor substrate 100 between described adjacent trenches 101 and subsequent technique are formed collectively form fin structure.
The material of described first sub-fin layer 103 is silicon or SiGe, the thickness of described first sub-fin layer 103 is 40～100 nanometers, described first sub-fin layer 103 for forming the first sub-fin in subsequent technique, and forms the second sub-fin in described first sub-fin layer 103.
In the present embodiment, the formation process of described first sub-fin layer 103 is selective epitaxial depositing operation；The parameter of described selective epitaxial depositing operation is: temperature is 500～800 DEG C, and air pressure is 1 holder～100 holder；When the material of described first sub-fin layer 103 is silicon, the reacting gas of described selective epitaxial depositing operation includes: silicon source gas, HCl, B2H6And H2, wherein silicon source gas, HCl and B2H6Flow be 1sccm～1000sccm, H2Flow be 0.1slm～50slm；Described silicon source gas includes: SiH4And SiH2Cl2In one or both；When the material of described first sub-fin layer 103 is SiGe, described reacting gas also includes: ge source gas GeH4。
In another embodiment, when described Semiconductor substrate 100 and the first sub-fin layer 103 are silicon, the formation process of described first sub-fin layer 103 is: in described Semiconductor substrate 100, etching forms groove 101；Formation of deposits insulating barrier 102 in described groove 101, the surface of described insulating barrier 102 lower than described Semiconductor substrate 100 surface, then becomes the first sub-fin layer 103 higher than the Semiconductor substrate 100 on described insulating barrier 102 surface.
It should be noted that in the present embodiment, the sidewall of described groove 101 is made up of upper side wall and lower wall；Described upper side wall is vertical with described Semiconductor substrate 100 surface, and the height h of described upper side wall2It it is 40～300 nanometers；Described lower wall tilts, and makes the bottom width of described groove 101 less than open top width, and the angle f on described lower wall and described Semiconductor substrate 100 surface is 85 °；The degree of depth h of described groove 1011It it is 100～300 nanometers；Distance l between the horizontal mid-point of described adjacent trenches 101 is 10～60 nanometers；The bottom of described groove 101 is to Semiconductor substrate 100 sunken inside, and the angle g on the tangent line of bottom margin and Semiconductor substrate 100 surface is 60～80 °；The shape of described groove 101 is conducive to deposition fill insulant, makes defect in the insulating barrier 102 formed less, decreases the generation of leakage current, thus isolation effect is better, device performance is more preferably.
Refer to Fig. 4, form mask layer 104 on described Semiconductor substrate 100, insulating barrier 102 and the first sub-fin layer 103 surface, described mask layer 104 exposes the first sub-fin layer 103 surface needing to form the correspondence position of the second sub-fin (not shown).
Described mask layer 104 for protecting described first sub-fin layer 103 surface in subsequent technique, and the material of described mask layer 104 is silicon nitride, and the thickness of described mask layer 104 isDescribed mask layer 104 is for defining the second sub-fin formed in described first sub-fin layer 103 at the follow-up needs correspondence position on described first sub-fin layer 103 surface；The formation process of described hard mask layer 104 is: at described Semiconductor substrate 100, insulating barrier 102 and the first sub-fin layer 103 surface formation of deposits mask thin film, it is preferred that chemical vapor deposition method；Photoresist layer is formed at described mask film surface；Graphical described photoresist layer, exposes the correspondence position needing to form the second sub-fin；With described photoresist layer for mask thin film described in mask etching, form mask layer 104.
Refer to Fig. 5, with described mask layer 104 for mask, remove the first sub-fin layer 103 of segment thickness, in described first sub-fin layer 103, form opening 105.
Described opening 105 for forming the second sub-fin in subsequent technique, after described second sub-fin portion surface covers semi-conducting material, described second sub-fin is made to be formed in the first sub-fin, and the lattice paprmeter of the second sub-fin is more than the first sub-fin, so that the stress between the first sub-fin and the second sub-fin increases, then carrier mobility between the be subsequently formed first sub-fin and the second sub-fin improves；The degree of depth of described opening 105 isThe formation process of described opening 105 is etching technics, it is preferred that anisotropic dry etching；In the present embodiment, the formation process of described opening 105 is anisotropic dry etching, the parameter of described dry etching is: etching gas is the mixing gas of chlorine, hydrogen bromide or chlorine and hydrogen bromide, wherein, the flow of hydrogen bromide is 200～800sccm, and the flow of chlorine is 20～100sccm, and the flow as the noble gas of carrier gas is 50～1000sccm, the pressure of etching cavity is 2～200mTorr, and etch period is 15～60 seconds.
Refer to Fig. 6, the second sub-fin 106 is formed in described opening 105 (such as Fig. 5), the surface of described second sub-fin 106 is lower than the top of described first sub-fin layer 103, and the lattice paprmeter of the material of described second sub-fin 106 is more than described first sub-fin layer 103.
The material of described second sub-fin 106 is SiGe, SiGe stannum or germanium；When the material of described first sub-fin layer 103 is silicon, the material of described second sub-fin 106 is SiGe or SiGe stannum；When the material of described first sub-fin layer 103 is SiGe, the material of described second sub-fin 106 is germanium or germanium stannum；The surface of described second sub-fin 106 is lower than the top of described first sub-fin layer 103, then subsequent technique is after described second sub-fin 106 surface covers semi-conducting material, the the first sub-fin formed can wrap up described second sub-fin, and the lattice paprmeter of the material of described second sub-fin 106 is more than the first sub-fin, then there is, between described first sub-fin layer 103 and the second sub-fin 106, the stress produced because of lattice mismatch, so that the mobility that carrier is in the sub-fin 106 of the first sub-fin and second improves, leakage current reduces, the device performance formed improves.
The thickness of described second sub-fin 106 isThe formation process of described second sub-fin 106 is selective epitaxial depositing operation, identical when the selective epitaxial depositing operation of the described sub-fin of formation second 106 is with formation the first sub-fin；When the material of described second sub-fin 106 is SiGe stannum, described selective epitaxial depositing operation and reacting gas also include stannum source gas SnH4。
Refer to Fig. 7, semi-conducting material is covered until flushing with the first sub-fin layer 103 (such as Fig. 6) top on described second sub-fin 106 surface, the semi-conducting material covered and the first sub-fin layer 103 form the first sub-fin 107, and described semi-conducting material is consistent with the material of described first sub-fin layer 103.
The material of described semi-conducting material and the first sub-fin layer 103 is unanimously silicon or SiGe, the technique of described covering semi-conducting material is selective epitaxial depositing operation, described selective epitaxial depositing operation is consistent with the technique forming the first sub-fin layer 103, and therefore not to repeat here.
There is, between the first sub-fin 107 and the second sub-fin 106 that are formed, the stress produced because of lattice mismatch, then carrier mobility in described first sub-fin 107 and the second sub-fin 106 improves, thus improve the driving electric current of device, decrease the leakage current of device, and then improve device performance.
It should be noted that Semiconductor substrate the 100, first sub-fin 106 and the second sub-fin 106 between adjacent insulating barrier 102 collectively form fin structure.
Refer to Fig. 8, after forming the first sub-fin 107, remove mask layer 104 (such as Fig. 7).
The technique of described removal mask layer 104 is dry etching or wet etching, it is preferred that wet-etching technology；In the present embodiment, adopting wet etching to remove described mask layer 104, the etching liquid of described wet etching is phosphoric acid.
After above-mentioned steps completes, described in the present embodiment, semiconductor device completes.In the forming method of semiconductor device described in the present embodiment, the second sub-fin 106 is formed in described first sub-fin 107, the described first fully wrapped around described second sub-fin 106 of sub-fin 107, and the lattice paprmeter of the material of described second sub-fin 106 is more than the first sub-fin 107, then there is the stress produced because of lattice mismatch in described first sub-fin 107 and the second sub-fin 106, so that the mobility that carrier is in described first sub-fin 107 and the second sub-fin 106 improves；The driving electric current of the semiconductor device formed increases, and leakage current reduces, performance improvement.
The present inventor also provides for a kind of semiconductor device formed based on said method, refer to Fig. 8, including: Semiconductor substrate 100, there is in described Semiconductor substrate some grooves 101；Being positioned at the insulating barrier 102 of described groove 101, the surface of described insulating barrier 102 flushes with Semiconductor substrate 100 surface；The fin on Semiconductor substrate 100 surface between adjacent trenches 101, described fin includes: be positioned at the first sub-fin 107 of outer layer, and it being positioned at the second sub-fin 106 wrapped up by the first sub-fin 107 of described first sub-fin 107, the lattice paprmeter of the material of described second sub-fin 106 is more than described first sub-fin 107.
Described Semiconductor substrate 100 is for providing work platforms for subsequent technique, and the material of described Semiconductor substrate 100 is silicon, SiGe, carborundum, silicon-on-insulator or III-V (silicon nitride or GaAs etc.).
The material of described first sub-fin 107 is silicon or SiGe；When the material of described first sub-fin 107 is silicon, the material of described second sub-fin 106 is SiGe or SiGe stannum；When the material of described first sub-fin 107 is SiGe, the material of described second sub-fin 106 is germanium or germanium stannum；There is, between described first sub-fin 107 and the second sub-fin 106, the stress produced because of lattice mismatch, so that carrier improves at the mobility of described first sub-fin 107 and the second sub-fin 106；Then the driving electric current of described semiconductor device increases, and leakage current reduces, and performance improves.
The thickness of described first sub-fin 107 isThe thickness of described second sub-fin 106 isThe material of described insulating barrier 102 is silicon oxide or silicon nitride.
It should be noted that Semiconductor substrate the 100, first sub-fin 107 and the second sub-fin 106 between adjacent insulating barrier 102 collectively form fin structure.
It should be noted that in the present embodiment, refer to Fig. 3, the sidewall of described groove 101 is made up of upper side wall and lower wall；Described upper side wall is vertical with described semiconductor substrate surface, and the height h of described upper side wall2It it is 40～300 nanometers；Described lower wall tilts, and makes the bottom width of described groove 101 less than open top width, and the angle f of described lower wall and described semiconductor substrate surface is 85 °；The degree of depth h of described groove 1011It it is 100～300 nanometers；Distance l between the horizontal mid-point of described adjacent trenches 101 is 10～60 nanometers；The bottom of described groove 101 is to Semiconductor substrate 100 sunken inside, and the angle g on the tangent line of bottom margin and Semiconductor substrate 100 surface is 60～80 °；The shape of described groove 101 can make the quality of the insulating barrier 102 in groove 101 good, and defect is few, improves isolation effect, is that device performance improves.
In semiconductor device described in the present embodiment, described second sub-fin 106 is positioned at described first sub-fin 107, and the described first fully wrapped around described second sub-fin 106 of sub-fin 107, and the lattice paprmeter of the material of described second sub-fin 106 is more than described first sub-fin 107, then there is stress between described first sub-fin 107 and the second sub-fin 106, thus improve the mobility of carrier；The drive circuit of described semiconductor device improves, and leakage current reduces, performance improvement.
Second embodiment
Accordingly, inventor additionally provides the forming method of a kind of fin field effect pipe, on the basis of the semiconductor device (such as Fig. 8) formed in first embodiment, also includes:
Refer to Fig. 9 and Figure 10, Figure 10 is Fig. 9 cross-sectional view on AA ' direction, is developed across the top of described first sub-fin 107 and the grid structure 108 of sidewall on described Semiconductor substrate 100, insulating barrier 102 and the first sub-fin 107 surface.
Described grid structure 108 includes: across the described top layers of the first sub-fin 107 and the gate dielectric layer 110 of side wall layer and the gate electrode layer 111 being positioned at described gate dielectric layer 110 surface.
The material of described gate electrode layer 111 is polysilicon or metal；When the material of described gate electrode layer 111 is polysilicon, described gate dielectric layer 110 is silicon oxide；When the material of described gate electrode layer 111 is metal, described gate dielectric layer 110 is hafnium.
Refer to Figure 11, in the first sub-fin 107 and the second sub-fin 106 of described grid structure 108 both sides, form source/drain region 109.
The formation process of described source/drain region 109 is, with described grid structure 108 for mask, carries out ion implanting and form source/drain region 109 in the first sub-fin 107 and the second sub-fin 106 of described grid structure 108 both sides；Need to illustrate still, when needs form PMOS transistor, implanted with p-type ion boron or indium；When needs form PMOS transistor, ion implanting n-type ion phosphorus or arsenic ion.
After above-mentioned steps completes, described in the present embodiment, fin field effect pipe completes.In the fin field effect pipe that the present embodiment is formed, there is stress between described first sub-fin 107 and the second sub-fin 106 because of lattice mismatch, then the channel region carriers mobility of the fin field effect pipe formed improves, and makes driving electric current increase, leakage current reduces, and performance improves.
The present inventor also provides for a kind of fin field effect pipe formed based on said method, refer to Fig. 9 and Figure 11, on the basis of semiconductor device described in first embodiment (such as Fig. 8), also include: across the grid structure 108 at the top of described first sub-fin 107 and sidewall；It is positioned at the first sub-fin 107 of described grid structure 108 both sides and the source/drain region of the second sub-fin 106.
In sum, described semiconductor device includes the first sub-fin of the semiconductor substrate surface between adjacent trenches and is positioned at the described first sub-fin the second sub-fin by described first sub-fin parcel, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin, then between described first sub-fin and the second sub-fin, because of lattice mismatch, stress increases, carrier mobility in the first sub-fin and the second sub-fin is made to improve, thus improve the driving electric current of device, reduce the generation of leakage current, improve device performance.
Described fin field effect pipe has the grid structure of the fin top across above-mentioned semiconductor device and sidewall, owing between described first sub-fin and the second sub-fin, because of lattice mismatch, stress increases, stress in the channel region that then described fin contacts with grid structure increases, carrier mobility in channel region improves, thus decreasing the leakage current of device, improve the performance of fin field effect pipe.
The technique of the forming method of described semiconductor device is simple, the second sub-fin is formed in the first sub-fin layer, described first sub-fin wraps up the second sub-fin, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin layer, between the first sub-fin and the second sub-fin that are then formed, because of lattice mismatch, stress increases, the device carriers formed mobility in the first sub-fin and the second sub-fin is made to improve, it is thus possible to improve the driving electric current of device, and reduce the generation of device creepage, improve device performance.
The forming method of described fin field effect pipe is on the basis of the forming method of above-mentioned semiconductor device, it is developed across the top of described fin and the grid structure of sidewall, between the first sub-fin and the second sub-fin owing to being formed, because of lattice mismatch, stress increases, the fin then formed increases with the stress in the channel region contacted with described grid structure, the carrier mobility in channel region is then made to improve, the driving electric current of the fin field effect pipe formed increases, leakage current reduces, and performance improves.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (19)
1. a semiconductor device, it is characterised in that including:
Semiconductor substrate, has some grooves in described Semiconductor substrate；
Being positioned at the insulating barrier of described groove, the surface of described insulating barrier flushes with semiconductor substrate surface；
The fin of the semiconductor substrate surface between adjacent trenches, described fin includes: being positioned at the first sub-fin of outer layer and the second sub-fin by the first sub-fin parcel, the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin.
2. semiconductor device as claimed in claim 1, it is characterised in that the material of described first sub-fin is silicon or SiGe.
3. semiconductor device as claimed in claim 2, it is characterised in that when the material of described first sub-fin is silicon, the material of described second sub-fin is SiGe or SiGe stannum；When the material of described first sub-fin is SiGe, the material of described second sub-fin is germanium or germanium stannum.
4. semiconductor device as claimed in claim 1, it is characterised in that the thickness of described first sub-fin isThe thickness of described second sub-fin is
5. semiconductor device as claimed in claim 1, it is characterised in that the material of described insulating barrier is silicon oxide or silicon nitride.
6. semiconductor device as claimed in claim 1, it is characterised in that also include: across the grid structure at the top of described fin and sidewall；It is positioned at the source/drain region of the fin of described grid structure both sides.
7. as claimed in claim 6 semiconductor device, it is characterised in that described grid structure includes across the described top of the first sub-fin and the gate dielectric layer of sidewall and the gate electrode layer being positioned at described gate dielectric layer surface.
8. semiconductor device as claimed in claim 7, it is characterised in that the material of described gate dielectric layer is silicon oxide or high K dielectric, and the material of described gate electrode layer is polysilicon or metal.
9. the forming method of a semiconductor device, it is characterised in that including:
Thering is provided Semiconductor substrate, have some grooves, have insulating barrier in described groove in described Semiconductor substrate, the surface of described insulating barrier flushes with semiconductor substrate surface, and the semiconductor substrate surface between adjacent described groove has the first sub-fin layer；
Form mask layer on described Semiconductor substrate, insulating barrier and the first sub-fin layer surface, described mask layer exposes the first sub-fin layer surface needing to form the correspondence position of the second sub-fin；
With described mask layer for mask, remove the first sub-fin layer of segment thickness, form opening；
Forming the second sub-fin in described opening, the surface of described second sub-fin is lower than the top of described first sub-fin layer, and the lattice paprmeter of the material of described second sub-fin is more than described first sub-fin layer；
Covering semi-conducting material until flushing with the first sub-fin layer top in described second sub-fin portion surface, the semi-conducting material covered and the first sub-fin layer form the first sub-fin, and described semi-conducting material is consistent with the material of described first sub-fin layer；
After forming the first sub-fin, remove mask layer.
10. the forming method of semiconductor device as claimed in claim 9, it is characterised in that the material of described first sub-fin is silicon or SiGe.
11. the forming method of semiconductor device as claimed in claim 10, it is characterised in that when the material of described first sub-fin is silicon, the material of described second sub-fin is SiGe or SiGe stannum；When the material of described first sub-fin is SiGe, the material of described second sub-fin is germanium or germanium stannum.
12. the forming method of semiconductor device as claimed in claim 9, it is characterised in that the thickness of described first sub-fin isThe thickness of described second sub-fin is
13. the forming method of semiconductor device as claimed in claim 9, it is characterised in that described second sub-fin and the formation process covering semi-conducting material in described second sub-fin portion surface are selective epitaxial depositing operation.
14. the forming method of semiconductor device as claimed in claim 13, it is characterized in that, the described selective epitaxial growth process covering semi-conducting material in described second sub-fin portion surface is temperature is 500 ~ 800 DEG C, and air pressure is 1 holder ~ 100 holder, and reacting gas includes: silicon source gas, HCl, B2H6、H2, wherein silicon source gas, HCl and B2H6Flow be 1sccm ~ 1000sccm, H2Flow be 0.1slm ~ 50slm.
15. the forming method of semiconductor device as claimed in claim 9, it is characterised in that the material of described mask layer is silicon nitride.
16. the forming method of semiconductor device as claimed in claim 9, it is characterised in that the material of described insulating barrier is silicon oxide or silicon nitride.
17. the forming method of semiconductor device as claimed in claim 9, it is characterised in that also include: be developed across the top of described first sub-fin and the grid structure of sidewall in described first sub-fin portion surface；Source/drain region is formed in the first sub-fin and the second fin of described grid structure both sides.
18. the as claimed in claim 17 forming method of semiconductor device, it is characterised in that described grid structure includes across the described top of the first sub-fin and the gate dielectric layer of sidewall and the gate electrode layer being positioned at described gate dielectric layer surface.
19. the forming method of semiconductor device as claimed in claim 18, it is characterised in that the material of described gate dielectric layer is silicon oxide or high K dielectric, and the material of described gate electrode layer is polysilicon or metal.
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