CN103377981B - Fleet plough groove isolation structure and forming method thereof - Google Patents
Fleet plough groove isolation structure and forming method thereof Download PDFInfo
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Abstract
A kind of fleet plough groove isolation structure and forming method thereof, the formation method of wherein said fleet plough groove isolation structure comprises: provide Semiconductor substrate, forms cushion oxide layer and hard mask layer successively at semiconductor substrate surface; Remove part hard mask layer and cushion oxide layer and expose semiconductor substrate surface, with remaining hard mask layer and cushion oxide layer for mask, in Semiconductor substrate, forming some openings; Laying is formed and the material of laying is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium in opening sidewalls and bottom; The insulating barrier flushed with hard mask layer surface is formed on laying surface; Remove hard mask layer, cushion oxide layer and the insulating barrier higher than semiconductor substrate surface.The formation method of fleet plough groove isolation structure of the present invention improves the isolation effect of fleet plough groove isolation structure, and when the semiconductor substrate surface of being isolated by described fleet plough groove isolation structure forms semiconductor device, the stable work in work of described semiconductor device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of fleet plough groove isolation structure and forming method thereof.
Background technology
The developing direction of semiconductor integrated circuit is for increasing density and reducing element.In ic manufacturing technology, isolation structure is a kind of important technology, and the element formed on a semiconductor substrate adopts isolation structure to carry out mutual insulation isolation.Along with the progress of semiconductor fabrication, shallow trench isolation is from (ShallowTrench Isolation, STI) technology is because its isolation effect is good, manufacturing process is simple, instead of gradually in conventional semiconductor devices manufacturing technology, the conventional isolation structure adopting the techniques such as such as localized oxidation of silicon technique (LOCOS) to be formed.
Form the cross-sectional view of the method for fleet plough groove isolation structure as shown in Figures 1 to 5 for prior art, comprising:
Please refer to Fig. 1, provide Semiconductor substrate 10, described Semiconductor substrate 10 surface is formed with oxide liner layer 11, and described oxide liner layer 11 surface is formed with hard mask layer 12.
Please refer to Fig. 2, remove part hard mask layer 12 and cushion oxide layer 11 and expose Semiconductor substrate 10 surface, with remaining hard mask layer 12 and cushion oxide layer 11 for mask, the some openings 13 of formation described Semiconductor substrate 10 in.
Please refer to Fig. 3, adopt thermal oxidation and tropical resources technique to form silicon oxynitride layer 14 at described opening 13 sidewall and bottom.
It should be noted that, in described tropical resources technical process, the top side wall 16 of described opening 13 in Semiconductor substrate 10 is more serious by nitrogenize ground, thus silicon nitride is built up in a large number in the top side wall 16 of described opening 13.
Please refer to Fig. 4, at described opening 13(as Fig. 3) silicon oxynitride layer 14 surface fill silica until flush with hard mask layer 12, formed insulating barrier 15.
Please refer to Fig. 5, adopt CMP (Chemical Mechanical Polishing) process to remove hard mask layer 12, cushion oxide layer 11, silicon oxynitride layer 14 and the insulating barrier 15 higher than Semiconductor substrate 10 surface, until expose Semiconductor substrate 10.
But the isolation effect of the fleet plough groove isolation structure that prior art is formed is bad, cause the performance of semiconductor device instability adopting described fleet plough groove isolation structure to isolate.
The content of more fleet plough groove isolation structures please refer to the U.S. patent documents that publication number is US 7391096 B2.
Summary of the invention
The problem that the present invention solves is to provide a kind of fleet plough groove isolation structure and forming method thereof, improve the isolation effect of fleet plough groove isolation structure, and when the semiconductor substrate surface that described fleet plough groove isolation structure is isolated forms semiconductor device, the stable work in work of described semiconductor device.
For solving the problem, the invention provides a kind of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, forms cushion oxide layer at described semiconductor substrate surface, form hard mask layer on described cushion oxide layer surface;
Remove part hard mask layer and cushion oxide layer and expose semiconductor substrate surface, with remaining hard mask layer and cushion oxide layer for mask, in described Semiconductor substrate, forming some openings;
Form laying in described opening sidewalls and bottom, and the material of described laying is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium;
Form insulating barrier on described laying surface, and described insulating barrier flushes with described hard mask layer surface;
Remove hard mask layer, cushion oxide layer and the insulating barrier higher than semiconductor substrate surface.
Optionally, before formation insulating barrier, thermal oxidation is carried out to described laying, form oxide layer on described laying surface.
Optionally, the thickness of described laying is 1 ~ 10 nanometer.
Optionally, the formation process of described laying is selective epitaxial depositing operation.
Optionally, the parameter of described selective epitaxial depositing operation is temperature 600 ~ 1150 DEG C, air pressure 0.1 ~ 10Torr, 5 seconds ~ 5 hours time.
Optionally, when the material of described laying is the silicon of doping carbon, reacting gas is silicon source gas SiH4 or SiH2Cl2 and carbon-source gas C2H4.
Optionally, when the material of described laying is the silicon of doped germanium, reacting gas is silicon source gas SiH4 or SiH2Cl2 and germanium source gas GeH4.
Optionally, when the material of described laying is the silicon of doping carbon and germanium, reacting gas is silicon source gas SiH4 or SiH2Cl2, germanium source gas GeH4 and carbon-source gas C2H4.
Optionally, in the silicon of described doping carbon, doped germanium or doping carbon and germanium, the atom percentage concentration of carbon or germanium is 0.1 ~ 50%.
Optionally, the material of described cushion oxide layer is silica.
Optionally, the formation process of described cushion oxide layer is thermal oxidation technology or depositing operation.
Optionally, the material of described hard mask layer is silicon nitride.
Optionally, the formation process of described hard mask layer is depositing operation.
The invention provides a kind of formation method of fleet plough groove isolation structure, comprising:
Semiconductor substrate;
Be positioned at some openings of Semiconductor substrate;
Be positioned at the laying of described opening sidewalls and bottom, the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium;
Be positioned at the insulating barrier on the laying surface of described opening sidewalls and bottom, and described surface of insulating layer flushes with described semiconductor substrate surface.
Optionally, the thickness of described laying is 1 ~ 10 nanometer.
Optionally, in the silicon of the silicon of described doping carbon, the silicon of doped germanium or doping carbon and germanium, the atomic percent of carbon or germanium is 0.1 ~ 50%.
Compared with prior art, the present invention has the following advantages:
The formation method of fleet plough groove isolation structure described in the embodiment of the present invention, form laying, and the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium at described opening sidewalls and bottom; After formation laying, in described opening, form insulating barrier; Can while the isolation effect improving the fleet plough groove isolation structure formed, the performance of semiconductor device that the described fleet plough groove isolation structure of employing is isolated is stablized; Because the silicon crystal lattice space of described doping carbon, doped germanium or doping carbon and germanium is less, the well region ion of the semiconductor device of isolating with described fleet plough groove isolation structure is difficult to enter in insulating barrier through described laying, the isolation effect of therefore formed fleet plough groove isolation structure improves, and the semiconductor device cut-in voltage of the described fleet plough groove isolation structure isolation of employing is stablized; In addition, after described opening sidewalls and bottom form laying, do not need to form silicon oxynitride layer by tropical resources and thermal oxidation technology, then silicon nitride can not be built up in the top of described opening sidewalls, the semiconductor device of then isolating with formed fleet plough groove isolation structure operationally, the top of described opening sidewalls can not produce leakage current, therefore the stable work in work of described semiconductor device.
Fleet plough groove isolation structure described in the embodiment of the present invention, there is the laying being positioned at described opening sidewalls and bottom, and the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium, can while the isolation effect improving described fleet plough groove isolation structure, the performance of semiconductor device of isolating with described fleet plough groove isolation structure is stablized, cut-in voltage is stablized, and leakage current reduces.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the cross-sectional view that prior art forms the method for fleet plough groove isolation structure;
Fig. 6 is the schematic flow sheet of the formation method of fleet plough groove isolation structure described in the embodiment of the present invention;
Fig. 7 to Figure 11 is the cross-sectional view of the formation method of fleet plough groove isolation structure described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, the isolation effect of the fleet plough groove isolation structure that prior art is formed is bad, causes the performance of semiconductor device instability adopting described fleet plough groove isolation structure to isolate.
In order to meet the integrated and microminiaturized growth requirement of prior art, the size of semiconductor device is more and more less, thus the distance also corresponding reduction between the fleet plough groove isolation structure of isolating described semiconductor device; But, because the distance between described fleet plough groove isolation structure reduces, cause the semiconductor device of isolating with described fleet plough groove isolation structure when carrying out the ion implantation technology of well region doping, the ion injected more easily diffuses into fleet plough groove isolation structure, thus the cut-in voltage of follow-up formed semiconductor device is reduced, cannot technical indicator be reached; Wherein, the ion of the P well region doping carried out when forming nmos pass transistor is boron ion, the ion carrying out the doping of N well region when forming PMOS transistor is phosphonium ion, and the size of boron ion is less than phosphonium ion, therefore boron ion more easily diffuses into fleet plough groove isolation structure, thus the Performance Ratio PMOS transistor of the nmos pass transistor of isolating with described fleet plough groove isolation structure is more unstable.
Please continue to refer to Fig. 3, prior art enters fleet plough groove isolation structure in order to the ion diffuse preventing well region from adulterating, and adopts thermal oxidation and tropical resources technique to form silicon oxynitride layer 14 at described opening 13 sidewall and bottom; But, in the tropical resources technical process forming described silicon oxynitride layer 14, the top side wall 16 of described opening 13 in Semiconductor substrate 10 is more serious by nitrogenize ground, thus the top side wall 16 of the opening 13 of the silicon nitride making tropical resources be formed in described Semiconductor substrate 10 is built up in a large number, semiconductor device that subsequent technique is formed is caused easily to produce leakage current in described top side wall 16 position, cause the unstable properties of formed semiconductor device, the isolation effect of fleet plough groove isolation structure is bad.
In order to solve the problem, the present inventor provides a kind of formation method of fleet plough groove isolation structure, please refer to Fig. 6, is the schematic flow sheet of the formation method of fleet plough groove isolation structure described in the embodiment of the present invention, comprises step:
Step S101, provides Semiconductor substrate, forms cushion oxide layer at described semiconductor substrate surface, forms hard mask layer on described cushion oxide layer surface;
Step S102, removes part hard mask layer and cushion oxide layer and exposes semiconductor substrate surface, with remaining hard mask layer and cushion oxide layer for mask, in described Semiconductor substrate, forms some openings;
Step S103, forms laying in described opening sidewalls and bottom, and the material of described laying is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium;
Step S104, form insulating barrier, and described insulating barrier flushes on described laying surface with described hard mask layer surface;
Step S105, removes hard mask layer, cushion oxide layer and the insulating barrier higher than semiconductor substrate surface.
The formation method of fleet plough groove isolation structure described in the present embodiment adopts at described opening sidewalls and the bottom laying that to be formed with the silicon of doping carbon, doped germanium or doping carbon and germanium be material, the isolation effect of formed fleet plough groove isolation structure can be improved, the well region ion of isolating with described fleet plough groove isolation structure is made to be difficult to enter in middle insulating barrier, thus described shallow trench isolation is from respond well, and stablize with the semiconductor device cut-in voltage that described fleet plough groove isolation structure is isolated; In addition, after forming described laying, do not need to form silicon oxynitride layer by tropical resources and thermal oxidation technology again, therefore silicon nitride can not be assembled because of tropical resources technique in the top of described opening sidewalls, thus reduce with the leakage current of semiconductor device at the top of described opening sidewalls that described fleet plough groove isolation structure is isolated, stable work in work.
According to the formation method of above-mentioned fleet plough groove isolation structure, the present inventor also provides a kind of fleet plough groove isolation structure, comprising: Semiconductor substrate; Be positioned at some openings of Semiconductor substrate; Be positioned at the laying of described opening sidewalls and bottom, the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium; Be positioned at the insulating barrier on the laying surface of described opening sidewalls and bottom, and described surface of insulating layer flushes with described semiconductor substrate surface.
Fleet plough groove isolation structure described in the present embodiment, at the laying of described opening sidewalls and the bottom laying that to have with the silicon of doping carbon, doped germanium or doping carbon and germanium be material, thus the isolation effect of described fleet plough groove isolation structure improves, and stablize with the performance of semiconductor device that described fleet plough groove isolation structure is isolated, cut-in voltage is stablized, and leakage current reduces.
Below with reference to accompanying drawing, fleet plough groove isolation structure described in the embodiment of the present invention and forming method thereof is described, the cross-sectional view of the formation method that Fig. 7 to Figure 11 is fleet plough groove isolation structure described in the embodiment of the present invention.
Please refer to Fig. 7, Semiconductor substrate 100 is provided, form cushion oxide layer 101 on described Semiconductor substrate 100 surface, form hard mask layer 102 on described cushion oxide layer 101 surface.
Described Semiconductor substrate 100 is for providing workbench for subsequent technique; The material of described Semiconductor substrate 100 is silicon or silicon-on-insulator.
Described cushion oxide layer 101, for when subsequent technique removes hard mask layer 102, protects described Semiconductor substrate 100 surface injury-free; The material of described cushion oxide layer 101 is silica; The formation process of described cushion oxide layer 101 is depositing operation, is preferably chemical vapor deposition method, or thermal oxidation technology.
Protection Semiconductor substrate 100 surface described hard mask layer 102 is for forming opening, forming laying and forming insulating barrier during at subsequent technique; The material of described hard mask layer 102 is silicon nitride; The formation process of described hard mask layer 102 is depositing operation, is preferably chemical vapor deposition method.
Please refer to Fig. 8, remove part hard mask layer 102 and cushion oxide layer 101 and expose Semiconductor substrate 100 surface, with remaining hard mask layer 102 and cushion oxide layer 101 for mask, the some openings 103 of formation described Semiconductor substrate 100 in.
The technique of described removal part hard mask layer 102 and cushion oxide layer 101 is: form photoresist layer on described hard mask layer 102 surface; Exposure imaging is carried out graphically to described photoresist layer, and exposes hard mask layer 102 surface of opening 103 correspondence position that subsequent technique is formed; With the photoresist layer after graphical for mask, etch described hard mask layer 102 and cushion oxide layer 101 till exposing Semiconductor substrate 100 surface.
Described opening 103 forms fleet plough groove isolation structure for fill insulant in subsequent technique; And Semiconductor substrate 100 surface between adjacent apertures 103 is for the formation of semiconductor device; The formation process of described opening 103 is: with remaining hard mask layer 102 and cushion oxide layer 101 for mask, adopts dry etch process to form opening 103.
Please refer to Fig. 9, form laying 104 in described opening 103 sidewall and bottom, and the material of described laying 104 is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium.
Described laying 104 is for stopping that the Doped ions of the well region of the semiconductor device of being isolated by formed fleet plough groove isolation structure spreads in fleet plough groove isolation structure, therefore the isolation effect of fleet plough groove isolation structure that formed of subsequent technique is better, and when the region surface that formed fleet plough groove isolation structure is isolated forms semiconductor device, the stable work in work of described semiconductor device.
In the prior art, please refer to Fig. 3, form silicon oxynitride layer 14 to stop that described well region Doped ions is to the diffusion in fleet plough groove isolation structure at described opening 13 sidewall and bottom; But, because the technique forming described silicon oxynitride layer 14 is tropical resources technique and thermal oxidation technology, and tropical resources technique can make the top side wall 16 of described opening 13 in Semiconductor substrate 10 more serious by nitrogenize compared with other regions, thus the top side wall 16 of the described opening of silicon nitride in Semiconductor substrate 10 is built up, cause subsequent technique to be formed and easily produce leakage current in the position at described opening sidewalls top 16, the hydraulic performance decline of the semiconductor device formed with the semiconductor device on Semiconductor substrate 10 surface.
In the present embodiment, the material of described laying 104 is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium, then the lattice voids of described laying 104 is less, thus well region Doped ions not easily passs through described laying 104 enters in formed fleet plough groove isolation structure, the isolation effect of the fleet plough groove isolation structure formed is better; The formation process of described laying 104 is selective epitaxial depositing operation, and without the need to forming silicon oxynitride layer 14(as Fig. 3 by thermal oxidation and tropical resources technique), then when the region surface that formed fleet plough groove isolation structure is isolated forms semiconductor device, the stable work in work of described semiconductor device, not easily produces leakage current.
The formation process of described laying 104 is selective epitaxial depositing operation, and the parameter of described selective epitaxial depositing operation is temperature 600 ~ 1150 DEG C, air pressure 0.1 ~ 10Torr, 5 seconds ~ 5 hours time; When the material of described laying 104 is the silicon of doping carbon, reacting gas is silicon source gas SiH
4or SiH
2cl
2, and carbon-source gas C
2h
4; When the material of described laying 104 is the silicon of doped germanium, reacting gas is silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4; When the material of described laying 104 is the silicon of doping carbon and germanium, reacting gas is silicon source gas SiH
4or SiH
2cl
2, germanium source gas GeH
4, and carbon-source gas C
2h
4; The thickness of described laying 104 is 1 ~ 10 nanometer, is preferably 2 ~ 5 nanometers; When described laying 104 is blocked up, described opening 103 can be narrow, causes subsequent technique fill insulant difficulty; When described laying 104 is crossed thin, described laying 104 can be formed in the process of oxide layer at subsequent technique and be fully oxidized consumption, then cannot stop the diffusion of well region Doped ions; In the silicon of described doping carbon, doped germanium or doping carbon and germanium, the atom percentage concentration of carbon or germanium is 0.1 ~ 50%.
Please refer to Figure 10, form insulating barrier 105 on described laying 104 surface, and described insulating barrier 105 flushes with described hard mask layer 102 surface.
The material of described insulating barrier 105 is silica, and the formation process of described insulating barrier 105 is depositing operation, is preferably chemical vapor deposition method.
It should be noted that, before forming insulating barrier 105 by depositing operation, by carrying out thermal oxidation to described laying 104, form oxide layer (not shown) on described laying 104 surface, and the material of described oxide layer can also be silica; After formation oxide layer, in described opening 103, fill full insulating material by depositing operation form insulating barrier 105; The insulating material of then being filled by depositing operation is finer and close, defect in the insulating barrier 105 formed is less, thus the well region Doped ions of being isolated by formed fleet plough groove isolation structure is difficult to enter in described fleet plough groove isolation structure, the isolation performance of the fleet plough groove isolation structure formed is better.
Please refer to Figure 11, remove hard mask layer 102, cushion oxide layer 101 and the insulating barrier 105 higher than Semiconductor substrate 100 surface, thus form fleet plough groove isolation structure.
Described removal hard mask layer 102, cushion oxide layer 101 and the technique higher than the insulating barrier 105 on Semiconductor substrate 100 surface are CMP (Chemical Mechanical Polishing) process, dry etch process or wet-etching technology, are preferably CMP (Chemical Mechanical Polishing) process.
It should be noted that, after the described fleet plough groove isolation structure of formation, form semiconductor device, such as PMOS transistor, nmos pass transistor, CMOS and flash memory cell etc. on Semiconductor substrate 100 surface isolated by described fleet plough groove isolation structure.
The formation method of fleet plough groove isolation structure described in the present embodiment is by forming laying 104 at described opening 103 sidewall and bottom, and the material of described laying 104 is the silicon of doping carbon, doped germanium or doping carbon and germanium; After the described laying 104 of formation, in described opening 103, form insulating barrier 105, thus form fleet plough groove isolation structure; Doped ions in the well region of being isolated by formed fleet plough groove isolation structure is difficult to diffuse in fleet plough groove isolation structure by described laying 104, and therefore the isolation performance of described fleet plough groove isolation structure improves; In addition, the semiconductor device workability formed on Semiconductor substrate 100 surface that described fleet plough groove isolation structure is isolated can be stablized, and leakage current reduces; And the formation method technique of described fleet plough groove isolation structure simple, be easy to operation, be applicable to large-scale production.
The embodiment of the present invention also provides a kind of fleet plough groove isolation structure formed according to the formation method of above-mentioned fleet plough groove isolation structure, please refer to Figure 11, comprising: Semiconductor substrate 100; Be positioned at some opening (not shown) of Semiconductor substrate 100; Be positioned at the laying 104 of described opening sidewalls and bottom, the material of described laying 104 is the silicon of doping carbon, doped germanium or doping carbon and germanium; Be positioned at the insulating barrier 105 on laying 104 surface of described opening sidewalls and bottom, and described insulating barrier 105 surface flushes with described Semiconductor substrate 100 surface.
The thickness of described laying 104 is 1 ~ 10 nanometer, is preferably 2 ~ 5 nanometers; When described laying 104 is blocked up, described opening can be narrow, causes the defect in insulating barrier 105 more; When described laying 104 is crossed thin, then cannot stop that well region Doped ions spreads in formed fleet plough groove isolation structure; The material of described laying 104 is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium, and carbon or the atomic percent of germanium in the silicon of doping carbon or the silicon of doped germanium are 0.1 ~ 50%; Semiconductor substrate 100 surface between adjacent apertures is for the formation of semiconductor device.
Fleet plough groove isolation structure described in the present embodiment is formed with the laying 104 being positioned at described opening sidewalls and bottom, and the material of described laying 104 is the silicon of doping carbon, doped germanium or doping carbon and germanium; Because the lattice voids of described laying 104 is less, the isolation effect of described fleet plough groove isolation structure is better; In addition, at the semiconductor device on Semiconductor substrate 100 surface isolated by described fleet plough groove isolation structure, its cut-in voltage is stable, leakage current is less, stable work in work.
In sum, the formation method of fleet plough groove isolation structure described in the embodiment of the present invention, form laying, and the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium at described opening sidewalls and bottom; After formation laying, in described opening, form insulating barrier; Can while the isolation effect improving the fleet plough groove isolation structure formed, the performance of semiconductor device that the described fleet plough groove isolation structure of employing is isolated is stablized; Because the silicon crystal lattice space of described doping carbon, doped germanium or doping carbon and germanium is less, the well region ion of the semiconductor device of isolating with described fleet plough groove isolation structure is difficult to enter in insulating barrier through described laying, the isolation effect of therefore formed fleet plough groove isolation structure improves, and the semiconductor device cut-in voltage of the described fleet plough groove isolation structure isolation of employing is stablized; In addition, after described opening sidewalls and bottom form laying, do not need to form silicon oxynitride layer by tropical resources and thermal oxidation technology, then silicon nitride can not be built up in the top of described opening sidewalls, the semiconductor device of then isolating with formed fleet plough groove isolation structure operationally, the top of described opening sidewalls can not produce leakage current, therefore the stable work in work of described semiconductor device.
Fleet plough groove isolation structure described in the embodiment of the present invention, there is the laying being positioned at described opening sidewalls and bottom, and the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium, can while the isolation effect improving described fleet plough groove isolation structure, the performance of semiconductor device of isolating with described fleet plough groove isolation structure is stablized, cut-in voltage is stablized, and leakage current reduces.
Although the embodiment of the present invention is described above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a formation method for fleet plough groove isolation structure, is characterized in that, comprising:
Semiconductor substrate is provided, forms cushion oxide layer at described semiconductor substrate surface, form hard mask layer on described cushion oxide layer surface;
Remove part hard mask layer and cushion oxide layer and expose semiconductor substrate surface, with remaining hard mask layer and cushion oxide layer for mask, in described Semiconductor substrate, forming some openings;
Form laying in described opening sidewalls and bottom, and the material of described laying is the silicon of the silicon of doping carbon, the silicon of doped germanium or doping carbon and germanium;
Thermal oxidation is carried out to described laying, forms oxide layer on described laying surface;
After the described oxide layer of formation, form insulating barrier on described oxide layer surface, and described insulating barrier flushes with described hard mask layer surface;
Remove hard mask layer, cushion oxide layer and the insulating barrier higher than semiconductor substrate surface.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the thickness of described laying is 1 ~ 10 nanometer.
3. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the formation process of described laying is selective epitaxial depositing operation.
4. the formation method of fleet plough groove isolation structure as claimed in claim 3, it is characterized in that, the parameter of described selective epitaxial depositing operation is temperature 600 ~ 1150 DEG C, air pressure 0.1 ~ 10Torr, 5 seconds ~ 5 hours time.
5. the formation method of fleet plough groove isolation structure as claimed in claim 3, it is characterized in that, when the material of described laying is the silicon of doping carbon, reacting gas is silicon source gas SiH
4or SiH
2cl
2, and carbon-source gas C
2h
4.
6. the formation method of fleet plough groove isolation structure as claimed in claim 3, it is characterized in that, when the material of described laying is the silicon of doped germanium, reacting gas is silicon source gas SiH
4or SiH
2cl
2, and germanium source gas GeH
4.
7. the formation method of fleet plough groove isolation structure as claimed in claim 3, it is characterized in that, when the material of described laying is the silicon of doping carbon and germanium, reacting gas is silicon source gas SiH
4or SiH
2cl
2, germanium source gas GeH
4, and carbon-source gas C
2h
4.
8. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, in the silicon of described doping carbon, doped germanium or doping carbon and germanium, the atom percentage concentration of carbon or germanium is 0.1 ~ 50%.
9. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the material of described cushion oxide layer is silica.
10. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the formation process of described cushion oxide layer is thermal oxidation technology or depositing operation.
The formation method of 11. fleet plough groove isolation structures as claimed in claim 1, it is characterized in that, the material of described hard mask layer is silicon nitride.
The formation method of 12. fleet plough groove isolation structures as claimed in claim 1, it is characterized in that, the formation process of described hard mask layer is depositing operation.
13. 1 kinds of fleet plough groove isolation structures, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at some openings of Semiconductor substrate;
Be positioned at the laying of described opening sidewalls and bottom, the material of described laying is the silicon of doping carbon, doped germanium or doping carbon and germanium;
Be positioned at the oxide layer on described laying surface;
Be positioned at the insulating barrier on the oxide layer surface of described opening sidewalls and bottom, and described surface of insulating layer flushes with described semiconductor substrate surface.
14. fleet plough groove isolation structures as claimed in claim 13, it is characterized in that, the thickness of described laying is 1 ~ 10 nanometer.
15. fleet plough groove isolation structures as claimed in claim 13, is characterized in that, in the silicon of the silicon of described doping carbon, the silicon of doped germanium or doping carbon and germanium, the atom percentage concentration of carbon or germanium is 0.1 ~ 50%.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308785A (en) * | 1992-01-24 | 1994-05-03 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
| US7391096B2 (en) * | 2003-06-18 | 2008-06-24 | Dongbu Electronics Co., Ltd. | STI structure |
| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
-
2012
- 2012-04-28 CN CN201210134249.2A patent/CN103377981B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308785A (en) * | 1992-01-24 | 1994-05-03 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
| US7391096B2 (en) * | 2003-06-18 | 2008-06-24 | Dongbu Electronics Co., Ltd. | STI structure |
| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
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