CN109411414B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN109411414B
CN109411414B CN201710711275.XA CN201710711275A CN109411414B CN 109411414 B CN109411414 B CN 109411414B CN 201710711275 A CN201710711275 A CN 201710711275A CN 109411414 B CN109411414 B CN 109411414B
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forming
source
side wall
layer
fin
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CN109411414A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Abstract

The invention provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: forming first source drain grooves in the first dummy gate structure and the first fin portions on two sides of the first side wall respectively; forming a first semiconductor layer on the side wall and the bottom of the first source drain groove; and forming a first source-drain doping layer which fills the first source-drain groove on the first semiconductor layer. According to the forming method, the first semiconductor layer is formed between the first source drain doping layer and the first fin portion, the risk of junction leakage current generated between the first source drain doping layer and the first fin portion is reduced, and therefore electrical stability and reliability of the semiconductor structure are improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are widely used as the most basic semiconductor devices, and the conventional planar transistors have weak control capability on channel current, short channel effect is generated, leakage current is caused, and finally the electrical performance of the semiconductor devices is affected.
In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source and drain doped regions are positioned in the fin parts at two sides of the grid structure.
However, as the density and size of semiconductor devices increase, the difficulty of the fin field effect transistor fabrication process increases, and the performance of the formed fin field effect transistor deteriorates and the reliability thereof decreases.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, wherein a first semiconductor layer is formed between a first source drain doping layer and a first fin portion, so that the overall performance of the semiconductor structure is improved, and the improvement of the integration level of a device is facilitated.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first area, the first area of the substrate is provided with a first fin part, and an isolation structure is positioned on the substrate and covers partial side walls of the first fin part; forming a first dummy gate structure crossing the first fin portion, wherein the first dummy gate structure is located on a part of the isolation structure and covers a part of the side wall and the top surface of the first fin portion; forming a first side wall on the side wall of the first pseudo gate structure; forming first source drain grooves in the first dummy gate structure and the first fin portions on two sides of the first side wall respectively; forming a first semiconductor layer on the side wall and the bottom of the first source drain groove; and forming a first source-drain doping layer which fills the first source-drain groove on the first semiconductor layer.
Optionally, the thickness of the first semiconductor layer is 30 angstroms to 200 angstroms.
Optionally, the material of the first semiconductor layer includes silicon, germanium, silicon carbide or silicon germanium.
Optionally, the forming process of the first semiconductor layer includes an epitaxial growth process.
Optionally, the first source-drain doping layer has doping ions, and the concentration of the doping ions is 8.0E20atom/cm3～1.8E21atom/cm3。
Optionally, the forming process of the first source-drain doping layer includes an epitaxial growth process.
Optionally, before forming the first dummy gate structure, the method further includes: and forming a pseudo gate oxide layer covering the side wall and the top surface of the first fin part on the isolation structure.
Optionally, the substrate further includes a second region, and the second region of the substrate has a second fin portion thereon; the isolation structure also covers part of the side wall of the second fin part; the pseudo gate oxide layer also covers the side wall and the top surface of the second fin part; forming a second pseudo gate structure crossing the second fin portion, wherein the second pseudo gate structure is located on a part of the isolation structure and covers a part of the side wall and the top surface of the second fin portion; forming a second side wall on the side wall of the second pseudo gate structure; forming second source drain grooves in the second dummy gate structure and the second fin portions on two sides of the second side wall respectively; and filling a second source-drain doping layer in the second source-drain groove.
Optionally, before forming the first semiconductor layer on the sidewall and the bottom of the first source-drain groove, the method further includes: and forming a mask layer on the side wall and the bottom of the second source drain groove.
Optionally, the thickness of the mask layer is 10 angstroms to 40 angstroms.
Optionally, the material of the mask layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
Optionally, the forming process of the mask layer includes a deposition process or an oxidation process.
Optionally, after forming the first semiconductor layer, the method further includes: and removing the mask layer.
Optionally, after removing the mask layer, the method further includes: and forming a second semiconductor layer on the first semiconductor layer and the side wall and the bottom of the second source drain groove.
Optionally, the thickness of the second semiconductor layer is 10 angstroms to 80 angstroms.
The present invention also provides a semiconductor structure comprising: the substrate comprises a first area, a first fin portion located on the first area and an isolation structure located on the substrate, wherein the isolation structure covers partial side walls of the first fin portion; the pseudo gate oxide layer covers the partial side wall and the top surface of the first fin part; the first dummy gate structure crosses over the first fin part, is positioned on part of the isolation structure and covers part of the side wall and the top surface of the first fin part; the first side wall is positioned on the side wall of the first pseudo gate structure; the first source-drain doping layers are respectively positioned in the first dummy gate structure and the first fin parts on two sides of the first side wall; and the first semiconductor layer is positioned between the first source drain doping layer and the first fin portion.
Optionally, the thickness of the first semiconductor layer is 30 angstroms to 200 angstroms.
Optionally, the substrate further includes a second region and a second fin portion located on the second region; the isolation structure also covers part of the side wall of the second fin part; the pseudo gate oxide layer also covers the side wall and the top surface of the second fin part; a second dummy gate structure crossing the second fin portion, wherein the second dummy gate structure is located on a part of the isolation structure and covers a part of the side wall and the top surface of the second fin portion; a second side wall positioned on the side wall of the second pseudo gate structure; and the second source-drain doping layers are respectively positioned in the second dummy gate structure and the second fin parts at two sides of the second side wall.
Optionally, the method further includes: and the second semiconductor layer is positioned on the first semiconductor layer and between the second source drain doping layer and the second fin portion.
Optionally, the thickness of the second semiconductor layer is 10 angstroms to 80 angstroms.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, due to the instant enhanced diffusion effect, the doped ions of the first source-drain doped layer transversely diffuse into the first fin part, so that the effective channel length of the semiconductor structure is shortened, and the short channel effect is caused; the first semiconductor layer is located between the first source-drain doping layer and the first fin portion and used for blocking diffusion of the doped ions, effectively improving a short channel effect, improving breakdown voltage of the first source-drain doping layer, reducing leakage current of the semiconductor structure and improving electrical performance of the semiconductor structure.
Further, the material of the first semiconductor layer comprises silicon, germanium, silicon carbide or silicon germanium, first source-drain grooves are formed in the first dummy gate structure and the first fin portions on two sides of the first side wall respectively, the crystal orientation of the side wall of each first source-drain groove is different from that of the bottom of the corresponding first source-drain groove, and the first semiconductor layer is formed on the side wall and the bottom of each first source-drain groove, so that the first source-drain doping layer and the first fin portions are prevented from being defective due to dislocation; meanwhile, stress is introduced into a channel of the semiconductor structure by the first semiconductor layer, so that the electric leakage phenomenon caused by the interface defect of the first source-drain doped layer is inhibited, and the electrical performance of the semiconductor structure is improved.
Furthermore, the forming process of the first semiconductor layer comprises an epitaxial growth process, the epitaxial growth process can avoid introducing lattice damage into the first fin portion, the thickness of the formed first semiconductor layer can be accurately controlled, meanwhile, the surface flatness of the formed first semiconductor layer is good, the electric leakage phenomenon caused by the interface defect of the first source drain doping layer is inhibited, and therefore the electrical characteristics of the semiconductor device are improved.
Further, the thickness of the first semiconductor layer is 30 to 200 angstroms. When the semiconductor device is in a high-voltage working state, the junction barrier of the first source-drain doping layer is easily caused to be lowered under the influence of a high-strength electric field, so that the threshold voltage of the semiconductor device is lowered; and adjusting the capacitance between the first source-drain doping layer and the subsequently formed first gate structure through the thickness of the first semiconductor layer, so as to avoid the risk of reduction of threshold voltage and improve the electrical characteristics of the semiconductor device.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2to 11 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background art, as the density of semiconductor devices increases and the size decreases, the performance of the formed semiconductor structure deteriorates and the reliability decreases.
In order to improve the forward conduction characteristic of the semiconductor device, the concentration of doped ions in the source and drain doped regions is correspondingly increased, so that the risk of junction leakage current is increased, and the electrical characteristic and the stability of the semiconductor device are reduced. The following description will be made with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor structure, which includes: the semiconductor device comprises a substrate 100, a fin 110 located on the substrate, and an isolation structure 102 located on the substrate 100, wherein the isolation structure 102 covers part of the sidewall of the fin 110; a gate structure 111 crossing the fin 110, wherein the gate structure 111 is located on a portion of the isolation structure 102 and covers a portion of the sidewall and the top surface of the fin 110; a sidewall spacer 112 on a sidewall of the gate structure 111; source-drain doped regions 113 in the fin 110 at both sides of the gate structure 111; and the dielectric structure 103 is located on the isolation structure 102, and the dielectric structure 103 covers the source-drain doped region 113 and exposes the top surfaces of the sidewall 112 and the gate structure 111.
As the density of semiconductor devices increases and the size thereof decreases, the charge sharing effect (SCE) becomes more and more significant, and thus the Short Channel Effect (SCE) becomes more serious. In order to effectively suppress the short channel effect and improve the sub-threshold slope (SS), the junction depth of the source/drain doped region 113 must be reduced with the reduction of the semiconductor device, which results in the increase of the sheet resistance (sheet resistance) of the source/drain doped region 113, and thus the doping concentration of the source/drain doped region 113 must be increased.
However, due to the concentration of dopant ions in the source/drain doped region 113 (up to 7E18 atom/cm)3) The concentration difference of the doped ions exists between the source/drain doped region 113 and the fin portion 110, and the doped ions are diffused from the high-concentration source/drain doped region 113 to the low-concentration gate structure 111, so that the effective channel length of the semiconductor structure is shortened, and a short channel effect is caused.
Meanwhile, the forming process of the source/drain doped region 113 includes: forming a source-drain groove (not shown) in the fin 110 located at two sides of the gate structure 111 and the sidewall 112, and forming a source-drain doped region 113 in the source-drain groove; the source-drain grooves formed by etching have a difference in crystal orientation between the sidewalls and the bottom thereof, which results in an interface defect of the source-drain doped region 113, thereby causing a risk of junction leakage current (junction leakage).
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, wherein first source drain grooves are formed in a first dummy gate structure and first fin parts on two sides of a first side wall respectively; forming a first semiconductor layer on the side wall and the bottom of the first source drain groove; and forming a first source-drain doping layer which fills the first source-drain groove on the first semiconductor layer. According to the forming method, the first semiconductor layer is formed between the first source drain doping layer and the first fin portion, and therefore electrical stability and reliability of the semiconductor structure are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2to 11 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, where the substrate 200 includes a first region a, a first fin 210 is disposed on the first region a of the substrate 200, and an isolation structure 201 is disposed on the substrate 200, where the isolation structure 201 covers a portion of a sidewall of the first fin 210.
The substrate 200 further includes a second region B, the second region B of the substrate 200 having a fin 220 thereon; the isolation structure 201 also covers a portion of the sidewalls of the second fin 220.
In one embodiment, the first region a is used for forming peripheral devices, and the second region B is used for forming core devices; the density of core devices of the second area B is greater than that of peripheral devices of the first area A, and the characteristic Dimension (CD for short) of the core devices is smaller than that of the peripheral devices.
The substrate 200 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like; the substrate 200 may be a bulk material or may be a composite structure, such as silicon-on-insulator; the substrate 200 may also be other semiconductor materials, not to mention a few examples.
In one embodiment, the first fin portion 210 and the second fin portion 220 are formed by patterning the substrate 200. Alternatively, a fin material layer is formed on the substrate 200, and the first fin portion 210 and the second fin portion 220 are formed by patterning the fin material layer.
In an embodiment, under the influence of the etching process, the bottom width of the first fin portion 210 is greater than the top width of the first fin portion 210, and the bottom width of the second fin portion 220 is greater than the top width of the second fin portion 220. The bottom width and the top width of the first fin portion 210 refer to the dimension in the direction parallel to the surface of the substrate 200 and perpendicular to the extension direction of the first fin portion 210, and the bottom width and the top width of the second fin portion 220 refer to the dimension in the direction parallel to the surface of the substrate 200 and perpendicular to the extension direction of the second fin portion 220.
In this embodiment, the top width of the first fin portion 210 is equal to the bottom width of the first fin portion 210, and the top width of the second fin portion 220 is equal to the bottom width of the second fin portion 220.
The step of forming the isolation structure 201 includes: forming an initial isolation film on the substrate 200, wherein the initial isolation film covers the side walls of the first fin portion 210 and the second fin portion 220; planarizing the initial isolation film; the initial isolation film is etched back until portions of the sidewalls and top surfaces of the first fin 210 and the second fin 220 are exposed.
The material of the initial isolation film comprises silicon oxide or silicon nitride.
The forming process of the initial isolation film comprises a deposition process.
In an embodiment, before forming the isolation structure 201, a liner oxide layer (not shown) covering sidewalls of the first fin portion 210 and sidewalls of the second fin portion 220 is further formed on the substrate 200, and the liner oxide layer is located between the isolation structure 230 and the first fin portion 210 and between the isolation structure 230 and the second fin portion 220, so as to improve interface bonding strength between the first fin portion 210 and the isolation structure 230 and between the second fin portion 220 and the isolation structure 230.
The forming process of the liner oxide layer comprises a deposition process or an oxidation process.
Referring to fig. 3 and 4, fig. 3 is a schematic structural diagram based on fig. 2, and fig. 4 is a schematic structural diagram along a cutting line M-M1 of fig. 3, a first dummy gate structure 211 crossing the first fin 210 is formed, where the first dummy gate structure 211 is located on a portion of the isolation structure 201 and covers a portion of the sidewall and the top surface of the first fin 210.
In this embodiment, a second dummy gate structure 221 crossing the second fin portion 220 is further formed, where the second dummy gate structure 221 is located on a portion of the isolation structure 201 and covers a portion of a sidewall and a top surface of the second fin portion 221.
In this embodiment, before forming the first dummy gate structure 211, a dummy gate oxide layer 202 covering a portion of the sidewall and the top surface of the first fin 210 is further formed on the isolation structure 201; the dummy gate oxide layer 202 also covers the sidewalls and top surface of the second fin portion 220.
In another embodiment, before forming the isolation structure 201, the dummy gate oxide layer 202 is formed on the substrate 200, and the dummy gate oxide layer 202 covers the sidewalls and the top surface of the first fin portion 210 and the sidewalls and the top surface of the second fin portion 220.
The dummy gate oxide layer 202 is used for protecting the first fin portion 210 and the second fin portion 220 when a dummy gate structure is removed in the following.
The material of the dummy gate oxide layer 202 includes silicon oxide.
The forming process of the dummy gate oxide layer 202 includes a deposition process or an oxidation process.
In one embodiment, the process for forming the dummy gate oxide layer 202 is an In-situ steam Generation (ISSG); the thickness of the dummy gate oxide layer 202 is 20-60 angstroms. The parameters of the in-situ steam generation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 10 seconds-5 minutes. The dummy gate oxide layer 202 formed by the in-situ steam generation process has good step coverage capability, the formed dummy gate oxide layer 202 can be tightly covered on the side walls and the top surfaces of the first fin portion 210 and the second fin portion 220, and the formed dummy gate oxide layer 202 is uniform in thickness.
In another embodiment, the forming process of the dummy gate oxide layer 202 is a chemical oxidation process; the steps of the chemical oxidation process include: oxidizing the side walls and the top surfaces of the first fin portion 210 and the second fin portion 220 by using an aqueous solution into which ozone is introduced, and forming a pseudo gate oxide layer 202 on the side walls and the surfaces of the first fin portion 210 and the second fin portion 220. Wherein, in the water solution with the ozone, the concentration of the ozone in the water is 1 to 15 percent.
In this embodiment, the first dummy gate structure 211 includes a first dummy gate dielectric layer 212 crossing the first fin portion 210 and a first dummy gate electrode layer 213 on the first dummy gate dielectric layer 212; the second dummy gate structure 221 includes a second dummy gate dielectric layer 222 crossing the second fin portion 220 and a second dummy gate electrode layer 223 on the second dummy gate dielectric layer 222. The first dummy gate dielectric layer 212 is located on a partial surface of the isolation structure 201 in the first region a, and covers a partial top surface and a partial sidewall surface of the first fin portion 210; the second dummy gate dielectric layer 222 is located on a portion of the surface of the isolation structure 201 in the second region B, and covers a portion of the top surface and a portion of the sidewall surface of the second fin 220.
The material of the first dummy gate dielectric layer 212 and the second dummy gate dielectric layer 222 includes silicon oxide, silicon nitride or silicon oxynitride. The material of the first dummy gate electrode layer 213 and the second dummy gate electrode layer 223 includes silicon, amorphous silicon, polysilicon, doped polysilicon, a polysilicon-germanium alloy material, or a polysilicon metal silicide material.
Referring to fig. 5, fig. 5 is a schematic structural diagram based on fig. 4, and a first sidewall 214 is formed on a sidewall of the first dummy gate structure 211.
In this embodiment, a second sidewall 224 is also formed on the sidewall of the second dummy gate structure 221.
The roles of the first side wall 214 and the second side wall 224 include: when the first source-drain doping layer and the second source-drain doping layer are formed subsequently, the first sidewall 214 prevents the first fin portion 210 from being doped, and the second sidewall 224 prevents the second fin portion 220 from being doped.
The forming steps of the first side wall 214 and the second side wall 224 include: forming a sidewall film covering part of the sidewall and part of the top surface of the first fin 210, part of the sidewall and part of the top surface of the second fin 220, the dummy gate oxide layer 202, the top surface of the first dummy gate structure 211 and the top surface of the second dummy gate structure 221 on the isolation structure 201; the sidewall film is etched back until the top surface of the first dummy gate structure 211 and the top surface of the second dummy gate structure 221 are exposed, so as to form a first sidewall 214 and a second sidewall 224, respectively.
The forming process of the side wall film comprises a deposition process.
The material of the side wall film comprises one or more of silicon oxide, silicon nitride and silicon oxynitride.
In an embodiment, the first sidewall 214 and the second sidewall 224 further cover the sidewall of the first fin 210 and the sidewall of the second fin 220, so as to prevent the dummy gate oxide layer 202 from being damaged in a subsequent process of forming a first source drain recess and a second source drain recess.
Referring to fig. 6, first source-drain grooves 215 are respectively formed in the first fin portions 210 on two sides of the first dummy gate structure 211 and the first sidewall 214.
In this embodiment, second source-drain grooves 225 are further formed in the second dummy gate structure 221 and the second fin portions 220 on two sides of the second sidewall 224, respectively.
The first source-drain groove 215 is located at two sides of the first dummy gate structure 211 and the first sidewall 214, and provides a growth space for forming a first source-drain doping layer subsequently; the second source-drain grooves 225 are located on two sides of the second dummy gate structure 221 and the second sidewall 224, and provide a growth space for subsequently forming a second source-drain doping layer.
In this embodiment, the forming steps of the first source-drain groove 215 and the second source-drain groove 225 include: forming a patterning layer covering part of the side wall and part of the top surface of the first fin portion 210, part of the side wall and part of the top surface of the second fin portion 220, the dummy gate oxide layer 202, the top surface of the first dummy gate structure 211 and the top surface of the second dummy gate structure 221 on the isolation structure 201, wherein the patterning layer defines the positions and the shapes of the first source drain groove 215 and the second source drain groove 225; and etching the first fin portion 210 and the second fin portion 220 by using the patterning layer as a mask to form the first source drain groove 215 and the second source drain groove 225.
The process for etching the first fin portion 210 and the second fin portion 220 includes one or two of a wet etching process and a dry etching process.
In an embodiment, the first source-drain groove 215 and the second source-drain groove 225 are formed by a dry etching process, and the parameters include: the gas used includes a fluorocarbon-based gas.
In another embodiment, a first source-drain groove is formed first, and then a second source-drain groove is formed, and the distance between the bottom of the first source-drain groove and the surface of the substrate is greater than the distance between the bottom of the second source-drain groove and the surface of the substrate. The method has the advantages that when the first region is used as the peripheral region of the semiconductor structure, as the density degree of the semiconductor structure is improved, the channel width between the subsequently formed first source-drain doping layers is smaller and smaller, the depletion layer width of the first source-drain doping layers extends towards the channel direction along with the increase of the voltage, and therefore the distance between the bottom of the first source-drain groove and the substrate is increased, and the risk of causing the punch-through effect is reduced.
In this embodiment, before forming the first semiconductor layer on the sidewall and the bottom of the first source-drain groove, the method further includes: and forming a mask layer on the side wall and the bottom of the second source drain groove.
Referring to fig. 7, a mask layer 204 is formed on the sidewalls and bottom of the second source/drain recess 225.
In the subsequent formation of the first semiconductor layer on the sidewall and the bottom of the first source-drain groove 215, the mask layer 204 is used to protect the sidewall and the bottom surface of the second source-drain groove 225.
The material of the mask layer 204 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
The forming process of the mask layer 204 includes a deposition process or an oxidation process.
The thickness of the mask layer 204 is 10to 40 angstroms. The method has the advantages that the mask layer 204 is too thin, so that the film thickness is easily uneven, and effective protection cannot be formed on the side wall and the bottom of the second source drain groove; the thickness of the mask layer 204 is too thick, which results in process waste.
In this embodiment, the mask layer 204 is further located on the sidewall and the top surface of the second sidewall 224 and the top surface of the second dummy gate structure 221; the forming step of the mask layer 204 includes: forming a mask material film (not shown) on the isolation structure 201, wherein the mask material film covers the sidewalls and the bottom of the first source-drain groove 215, the sidewalls and the bottom of the second source-drain groove 225, the sidewalls and the top surface of the first sidewall 214, the sidewalls and the top surface of the second sidewall 224, the top surface of the first dummy gate structure 211, the top surface of the second dummy gate structure 221, a part of the sidewalls and the top surface of the first fin 210, and a part of the sidewalls and the top surface of the second fin 220; forming a patterning layer (not shown) on the mask material film, wherein the patterning layer exposes the isolation layer 201, the first source/drain grooves 215, the first dummy gate structures 211, and the first sidewalls 214; and etching the mask material film by taking the patterning layer as a mask until the side wall and the top surface of the first source-drain groove 215 are exposed.
In an embodiment, the patterned layer only exposes the first source-drain recess 215, and the formed mask layer 204 is further located on the isolation layer 201, the top surface of the first dummy gate structure 211, and the sidewalls and the top surface of the first sidewalls 214.
In an embodiment, the mask material film is formed on the side wall and the bottom of the first source-drain groove and the side wall and the bottom of the second source-drain groove by an oxidation process. The parameters of the oxidation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 10 seconds-5 minutes. The mask material film formed by the oxidation process has good step coverage capability and tightly covers the sidewall and the bottom surface of the first source drain groove 215 and the sidewall and the bottom surface of the second source drain groove 225.
In another embodiment, the mask material film is formed using a chemical oxidation process; the steps of the chemical oxidation process include: and oxidizing the side wall and the bottom surface of the first source-drain groove 215 and the side wall and the bottom surface of the second source-drain groove 225 by adopting an aqueous solution into which ozone is introduced, and forming a mask material film on the side wall and the bottom surface of the first source-drain groove 215 and the side wall and the bottom surface of the second source-drain groove 225. Wherein, in the water solution with the ozone, the concentration of the ozone in the water is 1 to 15 percent.
In another embodiment, before forming the mask material film, the sidewalls and bottom surfaces of the first source drain recess 215 and the second source drain recess 225 are further etched to remove a native oxide layer (not shown). The natural oxide layer is formed on the surface of a semiconductor material in the semiconductor manufacturing process. The native oxide layer has uncertainty in thickness and quality and therefore needs to be removed. Removing the natural oxide layer by wet etching, wherein the wet etching process adopts HF solution and NH3Mixed solution with HF, or NF3And a mixed solution of HF. In the wet etching process using the solution, the etching solution reacts only with the native oxide layer, and does not damage the substrate 200 and other semiconductor structures.
Referring to fig. 8, a first semiconductor layer 205 is formed on the sidewall and the bottom of the first source-drain recess 215.
The material of the first semiconductor layer 205 includes silicon, germanium, silicon carbide, or silicon germanium; forming first source-drain grooves 215 in the first fin portions 210 on two sides of the first dummy gate structure 211 and the first side wall 214 respectively, wherein the crystal orientation of the side wall of each first source-drain groove 215 is different from that of the bottom of the first source-drain groove, and the first semiconductor layer 205 is formed on the side wall and the bottom of each first source-drain groove 215, so that defects caused by dislocation between the first source-drain doped layer formed subsequently and the first fin portions 210 are avoided; meanwhile, stress is introduced into a channel of the semiconductor structure by the first semiconductor layer 205, so that the electric leakage phenomenon caused by the interface defect of the first source-drain doped layer is inhibited, and further the electrical performance of the semiconductor structure is improved.
The forming process of the first semiconductor layer 205 includes an epitaxial growth process; the epitaxial growth process can avoid introducing lattice damage into the first fin portion 210, can accurately control the thickness of the formed first semiconductor layer 205, has good surface flatness of the formed first semiconductor layer 205, and inhibits a current leakage phenomenon caused by a first source-drain doped layer interface defect, thereby improving the electrical characteristics of the semiconductor device.
The thickness of the first semiconductor layer 205 is 30 to 200 angstroms. The method has the advantages that when the semiconductor structure is in a high-voltage working state, junction barrier lowering of a first source-drain doping layer formed subsequently is easily caused under the influence of a high-strength electric field, so that the threshold voltage of the semiconductor structure is reduced; the capacitance between the first source-drain doped layer and the first fin portion 210 is adjusted by the thickness of the first semiconductor layer 205, so that the risk of lowering the threshold voltage is avoided, and the electrical characteristics of the semiconductor structure are improved.
In one embodiment, the first semiconductor layer 205 is a single layer structure, and the process gas for forming the first semiconductor layer includes one or more of a silicon-containing source gas, a silicon-germanium-containing gas, and a carbon-containing source gas. The silicon containing source gas comprises SiH4、SiH2Cl2、SiHCl3One or more combinations of (a); the silicon-germanium containing gas comprises GeH4(ii) a The carbon containing source gas comprises C2H4、H3Si-CH2-SiH2-CH3One or a combination of both. In another embodiment, the process gas further comprises H2And HCl, the H2As carrier gas, HCl is used as selective gas.
In another embodiment, the first semiconductor layer 205 is a multilayer structure having an n-layer stack structure in which a SiGe layer and a Si layer are sequentially stacked, where n is an integer greater than or equal to 2; in one embodiment, the multilayer structure is a p-layer laminated structure formed by sequentially laminating a SiGe layer and a SiC layer, wherein p is an integer greater than or equal to 2. Compared with a single-layer structure, the multi-layer structure can effectively inhibit the diffusion of the doping ions of the first source-drain doping layer formed subsequently.
In an embodiment, before forming the first semiconductor layer 205, implanting Ge metal into the sidewall and the bottom of the first source-drain groove 215, and annealing the Ge metal and the first fin made of Si to form a SiGe alloy; and forming the first semiconductor layer on the SiGe alloy, thereby avoiding direct contact between a first source drain doping layer formed subsequently and the first fin part, and introducing stress into a channel region, thereby improving the phenomenon of junction leakage current and further improving the electrical performance of the semiconductor structure.
In this embodiment, the process parameters of the epitaxial growth process include: the process gas comprises H2HCl, DCS (dichlorosilane), and B2H6Said H is2The gas flow of (A) is 10sccm to 3000sccm, the gas flow of HCl is 10sccm to 200sccm, the gas flow of DCS is 20sccm to 2000sccm, and B2H6The gas flow rate is 5 sccm-100 sccm, the process temperature is 500-800 ℃, and the pressure is 8-300 torr.
In this embodiment, after forming the first semiconductor layer, the method further includes: and removing the mask layer.
Referring to fig. 9, after the first semiconductor layer 205 is formed, the mask layer 204 is removed (as shown in fig. 8).
The process for removing the mask layer 204 includes one or two of a wet etching process and a dry etching process.
In an embodiment, the material of the mask layer 204 is silicon oxide, and the process for removing the mask layer 204 is a wet etching process. The parameters of the wet etching process comprise: the mass percentage of the hydrofluoric acid to the water is 1: 500-1: 2000, the etching time is 5-1000 seconds, and the over-etching amount is 50-300%. The wet etching process adopts hydrofluoric acid to remove the mask layer 204; due to the etching selectivity of hydrofluoric acid, the side wall and the bottom of the second source drain groove 225 cannot be etched.
In another embodiment, the process of removing the mask layer 204 is a dry etching process, and the dry etching process is an isotropic SICONI dry etching process. The SICONI dry etching process has uniform etching rate in different directions, and can uniformly remove the mask layer 204 on the side wall and the bottom of the second source-drain groove 225.
The parameters of the SICONI dry etching process comprise: the gas flow rate of He is 600 sccm-2000 sccm, NH3The gas flow rate of (1) is 200 sccm-500 sccm, NF3The gas flow rate of the gas is 20sccm to 200 sccm; the pressure is 2to 10torr, the etching time is 5 to 100 seconds, and the over-etching amount is 50 to 100 percent.
In this embodiment, after removing the mask layer, the method further includes: and forming a second semiconductor layer on the first semiconductor layer and the side wall and the bottom of the second source drain groove.
Referring to fig. 10, after removing the mask layer 204 (as shown in fig. 9), a second semiconductor layer 206 is further formed on the first semiconductor layer 205, on the sidewalls and the bottom of the second source-drain groove 225.
The second semiconductor layer 206 is located between the subsequently formed second source-drain doping layer and the second fin portion 220, and is used for preventing doping ions of the second source-drain doping layer from diffusing to the second fin portion 220, so that risk of junction leakage current caused by interface defects of the second source-drain doping layer is avoided, and electrical characteristics of the semiconductor device are improved.
The thickness of the second semiconductor layer 206 is 10to 80 angstroms. If the thickness is too small, the diffusion of the doped ions cannot be effectively blocked; when the thickness is too large and the second region is used as a core region, the capacitance between the second source-drain doping layer and the fin portion is too large, and the electrical characteristics of the semiconductor structure are reduced.
The material and the forming process of the second semiconductor layer 206 can refer to the first semiconductor layer 205, and are not described herein again.
Referring to fig. 11, a first source-drain doping layer 216 filling the first source-drain groove 215 (shown in fig. 10) is formed on the first semiconductor layer 205.
In this embodiment, a second source-drain doping layer 226 is further filled in the second source-drain groove 225 (as shown in fig. 10).
In this embodiment, the first semiconductor layer 205 and the second semiconductor layer 206 are formed between the first source-drain doping layer 216 and the first fin portion 210, and the first source-drain doping layer can be raised by the first semiconductor layer 205 and the second semiconductor layer 206, so that formation of a source-drain plug on the first source-drain doping layer in a subsequent process is facilitated, and poor contact between the source-drain plug and the first source-drain doping layer due to an excessively small volume of the first fin portion is prevented.
The formation process of the first source drain doping layer 216 and the second source drain doping layer 226 includes an epitaxial growth process.
In an embodiment, to obtain higher epitaxial quality, before the first source-drain doping layer 216 and the second source-drain doping layer 226 are formed, Hydrogen Pretreatment (Hydrogen Pretreatment) is performed on the sidewall and the bottom of the first source-drain groove 215 and the sidewall and the bottom of the second source-drain groove 225, respectively.
In this embodiment, the forming steps of the first source-drain doping layer 216 and the second source-drain doping layer 226 include: forming stress layers (not shown) in the first source-drain doped groove 215 and the second source-drain groove 225 respectively by using a selective epitaxial growth process; ions are doped in the stress layer to form a first source drain doped layer 216 and a second source drain doped layer 226 respectively.
When the formed semiconductor device is an NMOS transistor, the stress layer is made of silicon carbide, and the ions doped in the stress layer are N-type ions.
The first source drain doping layer 216 and the second source drain doping layer 226 respectively have doping ions, and the concentration of the doping ions is 5.0E20atom/cm3～1.0E22atom/cm3。
In the present embodiment, taking the formation of PMOS transistor as an example, the process gas of the epitaxial growth process includes H2HCl, dichlorosilane and PH3The process temperature is 650-850 ℃.
In one embodiment, carbon ion implantation is performed on the first source drain doping layer 216 and the second source drain doping layer 226, wherein the energy of the implanted ions is 5KeV, and the dose of the implanted ions is 1E13atom/cm3。
In one embodiment, the first source-drain doping layer and the second source-drain doping layer are pre-implanted with phosphorus ions, the energy of the implanted ions is 35KeV, and the dose of the implanted ions is 1E13atom/cm3(ii) a After the phosphorus ions are pre-implanted, annealing the first source-drain doping layer and the second source-drain doping layer, wherein the annealing temperature is 700 ℃ and the annealing time is 10-30 seconds; performing phosphorus ion implantation on the annealed first source-drain doping layer and the annealed second source-drain doping layer, wherein the energy of the implanted ions is 20KeV, and the dose of the implanted ions is 1E14atom/cm3. In another embodiment, boron ion implantation is performed on the first source drain doping layer 216 and the second source drain doping layer 226, wherein the energy of the implanted ions is 30KeV, and the dose of the implanted ions is 1E13atom/cm3(ii) a And annealing the first source-drain doping layer and the second source-drain doping layer after the boron ion pre-implantation, wherein the annealing temperature is 700 ℃ and the annealing time is 10-30 seconds.
Accordingly, the present embodiment further provides a semiconductor structure, please refer to fig. 11, including: the semiconductor device comprises a substrate 200, wherein the substrate 200 comprises a first region A, a first fin portion 210 located on the first region A, and an isolation structure 201 located on the substrate 200, and the isolation structure 201 covers part of the side wall of the first fin portion 210; a dummy gate oxide layer 202 covering the sidewall and the top surface of the first fin portion 210; a first dummy gate structure 211 crossing the first fin 210, wherein the first dummy gate structure 211 is located on a part of the isolation structure 201 and covers a part of the sidewall and the top surface of the first fin 211; a first sidewall 214 on a sidewall of the first dummy gate structure 211; the first source-drain doping layers 216 are respectively located in the first fin portion 210 on two sides of the first dummy gate structure 211 and the first side wall 214; and the first semiconductor layer 205 is located between the first source-drain doping layer 216 and the first fin portion 210.
In this embodiment, the substrate 200 further includes a second region B and a second fin 220 located on the second region B; the isolation structure 201 also covers a portion of the sidewalls of the second fin 220; the dummy gate oxide layer 202 also covers the sidewalls and the top surface of the second fin portion 220; a second dummy gate structure 221 crossing the second fin 220, wherein the second dummy gate structure 221 is located on a portion of the isolation structure 201 and covers a portion of a sidewall and a top surface of the second fin 220; a second sidewall 224 on a sidewall of the second dummy gate structure 221; and the second source-drain doping layers 226 are respectively located in the second fin portions 220 on two sides of the second dummy gate structure 221 and the second sidewall 224.
In this embodiment, the semiconductor structure further includes: and a second semiconductor layer 206 located on the first semiconductor layer 205 and between the second source-drain doping layer 226 and the second fin 220.
The thickness of the first semiconductor layer 205 is 30 to 200 angstroms.
The thickness of the second semiconductor layer 206 is 10to 80 angstroms.
The material of the first semiconductor layer 205 and the second semiconductor layer 206 includes silicon, germanium, silicon carbide, or silicon germanium.
The material, size and structure of the first semiconductor layer 205 are all referred to the previous embodiments.
The first source drain doped layer 216 and the second source drain doped layerThe source and drain doping layers 226 respectively have doping ions with a concentration of 8.0E20atom/cm3～1.8E21atom/cm3。
The materials, the sizes and the structures of the first source drain doping layer 216 and the second source drain doping layer 226 refer to the foregoing embodiments.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area, the first area of the substrate is provided with a first fin part, and an isolation structure is positioned on the substrate and covers partial side walls of the first fin part;
forming a first dummy gate structure crossing the first fin portion, wherein the first dummy gate structure is located on a part of the isolation structure and covers a part of the side wall and the top surface of the first fin portion;
forming a first side wall on the side wall of the first pseudo gate structure;
forming first source drain grooves in the first dummy gate structure and the first fin portions on two sides of the first side wall respectively;
forming a first semiconductor layer on the side wall and the bottom of the first source drain groove;
and forming a first source-drain doping layer which fills the first source-drain groove on the first semiconductor layer.
2. The method of claim 1, wherein the first semiconductor layer has a thickness of 30 to 200 angstroms.
3. The method of forming a semiconductor structure of claim 1, wherein a material of the first semiconductor layer comprises silicon, germanium, silicon carbide, or silicon germanium.
4. The method of forming a semiconductor structure of claim 3, wherein the process of forming the first semiconductor layer comprises an epitaxial growth process.
5. The method for forming a semiconductor structure according to claim 1, wherein the first source-drain doping layer has doping ions, and a concentration of the doping ions is 8.0E20atom/cm3～1.8E21atom/cm3。
6. The method for forming the semiconductor structure according to claim 5, wherein the forming process of the first source-drain doping layer comprises an epitaxial growth process.
7. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the first dummy gate structure: and forming a pseudo gate oxide layer covering the side wall and the top surface of the first fin part on the isolation structure.
8. The method of forming a semiconductor structure of claim 7, wherein the substrate further comprises a second region having a second fin portion thereon; the isolation structure also covers part of the side wall of the second fin part; the pseudo gate oxide layer also covers the side wall and the top surface of the second fin part; forming a second pseudo gate structure crossing the second fin portion, wherein the second pseudo gate structure is located on a part of the isolation structure and covers a part of the side wall and the top surface of the second fin portion; forming a second side wall on the side wall of the second pseudo gate structure; forming second source drain grooves in the second dummy gate structure and the second fin portions on two sides of the second side wall respectively; and filling a second source-drain doping layer in the second source-drain groove.
9. The method for forming a semiconductor structure according to claim 8, wherein before forming the first semiconductor layer on the sidewall and the bottom of the first source-drain groove, the method further comprises: and forming a mask layer on the side wall and the bottom of the second source drain groove.
10. The method of claim 9, wherein the mask layer has a thickness of 10to 40 angstroms.
11. The method of claim 10, wherein the mask layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
12. The method of claim 11, wherein the mask layer forming process comprises a deposition process or an oxidation process.
13. The method of forming a semiconductor structure of claim 9, further comprising, after forming the first semiconductor layer: and removing the mask layer.
14. The method of forming a semiconductor structure of claim 13, wherein after removing the mask layer, further comprising: and forming a second semiconductor layer on the first semiconductor layer and the side wall and the bottom of the second source drain groove.
15. The method of forming a semiconductor structure according to claim 14, wherein a thickness of the second semiconductor layer is 10to 80 angstroms.
16. A semiconductor structure, comprising:
a substrate comprising a first region and a first fin portion located on the first region;
an isolation structure on the substrate, the isolation structure covering a portion of sidewalls of the first fin;
the pseudo gate oxide layer covers the partial side wall and the top surface of the first fin part;
the first dummy gate structure crosses over the first fin part, is positioned on part of the isolation structure and covers part of the side wall and the top surface of the first fin part;
the first side wall is positioned on the side wall of the first pseudo gate structure;
the first source-drain doping layers are respectively positioned in the first dummy gate structure and the first fin parts on two sides of the first side wall;
and the first semiconductor layer is positioned between the first source drain doping layer and the first fin portion.
17. The semiconductor structure of claim 16, wherein the first semiconductor layer has a thickness of 30 to 200 angstroms.
18. The semiconductor structure of claim 16, wherein the substrate further comprises a second region and a second fin on the second region; the isolation structure also covers part of the side wall of the second fin part; the pseudo gate oxide layer also covers the side wall and the top surface of the second fin part; a second dummy gate structure crossing the second fin portion, wherein the second dummy gate structure is located on a part of the isolation structure and covers a part of the side wall and the top surface of the second fin portion; a second side wall positioned on the side wall of the second pseudo gate structure; and the second source-drain doping layers are respectively positioned in the second dummy gate structure and the second fin parts at two sides of the second side wall.
19. The semiconductor structure of claim 18, further comprising: and the second semiconductor layer is positioned on the first semiconductor layer and between the second source drain doping layer and the second fin portion.
20. The semiconductor structure of claim 19, wherein the second semiconductor layer has a thickness of 10to 80 angstroms.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448737A (en) * 2014-09-30 2016-03-30 联华电子股份有限公司 Etching process for forming silicon grooves, and fin-type field effect transistor
US9324850B2 (en) * 2013-02-26 2016-04-26 Samsung Electronics Co., Ltd. Integrated circuit devices and fabricating method thereof
CN105742354A (en) * 2014-12-29 2016-07-06 台湾积体电路制造股份有限公司 FinFET with Multiple Dislocation Planes and Method for Forming the Same
CN106558618A (en) * 2015-09-24 2017-04-05 三星电子株式会社 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9673328B2 (en) * 2010-05-28 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for providing line end extensions for fin-type active regions
KR20160141034A (en) * 2015-05-27 2016-12-08 삼성전자주식회사 Semiconductor devices and methods of manufacturing semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324850B2 (en) * 2013-02-26 2016-04-26 Samsung Electronics Co., Ltd. Integrated circuit devices and fabricating method thereof
CN105448737A (en) * 2014-09-30 2016-03-30 联华电子股份有限公司 Etching process for forming silicon grooves, and fin-type field effect transistor
CN105742354A (en) * 2014-12-29 2016-07-06 台湾积体电路制造股份有限公司 FinFET with Multiple Dislocation Planes and Method for Forming the Same
CN106558618A (en) * 2015-09-24 2017-04-05 三星电子株式会社 Semiconductor device

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