CN106033757B

CN106033757B - High mobility device with anti-punch through layer and method of forming the same

Info

Publication number: CN106033757B
Application number: CN201510122423.5A
Authority: CN
Inventors: 江国诚; 冯家馨; 吴志强
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2014-10-10
Filing date: 2015-03-19
Publication date: 2020-03-20
Anticipated expiration: 2035-03-19
Also published as: US9548362B2; US20160104776A1; CN106033757A; KR101702722B1; KR20160042736A

Abstract

An exemplary semiconductor device includes a fin extending upward from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having an APT dopant and a channel region located above the APT layer. The channel region is substantially free of APT dopant. The semiconductor device also includes a conductive gate stack located on sidewalls and a top surface of the channel region. The invention relates to a high mobility device with an anti-punch through layer and a method of forming the same.

Description

High mobility device with anti-punch through layer and method of forming the same

Cross Reference to Related Applications

This application claims the benefit of U.S. provisional patent application No. 62/062,598 entitled "High Mobility Devices with anti-Punch Through Layers and Methods of Forming Same", filed 10.10.2014, which is incorporated herein by reference in its entirety.

Technical Field

The invention relates to a high mobility device with an anti-punch through layer and a method of forming the same.

Background

Semiconductor devices are used in a large number of electronic devices such as computers, mobile phones, and the like. Semiconductor devices include integrated circuits formed on semiconductor wafers by depositing thin films of materials of many types over the semiconductor wafers and patterning the thin films of materials to form the integrated circuits. Integrated circuits typically include Field Effect Transistors (FETs).

Generally, planar FETs have been used in integrated circuits. However, due to the increasing density and decreasing footprint (footprint) requirements of modern semiconductor processing, planar FETs can often present problems as their size decreases. Some such problems include subthreshold swing degradation (swing degradation), significant Drain Induced Barrier Lowering (DIBL), fluctuations in device characteristics, and leakage. Fin field effect transistors (finfets) have been investigated to overcome some of these problems.

In a typical finFET, a vertical fin structure is formed above a substrate. Such vertical fin structures are used to form source/drain regions in the lateral direction and to form a channel region in the fin. A gate is formed over a channel region of the fin in a vertical direction in which the finFET is formed. Subsequently, an interlayer dielectric (ILD) and a plurality of interconnect layers may be formed over the finFET.

Disclosure of Invention

In order to solve the problems in the prior art, according to an aspect of the present invention, there is provided a semiconductor device including: a first fin extending upward from a semiconductor substrate, wherein the first fin includes a first anti-punch through (APT) layer including an APT dopant; and a first channel region over the first APT layer, wherein the first channel region is substantially free of the APT dopant; and a conductive gate stack on sidewalls and a top surface of the first channel region.

In the above semiconductor device, the first APT layer includes silicon boron (SiB) or silicon boron carbon (SiCB).

In the above semiconductor device, further comprising source and drain regions adjacent to the conductive gate stack, wherein the first APT layer is disposed under the source and drain regions.

In the above semiconductor device, further comprising a second fin extending upward from the semiconductor substrate, wherein the second fin comprises: a second APT layer comprising an n-type APT dopant and a p-type APT dopant; and a second channel region over the second APT layer.

In the above semiconductor device, a ratio of the first concentration of the p-type APT dopant in the second APT layer to the second concentration of the n-type APT dopant in the second APT layer is at least about 2: 1.

In the above semiconductor device, the second APT layer includes silicon boron phosphorus or silicon carbon boron phosphorus.

According to another aspect of the present invention, there is also provided a semiconductor device including: a first fin field effect transistor (finFET), comprising: a first anti-punch through (APT) layer comprising a first APT dopant of a first type; and a first semiconductor layer located over the first APT layer; a first conductive gate stack on sidewalls and a top surface of the first semiconductor layer; and a first source and drain region adjacent to the first conductive gate stack; and a second finFET comprising: a second APT layer comprising a second APT dopant of a first type and a third APT dopant of a second type different from the first type; a second semiconductor layer over the second APT layer; a second conductive gate stack on sidewalls and a top surface of the second semiconductor layer; and a second source and drain region adjacent to the second conductive gate stack.

In the above semiconductor device, the first semiconductor layer is substantially undoped with any APT dopant.

In the above semiconductor device, the first APT layer includes silicon boron (SiB) or silicon boron carbon (SiCB), and wherein the second APT layer includes silicon boron phosphorous (SiBP) or silicon boron phosphorous carbon (SiCBP).

In the above semiconductor device, the second APT layer includes a third APT dopant at least twice as much as the second APT dopant.

In the above semiconductor device, the first finFET further includes: a third semiconductor layer underlying the first APT layer; and a semiconductor oxide layer on a sidewall of the third semiconductor layer.

In the above semiconductor device, the first APT layer is disposed under the first source and drain regions, and wherein the second APT layer is disposed under the second source and drain regions.

According to yet another aspect of the present invention, there is also provided a method of forming a semiconductor device, the method comprising: forming an anti-punch through (APT) layer over a semiconductor substrate, wherein the APT layer includes a first APT dopant; forming a semiconductor layer over the APT layer; patterning the semiconductor layer and the APT layer to define a first fin extending upward from the semiconductor substrate, wherein the first fin includes a first APT layer portion and a first semiconductor layer portion; and forming a conductive gate stack on a top surface and sidewalls of the first semiconductor layer portion of the first fin.

In the above method, the semiconductor layer is substantially free of any APT dopant.

In the above method, patterning the semiconductor layer and the APT layer further defines a second fin comprising a second APT layer portion and a second semiconductor layer portion, and wherein the method further comprises: removing portions of the second semiconductor layer to expose portions of the second APT layer; and implanting a second APT dopant in the second APT layer portion, wherein the type of the second APT dopant is different from the type of the first APT dopant.

In the above method, further comprising masking the first fin while implanting the second APT dopant.

In the above method, implanting the second APT dopant includes implanting at least about twice the second APT dopant in the second APT layer portion as much as the first APT dopant.

In the above method, after implanting the second APT dopant, the second APT layer portion includes silicon boron phosphorous (SiBP) or silicon carbon boron phosphorous (SiCBP).

In the above method, forming the APT layer includes epitaxially growing a layer including silicon boron or silicon boron carbide.

In the above method, further comprising forming source and drain regions in the first fin adjacent to the conductive gate stack, wherein the first APT layer is partially disposed under the source and drain regions.

Drawings

Aspects of the invention are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is an example of a fin field effect transistor (finFET) in a three-dimensional view.

Figures 2-17C illustrate cross-sectional views of intermediate stages of manufacturing the finFEt, according to some embodiments.

Figure 18 illustrates a flow diagram of a method for fabricating a finFET in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which other features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations.

Furthermore, spatial relationship terms such as "below …," "below …," "below," "above …," and "above" may be used herein to readily describe the relationship of one element or component to another element(s) or component(s) as illustrated in the figures. In addition to the orientations shown in the figures, the spatial relationship terms are intended to encompass a variety of different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments include epitaxially growing an anti-punch through (APT) layer in a semiconductor substrate. The APT layer provides in-situ APT dopants that may prevent n-type and p-type dopants from the source/drain regions from penetrating into the underlying semiconductor layer of various finFET devices. Furthermore, the inclusion of the APT layer eliminates the need to implement an APT implant at least in devices of the first type (e.g., n-type or p-type) during the formation of such finFET devices, which may result in undoped channel regions and improved electrical functionality. APT dopant implantation may still be performed to form devices of a second type (e.g., the other of n-type or p-type) in the wafer.

Fig. 1 shows an example of a finFET 30 in a three-dimensional view. FinFET 30 includes a fin 36 on substrate 32. Substrate 32 includes isolation regions 38, and fins 36 protrude above adjacent isolation regions 38 from between adjacent isolation regions 38. The substrate 32 may also include an APT layer 34, and the APT layer 34 may be used to in-situ dope various regions of the finFET 30 with APT dopants. A gate dielectric 40 is along the sidewalls of fin 36 and over the top surface of fin 36, and a gate electrode 42 is over gate dielectric 40. The portion of the fin 36 covered by the gate dielectric 40/gate electrode 42 may be referred to as a channel region of the finFET 30. Source/

drain regions

44 and 46 are disposed on opposite sides of fin 36 relative to gate dielectric 40 and gate electrode 42. Fig. 1 also shows a reference cross section used in the following figures. The cross-section a-a spans the channel of the finFET 30, the gate dielectric 40, and the gate electrode 42. The cross-section B-B spans the source/

drain region

44 or 46 of the finFET 30. Cross section C-C is perpendicular to cross section a-a and along the longitudinal axis of fin 36 and in the direction of current flow, for example, between source/

drain regions

44 and 46. For the sake of clarity, the following figures refer to these reference cross sections.

Fig. 2-17C are cross-sectional views of various intermediate stages of fabricating a finFET in accordance with various embodiments, and fig. 18 is a process flow of the process shown in fig. 2-17C. Fig. 2 and 3 show the reference cross-section a-a shown in fig. 1 in addition to a plurality of finfets and/or finfets having a plurality of fins. As discussed above, in fig. 4A-17C, the figures ending with the reference "a" are shown along a similar cross-section a-a; the drawing ending with the reference "B" is shown along a similar cross-section B-B; and the figures ending with the reference "C" are shown along a similar cross-section C-C.

Fig. 2 and 3 illustrate the formation of a semiconductor fin extending upward from a substrate. Referring first to fig. 2, a wafer 100 having a substrate 102 is shown. The substrate 102 includes an n-channel metal oxide semiconductor (NMOS) region 202 for forming an NMOS finFET device and a p-channel metal oxide semiconductor (PMOS) region 204 for forming a PMOS finFET device.

Regions

202 and 204 may or may not be contiguous, and any number of device components (e.g., isolation regions, dummy components, etc. (not shown)) may be formed between NMOS region 202 and PMOS region 204, depending on the device design.

As shown, substrate 102 is a multilayer substrate that includes

various substrate layers

104, 106, 108, and 110. The base substrate layer 104 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate layer 104 may include silicon (Si), germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.

As further shown in FIG. 2,

additional substrate layers

106, 108, and 110 may be formed above base substrate layer 104. In some embodiments, various epitaxy may be performed to form

various substrate layers

106, 108, and 110. Any suitable epitaxial process may be used, such as by Metal Organic (MO) Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), combinations thereof, and the like.

Substrate layers 106 and 110 are disposed above base substrate layer 104, with substrate layer 110 disposed above substrate layer 106. In some embodiments, substrate layer 106 has a thickness T1 of about 20nm to about 90nm, and substrate layer 110 may have a thickness T3 of about 20nm to about 60 nm. The substrate layers 106 and 110 may be lattice mixed-matched (lattice mix-matched) to produce desired strain and/or electrical characteristics in the resulting finFET device. In some embodiments, such lattice compounding may be achieved by selecting different atomic percentages of germanium for

substrate layers

106 and 110. For example, tensile strain may be achieved when substrate layer 110 has a lower atomic percent of Ge than the underlying substrate layer 106, which is beneficial for NMOS devices. Thus, in various embodiments, substrate layer 110 may comprise bulk Si, while substrate layer 106 comprises SiGe to create tensile strain. For PMOS devices, however, compressive strain may be advantageous, which may be achieved when substrate layer 106 has a lower atomic percent of Ge than substrate layer 110. Thus, in subsequent process steps (see, e.g., fig. 10A and 10B), substrate layer 110 in PMOS region 204 may be replaced by a SiGe layer having a higher atomic percent of Ge than the underlying substrate layer 106.

Furthermore, the atomic percent of Ge in substrate layer 106 may vary in different regions of substrate 102 (e.g., NMOS region or PMOS region 204) to create a desired type of strain and/or to create a desired electrical characteristic. For example, the substrate layer 106 in the NMOS region 202 may include SiGe having a relatively high atomic percent of Ge, e.g., about 30% to about 80%. Conversely, the substrate layer 106 in the PMOS region 204 may include SiGe with a lower atomic percent of Ge. In such an embodiment, for example, the substrate layer 106 in the PMOS region 204 may include SiGe having an atomic percent of Ge of about 20% to about 45%. Furthermore, in some embodiments, the APT layer 108 may be sufficiently thin so as not to affect the strain induced in the resulting finFET device. For example, the APT layer may have a thickness of about 3nm to about 10 nm.

An anti-punch through (APT) layer 108 is disposed between

substrate layers

106 and 110. In some embodiments, APT layer 108 may be a semiconductor layer including APT dopants adapted to prevent source/drain punch-through in an n-type device. For example, APT layer 108 may include silicon carbon boron (SiCB), silicon boron (SiB), and the like. For example, the concentration of n-type APT dopant (e.g., boron) in APT layer 108 may be about 1 x 10¹⁸/cm³To about 3X 10¹⁸/cm³. In embodiments when APT layer 18 comprises SiCB, the carbon atoms may prevent (or at least reduce) the diffusion of APT dopants (e.g., boron) into the surrounding device layers. In this implementationIn an example, the atomic concentration of C in APT layer 108 may be about 0.5% to about 1%. Further, the APT layer 108 may have a thickness T2 of about 3nm to about 10 nm. By epitaxially growing the ATP layer 108 directly in the substrate 102, conventional APT dopant implantation of devices in the NMOS region 202 may be avoided at least. For example, the overlying substrate layer 110 may be substantially free of any dopants, and the APT dopant implantation may not even be performed on the substrate layer 110 in subsequent process steps. The resulting NMOS finFET may include a substantially undoped channel region, thereby improving the electrical performance and/or characteristics of the resulting device.

As further shown in fig. 2, a hard mask 112 and a photoresist 114 may be disposed over the substrate 102. The hard mask 112 may include one or more oxide (e.g., silicon oxide) layers and/or nitride (e.g., silicon nitride) layers to prevent damage to the underlying substrate 102 during patterning. The hard mask 112 may be formed using any suitable deposition process, such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), high density plasma CVD (HDP-CVD), Physical Vapor Deposition (PVD), and the like. The photoresist 114 may comprise any suitable photosensitive material blanket deposited using a suitable process such as spin coating or the like.

Fig. 3 illustrates patterning the substrate 102 to form fins 116 disposed between adjacent trenches 118. In example embodiments, the photoresist 114 may be first patterned by exposing the photoresist 114 to light using a photomask. The exposed or unexposed portions of photoresist 114 can then be removed, depending on whether a positive or negative photoresist is used.

The pattern of photoresist 114 may then be transferred to hard mask 112 (e.g., using a suitable etching process). Subsequently, the trench 118 is patterned into the underlying substrate 102 using the hard mask 112 as a patterning mask, for example, during an etching process. Etching the substrate 102 may include an acceptable etching process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etching may be anisotropic. The photoresist 114 is subsequently removed, for example, in an ashing and/or wet strip process. The hard mask 112 may also be removed. Thus, fins 116 are formed in the wafer 100. Fins 116 extend upward from the base substrate layer 104 between adjacent trenches 118.

Fig. 4A-5B illustrate the optional formation of a tensile strain producing member (e.g., dielectric layer 122, see, e.g., fig. 5A) on fin 116 in NMOS region 202. Referring to fig. 4A and 4B, a hard mask 120 is formed over a portion of wafer 102. Furthermore, fig. 4A shows a cross-section of the wafer 100 across the channel region (cross-section a-a of fig. 1), while fig. 4B shows a cross-section of the wafer 100 across the source/drain regions at the same stage of fabrication (cross-section B-B of fig. 1). As shown, the hard mask 120 covers the top surface and sidewalls of the fin 116 in the PMOS region 204 and the source/drain regions of the fin 116 in the NMOS region 202. However, the hard mask 120 is patterned to expose the channel region of the fin 116 in the NMOS region 202. The hard mask 120 may comprise any suitable dielectric material (e.g., nitride or oxide), which may be patterned using a combination of lithography and etching, for example.

Fig. 5A and 5B illustrate the formation of the dielectric layer 122 on the portion of the fin 116 in the NMOS region 202. The dielectric layer 122 may be formed by oxidizing the substrate layer 106 in the NMOS region 202. In such an embodiment, the dielectric layer 122 may comprise a semiconductor oxide (e.g., SiGe oxide). Any suitable oxidation process may be used, such as a wet oxidation process that selectively oxidizes Ge within substrate layer 106 but does not oxidize the semiconductor material of

other substrate layers

104, 108, or 110 (e.g., bulk Si, SiB, or SiCB). In some example embodiments, the wet oxidation process may include maintaining the wafer 100 at a temperature of about 400 ℃ to about 500 ℃ while supplying pure water vapor to the wafer 100 for a duration of between about thirty minutes and about one hour in an environment maintained at a pressure of about 1 Atm. For example, the resulting dielectric layer 122 may have a thickness T4 (at the thickest point) of about 3nm to about 10 nm. Other suitable oxidation processes may also be used.

The oxidation process forms dielectric layer 122 within trench 118 of the channel region in NMOS region 202. The dielectric layer 122 may create a tensile strain in the fin 116 on which the dielectric layer 122 is formed. The resulting tensile strain may be more suitable for the channel region of an NMOS device. Accordingly, the formation of the dielectric layer 122 may be limited to the channel region of the NMOS region 202, and the dielectric layer 122 may not be formed in the PMOS region 204 or under the source/drain regions in the NMOS region 202. Selective formation of the dielectric layer 122 may be facilitated by configuring the hard mask 120. For example, during the oxidation process, the hard mask 120 may mask the fin 116 in the PMOS region 204 and the fin 116 in the source/drain regions of the fin 116 in the NMOS region 202. After the dielectric layer 122 is formed, the hard mask 120 may be removed.

Referring next to fig. 6A and 6B, a liner 124, such as a diffusion barrier layer, may be disposed along the bottom and sidewalls of trench 118. In some embodiments, the liner 124 may include a semiconductor (e.g., silicon) nitride, a semiconductor (e.g., silicon) oxide, a thermal semiconductor (e.g., silicon) oxide, a semiconductor (e.g., silicon) oxynitride, a polymer dielectric, combinations thereof, and the like. The formation of liner 124 may include any suitable method, such as Atomic Layer Deposition (ALD), CVD, High Density Plasma (HDP) CVD, Physical Vapor Deposition (PVD), and the like.

In fig. 7A and 7B, the trench 118 may be filled with a dielectric material such as silicon oxide. In some embodiments, Silane (SiH)₄) And oxygen (O)₂) As a reaction precursor, the resulting STI region 126 may be formed using a High Density Plasma (HDP) CVD process. In other embodiments, the STI region 126 may be formed using a sub-atmospheric CVD (SACVD) process or a High Aspect Ratio Process (HARP), wherein the process gases may include Tetraethylorthosilicate (TEOS) and ozone (O)₃). In still other embodiments, STI regions 126 may be formed using a spin-on dielectric (SOD) process, such as Hydrogen Silsesquioxane (HSQ) or Methyl Silsesquioxane (MSQ). An anneal (or other suitable process) may be performed to solidify the material of STI regions 126, and liner 124 may prevent (or at least reduce) diffusion of semiconductor material (e.g., Si and/or Se) in fin 116 into surrounding STI regions 126 during the anneal. Other processes and materials may be used. A Chemical Mechanical Polishing (CMP) or etch back process may be used to level the STI regions 126, liner 124, and top surface of fin 116.

Fig. 8A and 10B illustrate the replacement of semiconductor layer 110 with semiconductor layer 134 (e.g., having a higher atomic percent of Ge) in PMOS region 204. Fig. 8A and 8B illustrate removing the top of fin 116 (e.g., a portion of semiconductor layer 110) in PMOS region 204. In some embodiments, the NMOS region 202 may be masked (e.g., by the hard mask 128) during removal of the semiconductor layer 110 in the PMOS region 204. Thus, PMOS region 204 may be selectively processed without affecting the components of NMOS region 202. Removing semiconductor layer 110 in PMOS region 204 may include any suitable process, such as dry etching, wet etching, RIE, or the like. Removing portions of semiconductor layer 110 defines trenches 132 between adjacent STI regions 126, and such trenches 132 may expose APT layer 108 in PMOS region 204.

As further illustrated by fig. 8A and 8B, after exposing APT layer 108 in PMOS region 204, an APT dopant implantation process (indicated by arrow 130) may be performed. The APT dopant implantation process may implant p-type APT dopants into the exposed APT layer 108. In some embodiments, the implanted APT dopant may be useful for preventing source/drain punch-through in p-type devices. For example, the p-type APT dopant used may include phosphorus and the like.

In some embodiments, the p-type APT dopant may be implanted at a suitably high concentration to suppress the n-type APT dopant (e.g., boron) originally found in APT layer 108. For example, the ratio of the concentration of the implanted p-type APT dopant (e.g., phosphorus) to the n-type APT dopant (e.g., boron) may be at least about 2: 1. As another example, the concentration of n-type APT dopant (e.g., boron) in APT layer 108 may be about 1 x 10¹⁸/cm³To about 3X 10¹⁸/cm³In an embodiment, the concentration of the p-type APT dopant (e.g., phosphorus) implanted into APT layer 108 may be about 2 x 10¹⁸/cm³To about 6X 10¹⁸/cm³. After implantation, the resulting APT layer 108 (labeled 108P in fig. 9A and 9B) in the PMOS region 204 may include silicon-carbon-boron-phosphorus (SiCBP), silicon-boron-phosphorus (SiBP), and the like. During the p-type APT dopant implantation, the NMOS region 202 may be masked, and thus the portion of the fin 116 (e.g., the substrate layer 110) in the NMOS region 202 may remain substantially undoped even after the implantation.

Fig. 9A and 9B show that pad 124 in PMOS region 204 is optionally recessed. The recessing of the liner 124 may include any suitable process, such as dry etching, wet etching, RIE, and the like. Pad 124 may be recessed from a top surface of APT layer 108P in PMOS region 204. In subsequent process steps (e.g., in fig. 10A and 10B), a semiconductor layer 134 may be grown in the trench 132. In embodiments where liner 124 is recessed across APT layer 108P, semiconductor layer 134 may be grown on multiple surfaces (e.g., lateral top and sidewall surfaces) of APT layer 108P. This increased bonding area may reduce the occurrence of voids and other interface defects at the interface between APT layer 108P and semiconductor layer 134.

Subsequently, in fig. 10A and 10B, epitaxy is performed to epitaxially grow the semiconductor layer 134 in the trench 132. In various embodiments, the semiconductor layer 134 may be lattice-compounded with the underlying substrate layer 106 to achieve a compressive strain, which may be beneficial for p-type devices. For example, the semiconductor layer 134 may include a higher atomic percentage of Ge than the underlying substrate layer 106. In such an embodiment, the substrate layer 106 may comprise SiGe having an atomic percent of Ge of about 20% to about 45%, and the semiconductor layer 134 may comprise SiGe or Ge having an atomic percent of Ge of about 45% to about 100%. The epitaxy of semiconductor layer 134 may overgrow the top surface of STI regions 126 and a planarization technique (e.g., a Chemical Mechanical Polishing (CMP) process) may be performed to make the top surface of semiconductor layer 134 and the top surface of STI regions 126 flush. In addition, the material (e.g., SiGe or Ge) of semiconductor layer 134 may provide enhanced electrical performance (e.g., increased mobility) in the channel region of the resulting p-type device. In some embodiments, after formation, semiconductor layer 134 may include a concentration of about 2 x 10¹⁷/cm³To about 2X 10¹⁸/cm³Due to the epitaxy of semiconductor layer 134 over APT layer 108P, dopants may form in semiconductor layer 134. However, even in such embodiments, the semiconductor layer 110 may remain undoped due to the hard mask 128. After the semiconductor layer 134 is epitaxial, the hard mask 128 may be removed.

In fig. 11A and 11B, the STI region 126 is recessed such that the top of the semiconductor layers 110 and 134 is higher than the top surface of the STI region 126. Recessing the STI regions 126 may include a chemical etch process, e.g., using ammonia (NH) with or without a plasma₃) With hydrofluoric acid (HF) or nitrogen trifluoride (NF)₃) The combination of (1) as a reaction solution. When HF is used as the reaction solution, the dilution ratio of HF may be between about 1:50 to about 1: 100. Can also be recessedThe liner 124 in the NMOS region 202 may be substantially flush with the recessed STI region 126. After the recess, the top surfaces and sidewalls of the semiconductor layers 110 and 134 in the fin 116 are exposed. Thereby forming a channel region 136 (e.g., exposed portions of

semiconductor layers

110 and 134 along cross-section a-a) in fin 116. In the completed finFET structure, the gate wraps around and covers the sidewalls of such channel region 136 (see, e.g., fig. 1 and 17A). For example, due to the inclusion of APT layer 108, at least channel region 136 in NMOS region 202 may be undoped and substantially free of any dopants, since APT layer 108 is formed without an APT implant process.

Fig. 12A-12C illustrate the formation of a gate stack 140 on the top surface and sidewalls of the channel region 136. Gate stack 140 includes a conformal dummy oxide 142 and a dummy gate 144 over dummy oxide 142. The dummy gate 144 may comprise, for example, polysilicon, but materials such as metal silicides, metal nitrides, and the like may also be used. Each gate stack 140 may also include a hard mask 146 over the dummy gate 144. For example, the hard mask 146 may comprise silicon nitride or silicon oxide. In some embodiments, each gate stack 140 may span over multiple semiconductor fins 116 and/or STI regions 126. The gate stack 140 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the semiconductor fin 116 (e.g., see fig. 1). As shown in fig. 12B, forming gate stack 140 may also include forming a dummy oxide 142 over sidewalls and top surfaces of fin 116 (e.g., over exposed portions of semiconductor layers 110 and 134) in the source/drain regions of fin 116.

As also shown in fig. 12C, gate spacers 148 are formed on the sidewalls of the gate stack 140. In some embodiments, the gate spacers 148 are formed of silicon oxide, silicon nitride, silicon carbonitride, or the like. In addition, the gate spacer 148 may have a multi-layer structure, for example, having a silicon nitride layer over a silicon oxide layer.

Referring to fig. 13A-13C, an etch is performed to etch the portions of the semiconductor fin 116 not covered by the hard mask 146 or the gate spacer 148. The etch may also remove portions of the dummy oxide 142 not covered by the hard mask 146, which may correspond to portions of the dummy oxide 142 above the semiconductor layers 110 and 134 located in the source/drain regions of the fin 116 (see fig. 13B). After etching, the remaining portions of the dummy oxide 142 may be used as Main Sidewall (MSW) spacers 152 to define source/drain epitaxial regions in subsequent process steps. Optionally, the fin 116 may be recessed beyond the top surface of the STI region 126, and the exposed sidewalls of the STI region 126 may be used to define source/drain epitaxial regions. In such embodiments, the spacers 152 may be omitted. Thus, a trench 150 is formed between adjacent spacers 152. Trenches 150 are located on opposite sides of dummy gate stack 140 (see fig. 13C). After forming the trenches 150, Lightly Doped Drain (LDD) and annealing processes may be performed on the exposed surfaces of the fins 116 (e.g., the recessed semiconductor layers 110 and 134). Although trenches 150 are shown to expose recessed surfaces of

semiconductor layers

110 and 134, in alternative embodiments, trenches 150 may also expose underlying APT layers 108 and 108P.

Next, as shown in fig. 14A to 14C, an epitaxial region 154 is formed by selectively growing a semiconductor material in the trench 150. In some embodiments, epitaxial region 154 includes silicon (no germanium), germanium (no silicon), silicon germanium, silicon phosphorous, and the like. For example, epitaxial region 154 may also be formed from pure or substantially pure germanium having an atomic percent of germanium greater than about 95%. The hard mask 146 and spacers 152 may mask regions of the wafer 100 to define areas for forming epitaxial regions 154 (e.g., only on exposed portions of the fins 116). After filling the trenches 150 with the epitaxial regions 154, further epitaxial growth of the source/drain regions 154 causes the epitaxial regions 154 to expand laterally and facet formation may begin. Furthermore, due to the lateral growth of the source/drain regions 154, portions of the STI regions 126 may underlie portions of the epitaxial regions 154 and align with portions of the epitaxial regions 154.

After the epitaxial step, epitaxial region 154 may be implanted with a p-type impurity (e.g., boron or BF) in PMOS region 204₂) And the NMOS region 202 is implanted with an n-type impurity (e.g., phosphorous or arsenic) to form source/drain regions, which may also be referred to using reference numeral 154. Alternatively, the epitaxial regions 154 may be doped in-situ with p-type or n-type impurities when grown to form the source/drain regions. The source/drain regions 154 are located on opposite sides of the gate stack 140 (see fig. 14C) and may be covered and overlapped portions of the surface of the STI region 126 (see fig. 14B). In addition, the toolAPT layer 108/108P with appropriate types of APT dopants (e.g., n-type APT dopants in NMOS region 202 and P-type APT dopants in PMOS region 204) is located below source/drain region 154, and APT layer 108/108P may prevent or at least reduce source/drain punch-through.

Fig. 15A-15C show wafer 100 after formation of interlayer dielectric 156. The ILD 156 may comprise a flowable oxide formed using, for example, Flowable Chemical Vapor Deposition (FCVD). CMP (or other suitable planarization process) may be performed to make the top surfaces of ILD 156, gate stack 140, and gate spacer 148 flush with one another. Although not shown in detail in fig. 15A-15C, various intervening layers (e.g., buffer layers and/or etch stop layers) may be disposed between ILD layer 156 and source/drain regions 154, gate stack 140, and/or gate spacers 148.

Fig. 16A-16C show variations of the wafer 100 after the channel region 136 of the fin 116 is exposed. Exposing channel region 136 can include removing gate stack 140 (including hard mask 146, dummy gate 144, and dummy oxide 142) from the sidewalls and top surface of channel region 136. Removal of gate stack 140 may define trenches 160 between gate spacers 148 (see fig. 16C). A hard mask 158 may be used to mask the ILD 156 and the source/drain regions 154 during removal of the gate stack 140. Thus, the gate stack 140 may be removed without patterning the ILD 156 or the source/drain regions 154.

Next, referring to fig. 17A to 17B, a gate stack 162 is formed in the trench 160. For example, the gate dielectric 164 is formed as a conformal layer in the trench 160. Gate dielectric 164 may cover the top surface and sidewalls of channel region 136 (see fig. 17A). According to some embodiments, the gate dielectric 164 comprises silicon oxide, silicon nitride, or multilayers thereof. In an alternative embodiment, the gate dielectric 164 comprises a high-k dielectric material. In such an embodiment, the gate dielectric 164 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), combinations thereof, and the like. Methods of forming the gate dielectric 164 may include Molecular Beam Deposition (MBD), ALD, plasma enhanced cvd (pecvd), and the like.

Next, a conductive gate electrode 166 is formed over the gate dielectric 164 by filling the remaining portion of the trench 160 with a conductive material. The gate electrode 166 may include a metal-containing material such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ru), aluminum (Al), combinations thereof, multilayers thereof, and the like. The formation of gate dielectric 164 and gate electrode 166 may overflow trench 160 and cover the top surface of ILD 156. Subsequently, planarization (e.g., CMP) is performed to remove excess portions of the gate dielectric 164 and the gate electrode 166. The remaining portions of the resulting gate dielectric 164 and gate electrode 166 form a gate stack 162 over the channel region 136 of the resulting finFET. Additional features, such as source/drain contacts 168, for example, including nickel (Ni), tungsten (W), etc., may then be formed in ILD 156 using any suitable process to electrically connect with source/drain regions 154.

Fig. 18 illustrates an example process flow 300 for forming a semiconductor device (e.g., a finFET), in accordance with some embodiments. In step 302, an APT layer (e.g., APT layer 108) is epitaxially grown in a semiconductor substrate (e.g., substrate 102). The APT layer may include a first type of APT dopant. For example, in some embodiments, the APT layer may include an n-type APT dopant, and in such embodiments, the APT layer may include SiB or SiCB. In step 304, a first semiconductor layer (e.g., semiconductor layer 110) is formed over the APT layer using any suitable process, such as performing additional epitaxy. The first semiconductor layer may be substantially free of any dopants and at least a portion of the first semiconductor layer may serve as a channel region (e.g., trench region 136) of the resulting finFET.

Next, in step 306, first and second fins (e.g., fins 116 in NMOS region 202 and PMOS region 204) extending upward from the semiconductor substrate are patterned. Each fin may include a first semiconductor layer portion and an APT layer portion. In step 308, the APT layer portion of the second fin is exposed, for example, by removing the first semiconductor layer portion of the second fin. In step 310, a different type of APT dopant is implanted in the APT layer portion of the second fin. For example, when the original APT layer includes an n-type APT dopant, the APT dopant implanted in step 310 may include a p-type APT dopant. In some embodiments, step 310 may include implanting an APT dopant at a concentration high enough to suppress APT dopant originating from the APT layer. After implantation, for example, the APT layer in the second fin may comprise SiBP or SiCBP. In step 312, a second semiconductor layer (e.g., semiconductor layer 134) is formed over the APT in the second fin.

In various embodiments, the first fin (e.g., fin 116 of NMOS region 202) is masked during steps 308-312. Thus, the first fin may still comprise a first semiconductor layer that may remain substantially undoped. Finally, in step 314, a conductive gate stack is formed on the top surface and sidewalls of the first and second fins. For example, a conductive gate stack may be formed on a top surface and sidewalls of the first semiconductor layer portion of the first fin and on the second semiconductor layer portion of the second fin. Additional features such as source/drain regions may also be formed adjacent to the conductive gate stack, and an APT layer may be disposed below such source/drain regions to prevent (or at least reduce) source/drain punch-through in the resulting finFET device.

Various embodiments include epitaxially growing an APT layer in a semiconductor substrate. The APT layer provides in-situ APT dopants that may prevent n-type and p-type dopants from the source/drain regions from penetrating into the underlying semiconductor layer of various finFET devices. An additional semiconductor layer may be formed over the APT layer, and portions of the additional semiconductor layer may serve as a channel region of the resulting finFET device. The inclusion of the APT layer with native APT dopants eliminates APT implantation in at least a first type (e.g., n-type or p-type) of device in the fin of such finFET device, which may result in an undoped channel region and improved electrical function. APT dopant implantation may still be performed to form devices of a second type (e.g., the other of n-type or p-type) in the wafer.

According to an embodiment, a semiconductor device includes a fin extending upward from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having an APT dopant and a channel region located above the APT layer. The channel region is substantially free of APT dopant. The semiconductor device also includes a conductive gate stack located on sidewalls and a top surface of the channel region.

According to another embodiment, a semiconductor device includes a first finFET and a second finFET. The first finFET includes a first anti-punch-through (APT) layer having a first APT dopant of a first type, a first semiconductor layer located above the first APT layer, a first conductive gate stack located on sidewalls and a top surface of the first semiconductor layer, and first source and drain regions adjacent the first conductive gate stack. The second finFET includes a second APT layer having a second APT dopant of a first type and a third APT dopant of a second type different from the first type. The second finFET further includes a second semiconductor layer located above the second APT layer, a second conductive gate stack located on sidewalls and a top surface of the second semiconductor layer, and second source and drain regions adjacent to the second conductive gate stack.

According to yet another embodiment, a method of forming a semiconductor device includes epitaxially growing an anti-punch through (APT) layer over a semiconductor substrate and forming a semiconductor layer over the APT layer. The APT layer includes a first APT dopant. The semiconductor layer and the APT layer are patterned to define a fin extending upwardly from the semiconductor substrate. The first fin includes a first APT layer portion and a first semiconductor layer portion. The method also includes forming a conductive gate stack on a top surface and sidewalls of the first semiconductor layer portion of the first fin.

The components of several embodiments are discussed above so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a first fin extending upward from a semiconductor substrate, wherein the first fin comprises

A first anti-punch through (APT) layer comprising an anti-punch through dopant;

a first channel region over the first anti-punch through layer, wherein the first channel region is free of the anti-punch through dopant;

a semiconductor layer located under the first anti-punch-through layer; and

a first semiconductor oxide layer located only on sidewalls of the semiconductor layer,

the semiconductor device further includes a conductive gate stack on sidewalls and a top surface of the first channel region.

2. The semiconductor device of claim 1, wherein the first anti-punch-through layer comprises silicon boron (SiB) or silicon boron carbon (SiCB).

3. The semiconductor device of claim 1, further comprising source and drain regions adjacent the conductive gate stack, wherein the first anti-punch-through layer is disposed below the source and drain regions.

4. The semiconductor device of claim 1, further comprising a second fin extending upward from the semiconductor substrate, wherein the second fin comprises:

a second anti-punch-through layer comprising an n-type anti-punch-through dopant and a p-type anti-punch-through dopant; and

a second channel region over the second anti-punch through layer.

5. The semiconductor device of claim 4, wherein a ratio of a first concentration of the p-type anti-punch-through dopant in the second anti-punch-through layer to a second concentration of the n-type anti-punch-through dopant in the second anti-punch-through layer is at least 2: 1.

6. The semiconductor device of claim 4, wherein the second anti-punch-through layer comprises silicon boron phosphorous or silicon boron carbon phosphorous.

7. A semiconductor device, comprising:

a first fin field effect transistor (finFET), comprising:

a first anti-punch through (APT) layer comprising a first anti-punch through dopant of a first type; and

a first semiconductor layer located over the first anti-punch-through layer;

a third semiconductor layer located under the first anti-punch-through layer;

a first semiconductor oxide layer only on sidewalls of the third semiconductor layer;

a first conductive gate stack on sidewalls and a top surface of the first semiconductor layer; and

a first source and drain region adjacent to the first conductive gate stack,

the semiconductor device further includes a second finFET, the second finFET comprising:

a second anti-punch-through layer comprising a second anti-punch-through dopant of a first type and a third anti-punch-through dopant of a second type different from the first type;

a second semiconductor layer over the second anti-punch through layer;

a second conductive gate stack on sidewalls and a top surface of the second semiconductor layer; and

a second source and drain region adjacent to the second conductive gate stack.

8. The semiconductor device of claim 7, wherein the first semiconductor layer is undoped with any anti-punch-through dopant.

9. The semiconductor device of claim 7, wherein the first anti-punch-through layer comprises silicon boron (SiB) or silicon boron carbon (SiCB), and wherein the second anti-punch-through layer comprises silicon boron phosphorous (SiBP) or silicon boron phosphorous carbon (SiBP).

10. The semiconductor device of claim 7, wherein the second anti-punch-through layer comprises a third anti-punch-through dopant at least twice as much as the second anti-punch-through dopant.

11. The semiconductor device of claim 7, wherein the first anti-punch-through layer is disposed under the first source and drain regions, and wherein the second anti-punch-through layer is disposed under the second source and drain regions.

12. A method of forming a semiconductor device, the method comprising:

forming an anti-punch through (APT) layer over a semiconductor substrate, wherein the APT layer includes a first anti-punch through dopant;

forming a semiconductor layer over the anti-punch through layer;

patterning the semiconductor layer and the anti-punch-through layer to define a first fin extending upwardly from the semiconductor substrate, wherein the first fin includes a first anti-punch-through layer portion and a first semiconductor layer portion, and further includes a third semiconductor layer underlying the first anti-punch-through layer portion and a first semiconductor oxide layer only on sidewalls of the third semiconductor layer; and

forming a conductive gate stack on a top surface and sidewalls of the first semiconductor layer portion of the first fin.

13. The method of claim 12, wherein the semiconductor layer is free of any anti-punch through dopant.

14. The method of claim 12, wherein patterning the semiconductor layer and the anti-punch-through layer further defines a second fin comprising a second anti-punch-through layer portion and a second semiconductor layer portion, and wherein the method further comprises:

removing the second semiconductor layer portion to expose the second anti-punch through layer portion; and

implanting a second anti-punch through dopant in the second anti-punch through layer portion, wherein the second anti-punch through dopant is of a different type than the first anti-punch through dopant.

15. The method of claim 14, further comprising masking the first fin while implanting the second anti-punch-through dopant.

16. The method of claim 14, wherein implanting the second anti-punch-through dopant comprises implanting at least twice the first anti-punch-through dopant in the second anti-punch-through layer portion.

17. The method of claim 14, wherein, after implanting the second anti-punch-through dopant, the second anti-punch-through layer portion comprises silicon boron phosphorous (SiBP) or silicon carbon boron phosphorous (SiCBP).

18. The method of claim 12, wherein forming the anti-punch-through layer comprises epitaxially growing a layer comprising silicon boron or silicon boron carbon.

19. The method of claim 12, further comprising forming source and drain regions in the first fin adjacent to the conductive gate stack, wherein the first anti-punch-through layer portion is disposed below the source and drain regions.