CN111415906B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN111415906B
CN111415906B CN201910008367.0A CN201910008367A CN111415906B CN 111415906 B CN111415906 B CN 111415906B CN 201910008367 A CN201910008367 A CN 201910008367A CN 111415906 B CN111415906 B CN 111415906B
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layer
fin
forming
fin portion
substrate
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CN111415906A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: etching the substrate of the first region to form first fin parts and first grooves located among the first fin parts; etching the substrate of the second region to form second fin parts and second grooves located among the second fin parts, wherein the second fin parts comprise bottom fin parts and top fin parts located on the bottom fin parts, and the width of the bottom fin parts is larger than that of the first fin parts in the extending direction perpendicular to the second fin parts; the depth of the second groove is greater than that of the first groove; and forming a first isolation layer in the second groove, wherein the first isolation layer at least covers the bottom fin part. According to the embodiment of the invention, the width of the bottom fin part is increased, so that the rigidity of the second fin part is higher, and the capability of the second fin part for bearing the stress of the first isolation layer is correspondingly higher, thereby reducing the probability of the second fin part being bent due to the stress of the first isolation layer, and further being beneficial to improving the performance and the performance uniformity of the device.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is lower than that of the first device; etching the substrate of the first region to form first fin parts and first grooves located among the first fin parts; etching the substrate of the second region to form second fin parts and second grooves located among the second fin parts, wherein the second fin parts comprise bottom fin parts and top fin parts located on the bottom fin parts, and the width of the bottom fin parts is larger than that of the top fin parts in the extending direction perpendicular to the second fin parts; wherein the depth of the second groove is greater than the depth of the first groove; and forming a first isolation layer in the second groove, wherein the first isolation layer at least covers the bottom fin part.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate comprising a first region for forming a first device and a second region for forming a second device having a lower power than the first device; the first fin parts are positioned on the substrate of the first region, and regions among the first fin parts are first grooves; the second fin portion is positioned on the substrate in the second region, a region between the second fin portions is a second groove, the second fin portion comprises a bottom fin portion and a top fin portion positioned on the bottom fin portion, and the width of the bottom fin portion is larger than that of the top fin portion in the extending direction perpendicular to the second fin portion; wherein the depth of the second groove is greater than the depth of the first groove; and the isolation layer is positioned in the first groove and the second groove and at least covers the bottom fin part.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
after the first isolation layer is formed, the first isolation layer is generally annealed to make the material of the first isolation layer more compact, but relatively larger stress is generated in the first isolation layer; the second fin portion comprises a bottom fin portion and a top fin portion located on the bottom fin portion, the bottom fin portion is wider than the top fin portion along an extending direction perpendicular to the second fin portion, and compared with the situation that the whole width of the second fin portion is equal to the width of the top fin portion, the width of the bottom fin portion is increased, so that the rigidity of the second fin portion is larger, the capacity of the second fin portion for bearing the stress of the first isolation layer is correspondingly larger, the probability that the second fin portion is bent due to the stress of the first isolation layer is reduced, and the performance uniformity of the device are improved.
Drawings
Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 3 to 13 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention;
fig. 14 to fig. 20 are schematic structural diagrams corresponding to respective steps of another method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 2, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 4 and a fin portion protruding from the substrate 4 are formed, where the substrate 4 includes a first region I and a second region II, the first region I is used to form a first device, the second region II is used to form a second device, and a power of the second device is lower than a power of the first device; the fin structure comprises a first region and a second region, wherein the first region is formed by a first groove and a second groove, the second groove is formed by a second groove, and the depth of the second groove 6 is larger than that of the first groove 3.
The widths of the first fin portion 2 and the second fin portion 5 are equal in a direction perpendicular to the extending direction of the second fin portion 5.
Referring to fig. 2, a barrier layer 7 is formed in the first groove 3 (shown in fig. 1) and the second groove 6 (shown in fig. 1) using a Flowable Chemical Vapor Deposition (FCVD) process.
After the isolation layer 7 is formed, the isolation layer 7 is typically annealed. The annealing treatment breaks the Si-H bond and the Si-O bond in the isolation layer 7, so that the isolation layer 7 is easy to deform and becomes more compact, and correspondingly, the isolation layer 7 has larger stress. Because the second recess 6 is deeper than the first recess 3, the thickness of the isolation layer 7 in the second recess 6 is greater than the thickness of the isolation layer 7 in the first recess 3, and therefore the stress to which the second fin 5 is subjected is greater, the second fin 5 being more flexible than the first fin 2; and because the height of the second fin portion 5 is greater than the height of the first fin portion 2, the rigidity of the second fin portion 5 is less than the rigidity of the first fin portion 2, and the second fin portion 5 is more easily bent under the same stress.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is lower than that of the first device; etching the substrate of the first region to form first fin parts and first grooves between the first fin parts; etching the substrate of the second region to form second fin parts and second grooves located among the second fin parts, wherein the second fin parts comprise bottom fin parts and top fin parts located on the bottom fin parts, and the width of the bottom fin parts is larger than that of the top fin parts in the extending direction perpendicular to the second fin parts; wherein the depth of the second groove is greater than the depth of the first groove; and forming a first isolation layer in the second groove, wherein the first isolation layer at least covers the bottom fin part.
After the first isolation layer is formed, the first isolation layer is generally annealed to make the material of the first isolation layer more compact, but relatively larger stress is generated in the first isolation layer; the second fin portion comprises a bottom fin portion and a top fin portion located on the bottom fin portion, the bottom fin portion is wider than the top fin portion along the extending direction perpendicular to the second fin portion, and compared with the situation that the whole width of the second fin portion is equal to the width of the top fin portion, the second fin portion is enabled to be higher in rigidity through increasing the width of the bottom fin portion, and the capacity of the second fin portion for bearing the stress of the first isolation layer is correspondingly higher, so that the probability that the second fin portion bends due to the stress of the first isolation layer is reduced, and further improvement of performance and performance uniformity of the device is facilitated.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 3 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, a substrate 100 is provided, the substrate 100 including a first region I for forming a first device and a second region II for forming a second device having a power lower than that of the first device.
The substrate 100 is used to provide a process foundation for forming a fin.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, in order to improve the performance of the device, a SiGe channel technology may be used, that is, the material of the substrate includes silicon germanium, and the material of the corresponding subsequently formed fin and channel layer is SiGe. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
And then patterning the substrate 100, forming a first fin portion in the first region I, and forming a second fin portion in the second region II.
In this embodiment, the first fin portion is formed first, and then the second fin portion is formed. In other embodiments, the first fin portion may be formed after the second fin portion is formed.
Referring to fig. 4, the substrate 100 in the first region I is etched (as shown in fig. 3), so as to form first fins 101 and first grooves 102 located between the first fins 101. The first recess 102 is used in preparation for a subsequent formation of a second isolation layer.
The step of forming the first fin 101 includes: and etching the base 100 of the first region I and the second region II to form a first substrate 104 and an initial fin portion located on the first substrate 104, wherein the initial fin portion located on the first region I is used as the first fin portion 101.
The step of forming the first fin 101 further includes: after providing the substrate 100, before etching the substrate 100, a mask layer 103 is formed on the substrate 100. The mask layer 103 is used as an etching mask for etching the substrate 100 to form the first fin portion 101.
In this embodiment, the mask layer 103 is made of SiN. In other embodiments, the mask layer may be further made of SiON, siCN, siOCN, or SiBCN.
Referring to fig. 5 to 6, after the forming of the initial fin portion, the method further includes: a second isolation layer 105 is formed on the first substrate 104 exposed by the first fin 101 (as shown in fig. 6).
The second isolation layer 105 is made of an insulating material, and the second isolation layer 105 is used for electrically isolating adjacent first fins 101 in the first region I.
In this embodiment, the material of the second isolation layer 105 is silicon oxide. In other embodiments, the material of the second isolation layer may also be silicon oxynitride, silicon nitride, silicon oxycarbonitride, or amorphous carbon.
The step of forming the second isolation layer 105 includes: forming a second isolation material layer 106 covering the first fin portion 101; performing planarization treatment on the second isolation material layer 106 until the mask layer 103 is exposed; after the mask layer 103 is exposed, the mask layer 103 is used as a mask to etch back the second isolation material layer 106 with a certain thickness, and the remaining second isolation material layer 106 is used as a second isolation layer 105.
In this embodiment, the second isolation material layer 106 is formed by a Flowable Chemical Vapor Deposition (FCVD) process.
Note that the second isolation layer 105 is also formed on the first substrate 104 in the second region II.
Referring to fig. 7 to 8, the substrate 100 in the second region II is etched to form second fins 107 (as shown in fig. 8) and second recesses 110 (as shown in fig. 8) located between the second fins 107; the depth of the second groove 110 is greater than the depth of the first groove 102 (shown in fig. 2); the second fin portion 107 includes a bottom fin portion 1071 and a top fin portion 1072 on the bottom fin portion 1071, and a width of the bottom fin portion 1071 is greater than a width of the top fin portion 1072 in an extending direction perpendicular to the second fin portion 107.
And forming a first isolation layer in the second groove 110, wherein after the first isolation layer is formed, a Si-H bond and a Si-O bond generally exist in the first isolation layer, and annealing the first isolation layer, wherein the annealing breaks the Si-H bond and the Si-O bond, and the material of the first isolation layer becomes denser, but the first isolation layer is also easily deformed, so that the first isolation layer has a larger stress. The second fin portion 107 includes a bottom fin portion 1071 and a top fin portion 1072 located on the bottom fin portion 1071, and the bottom fin portion 1071 is wider than the top fin portion 1072 along a direction perpendicular to an extending direction of the second fin portion 107, and compared with a case that the entire width of the second fin portion 107 is equal to the width of the top fin portion 1072, the second fin portion 107 according to the embodiment of the present invention has a higher rigidity by increasing the width of the bottom fin portion 1071, and the second fin portion 107 has a correspondingly higher ability to bear the stress of the first isolation layer, so that a probability that the second fin portion 107 is bent due to the stress of the first isolation layer is reduced, and further, the performance and the performance uniformity of the device are improved.
Moreover, the thermal dissipation coefficient of the first isolation layer is generally smaller than the thermal dissipation coefficient of the second fin 107. By making the width of the bottom fin portion 1071 larger than the width of the top fin portion 1072, the volume of the bottom fin portion 1071 and the contact area between the second fin portion 107 and the second substrate 109 located below the second fin portion 107 are increased, so that the heat dissipation performance of the device is correspondingly improved, the self-heating effect (self-heating effect) of the device is improved, and further the electrical performance of the semiconductor structure is optimized.
As shown in fig. 7 to 8, specifically, the step of forming the second fin portion 107 includes: forming a cap layer 108 on the sidewalls of the initial fin portion in the second region II (as shown in fig. 8); and etching the first substrate 104 with the exposed initial fin portion in the second region II by using the cap layer 108 as a mask, wherein the remaining etched first substrate is used as a second substrate 109, and the protrusion on the second substrate 109 is used as the second fin portion 107.
In this embodiment, the first substrate 104 exposed from the initial fin portion in the second region II is etched by using the cap layer 108 as a mask, so as to form a second fin portion 107 and a second groove 110 located between the second fin portions 107. In the process of forming the second fin portion 107 by etching, the cap layer 108 on the sidewall of the initial fin portion is used as a mask, so that the bottom fin portion 1071 is wider than the top fin portion 1072 in a direction perpendicular to the extending direction of the initial fin portion, and the thickness of the cap layer 108 determines the width difference between the bottom fin portion 1071 and the top fin portion 1072 in the second fin portion 107.
In the process of forming the second fin 107, the etching rate of the cap layer 108 is smaller than that of the first substrate 104, so that the cap layer 108 can function as an etching mask, and the bottom fin 1071 is wider than the top fin 1072.
In this embodiment, the material of the cap layer 108 includes SiN. In other embodiments, the material of the cap layer includes SiCN, siOCN or SiBCN.
It should be noted that the cap layer 108 is not too thick nor too shallow. If the cap layer 108 is too thick, too much process time is needed to form the cap layer 108, and compared with the top fin portion 1072, the bottom fin portion 1071 is too wide and correspondingly perpendicular to the direction of the second fin portion 107, the width of the second groove 110 is too narrow, and the subsequent first isolation layer formed on the second substrate 109 exposed by the second fin portion 107 cannot well realize electrical isolation of adjacent devices; if the cap layer 108 is too shallow, the width of the bottom fin 1071 is too small, and after the first isolation layer is annealed, the second fin 107 is easy to bend under the stress of the first isolation layer, so that the uniformity of the performance of the semiconductor device is poor. In this embodiment, the capping layer 108 has a thickness of 3 nm to 10 nm.
The step of forming the cap layer 108 includes: forming a capping material layer 114 conformally covering the initial fin (as shown in fig. 7); in the second region II, the cap material layer 114 on the top of the initial fin portion is removed, and the cap material layer 114 on the sidewall of the initial fin portion of the second region II is remained as the cap layer 108.
In this embodiment, the capping material Layer 114 is formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process.
It should be noted that after the initial fin portion is formed and before the cap layer 108 is formed, the second isolation layer 105 is formed on the first substrate 104 exposed from the initial fin portion, so that the cap material layer 114 conformally covers the second isolation layer 105 exposed from the initial fin portion in addition to the initial fin portion.
It should be noted that, in the process of etching the first substrate 104 exposed from the initial fin portion in the second region II by using the capping layer 108 as a mask, the mask layer 103 also serves as an etching mask. That is, the cap layer 108 and the mask layer 103 together serve as a mask for etching the etching mask of the first substrate 104 in the second region II.
The forming method of the semiconductor structure further comprises the following steps: after forming the cap material layer 114, a protection layer 111 is formed on the cap material layer 114 in the first region I before removing the cap material layer 114 on top of the initial fin.
The protective layer 111 is configured to protect the first fin portion 101 in the first region I during a process of forming the second fin portion 107, so as to prepare for forming a device on the first fin portion 101 subsequently; the protection layer 111 also protects the capping material layer 114 in the first region I during the formation of the second fin 107, and the capping material layer 114 protects the second isolation layer 105 from damage during the subsequent formation of the first isolation layer.
In this embodiment, the material of the protection layer 111 is an organic material. The protective layer 111 of the material is easy to remove and difficult to leave residues in subsequent processes.
Specifically, in the embodiment, the material of the protection layer 111 may be a bottom-anti-reflective coating (BARC) material, an Organic Dielectric Layer (ODL) material, a photoresist, a dielectric anti-reflective coating (DARC) material, a Deep ultraviolet Light Absorbing Oxide (DUO) material, or an Advanced Patterning Film (APF) material.
In this embodiment, a spin coating process is used to form a protective layer 111 on the cap material layer 114 in the first region I.
Accordingly, the step of forming the second fin 107 includes: etching the cap material layer by taking the protective layer 111 as a mask to form a cap layer 108; after the cap layer 108 is formed, etching the second isolation layer 105 by using the cap layer 108 and the protection layer 111 as masks; after the second isolation layer 105 is etched, the first substrate 104 in the second region II is etched by using the cap layer 108 and the protection layer 111 as masks, so as to form second fins 107 and second grooves 110 located between the second fins 107.
Referring to fig. 9, after the second fin 107 is formed, the cap layer 108 is removed (as shown in fig. 8).
The cap layer 108 is removed in preparation for subsequent device formation on the second fin 107.
In this embodiment, a wet etching process is used to remove the cap layer 108. In the process of removing the cap layer 108 by wet etching, the etched rate of the cap layer 108 is greater than that of the second fin portion 107.
In this embodiment, the capping layer 108 is made of silicon nitride, and accordingly, the capping layer 108 is removed by using a phosphoric acid solution.
Referring to fig. 10, after removing the cap layer 108, the protective layer 111 is removed.
In this embodiment, the protective layer 111 is made of a BARC material, and the BARC material is an organic material, which is volatile at high temperature and pollutes the machine. Therefore, the protective layer 111 is removed before the first isolation layer is formed, and the protective layer 111 is prevented from volatilizing to pollute the machine in the process of forming the first isolation layer.
In this embodiment, the protective layer 111 is removed by using an ashing process or a dry etching process.
Referring to fig. 11 and 12, a first isolation layer 112 (shown in fig. 12) is formed in the second recess 110 (shown in fig. 10), the first isolation layer 112 covering at least the bottom fin portion 1071.
Generally, the first isolation layer 112 has a thickness greater than that of the second isolation layer 105, so that it is not easily penetrated between the source and drain electrodes formed in the top fin 1072, and the first isolation layer 112 is thicker to better isolate the device.
Specifically, the step of forming the first isolation layer 112 includes: forming the first isolation material layer 113 covering the second fin 107 (as shown in fig. 11); performing planarization treatment on the first isolation material layer 113 until the mask layer 103 is exposed; after the mask layer 103 is exposed, the mask layer 103 is used as a mask to etch back the first isolation material layer 113 with a certain thickness, and the remaining first isolation material layer 113 is used as a first isolation layer 112.
In this embodiment, the first isolation material layer 113 is formed by a flow chemical vapor deposition process.
In this embodiment, after forming the first isolation layer 112, the top of the first isolation layer 112 is lower than the top of the second isolation layer 105, so as to prepare for removing the cap material layer 114 in the first region I. Specifically, the capping material layer 114 is higher than the first and second spacers 112, 105, such that the capping material layer 114 is more easily removed.
Note that, the first isolation material layer 113 is also formed on the cap material layer 114 in the first region I. In the process of etching back the first isolation material layer 113 to form the first isolation layer 105, the cap material layer 114 functions as an anti-etching layer, so that the second isolation layer 105 is prevented from being etched by mistake.
It should be noted that, in other embodiments, the second isolation layer may not be formed after the formation of the initial fin portion. Correspondingly, in the step of forming the first isolation layer, the first isolation layer is also formed in the first groove, and the tops of the isolation layers in the first groove and the second groove are flush.
Referring to fig. 13, after the first isolation layer 112 is formed, the cap material layer 114 is removed.
The capping material layer 114 is removed in preparation for subsequent semiconductor fabrication.
In this embodiment, a wet etching process is used to remove the cap material layer 114. During the wet etching process, the cap material layer 114 is etched at a rate greater than the etching rates of the first isolation layer 112 and the second isolation layer 105. In other embodiments, the cap material layer may be removed by a combination of wet and dry processes.
In this embodiment, the cap material layer 114 is made of silicon nitride, and correspondingly, the adopted etching solution is a phosphoric acid solution.
Fig. 14 to fig. 20 are schematic structural diagrams corresponding to steps in another embodiment of the method for forming a semiconductor structure of the present invention.
The same parts of this embodiment as those of the previous embodiment will not be described herein again. The present embodiment is different from the previous embodiment in that: after forming the second fin 202 (as shown in fig. 15), the first fin 210 is formed (as shown in fig. 19).
Referring to fig. 14 and 15, the base 200 of the second region II is etched to form a second substrate 201 (as shown in fig. 15) and an initial fin 202 (as shown in fig. 15) protruding from the second substrate 201.
Specifically, the step of forming the initial fin portion 202 includes: forming a first mask layer 204 on the second region II, and etching the base 200 in the second region II by using the first mask layer 204 as a mask to form a second substrate 201 and an initial fin 202 protruding from the second substrate 201.
In this embodiment, the first mask layer 204 is made of silicon nitride. In other embodiments, the material of the first mask layer may also be one or more of silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The forming step of the semiconductor structure comprises the following steps: before etching the substrate 200 in the second region II, a first shielding layer 203 is also formed on the substrate 200 in the first region I.
During the formation of the second fin 202, the first shielding layer 203 protects the substrate 200 in the first region I from etching.
The step of forming the first blocking layer 203 and the first mask layer 204 includes: forming a shielding material layer covering the substrate 200; forming a photoresist layer (not shown in the figure) on the shielding material layer, etching the shielding material layer by using the photoresist layer as a mask to form a first shielding layer 203 in the first region I, and forming a first mask layer 204 in the second region II.
Referring to fig. 16, a protection layer 205 is formed on the second substrate 201 exposed by the preliminary fin 202 (as shown in fig. 15), and the protection layer 205 covers a portion of the sidewalls of the preliminary fin 202.
In the subsequent oxidation process of the initial fin portion 202 exposing the protection layer 205, the sidewalls of the initial fin portion 202 covered by the protection layer 205 are not oxidized, so as to prepare for the subsequent formation of a second fin portion.
In this embodiment, the protection layer 205 is an organic material. The protective layer 205 is removed in a subsequent process, and is not likely to remain.
Specifically, the material of the protection layer 205 is a BARC material. In other embodiments, the material of the protection layer may also be an ODL material, a photoresist, a DARC material, a DUO material, or an APF material.
With reference to fig. 16 and with reference to fig. 17, the sidewalls of the initial fin portion 202 exposed from the protection layer 205 are oxidized to convert the initial fin portion 202 with a partial width into an oxide layer 207, and the remaining initial fin portion 202 serves as the second fin portion 206.
In this embodiment, a thermal oxidation process is used to oxidize the sidewalls of the initial fin portion 202, so as to convert the partial width of the initial fin portion 202 into the oxide layer 207.
Specifically, the process parameters of the thermal oxidation treatment include: the process temperature is 700 ℃ to 1000 ℃, and the process time is 100S to 1000S; the pressure of the chamber is 50to 300torr; the flow rate of oxygen is 1/20 liter/minute to 1/5 liter/minute; the flow rate of nitrogen gas is 1/20 liter/minute to 1/5 liter/minute.
In this embodiment, the initial fin 202 is made of silicon, and the oxide layer 207 is made of silicon oxide.
Since the sidewalls of the initial fin 202 exposing the protection layer 205 are converted into the oxide layer 207, the second fin 206 exposing the protection layer 205 is a top fin 2062 and the protection layer 205 is a bottom fin 2061. After the oxide layer 207 is subsequently removed, the bottom fin portion 2061 is wider than the top fin portion 2062 perpendicular to the extending direction of the second fin portion 206.
In the second region II, the region between the second fins 206 is a second groove 214 (as shown in fig. 17), and the subsequent process further includes forming an isolation layer in the second groove 214, where the thermal coefficient of the isolation layer is generally smaller than that of the second fins 206. By making the width of the bottom fin 2061 greater than the width of the top fin 2062, the volume of the bottom fin 2062 and the contact area between the second fin 206 and the second substrate 201 are increased, so that the heat dissipation performance of the device is correspondingly improved, the self-heating effect (self-heating effect) of the device is improved, and the electrical performance of the semiconductor structure is further optimized.
After the isolation layer is formed subsequently, the isolation layer usually has Si-H bonds and Si-O bonds, annealing treatment is carried out on the isolation layer, the Si-H bonds and the Si-O bonds are broken through the annealing treatment, the isolation layer is made of a more compact material, but the isolation layer is easy to deform, and therefore the isolation layer has larger stress. The second fin portion 206 includes a bottom fin portion 2061 and a top fin portion 2062 located on the bottom fin portion 2061, and the bottom fin portion 2061 is wider than the top fin portion 2062 along a direction perpendicular to the extending direction of the second fin portion 206, and compared with a case that the overall width of the second fin portion 206 is equal to the width of the top fin portion 2062, in the embodiment of the present invention, the width of the bottom fin portion 2061 is increased, so that the rigidity of the second fin portion 206 is greater, and the ability of the second fin portion 206 to bear the stress of the isolation layer is correspondingly greater, thereby reducing the probability that the second fin portion 206 is bent due to the stress of the isolation layer, and further facilitating improvement of the performance and the uniformity of the device.
It should be noted that, in the first region I, the sidewall of the substrate exposed out of the protection layer 205 is also oxidized and converted into the oxide layer 207, but this portion of the oxide layer is removed in the process of forming the first fin portion subsequently, so that the oxidation treatment does not affect the formation of the subsequent first fin portion.
With continued reference to fig. 17, the oxide layer 207 (shown in fig. 15) and the protective layer 205 (shown in fig. 15) are removed.
The oxide layer 207 is removed to expose sidewalls of the top fin 2062 of the second fin 206 in preparation for subsequent device formation on the second fin 206.
In this embodiment, the oxide layer 207 is removed by a wet etching process. During the wet etching process, the etching rate of the oxide layer 207 is greater than that of the second fin portion 206.
In this embodiment, the wet etching solution is a hydrofluoric acid solution.
Removing the protection layer 205 provides for the subsequent formation of a first fin in the first region I.
In this embodiment, the protection 205 is removed by ashing.
It should be noted that, in the process of removing the oxide layer 207 and the protection layer 205, the first mask layer 204 and the first blocking layer 203 are also removed.
Referring to fig. 18, after removing the protection layer 205 of the oxide layer 207, a filling layer 208 is formed on the second substrate 201 exposed by the second fin portion 206, and the filling layer 208 covers sidewalls of the second fin portion 206.
A fin protection layer is subsequently formed on the filling layer 208, and the filling layer 208 provides support for the subsequent formation of the fin protection layer.
In this embodiment, the material of the filling layer 208 is an organic material, and is easy to remove and not easy to have residue in the subsequent process.
Specifically, the material of the filling layer 208 is a BARC material. In other embodiments, the material of the filling layer may also be an ODL material, a photoresist, a DARC material, a DUO material, or an APF material.
Referring to fig. 19, after the filling layer 208 is formed, the base 200 of the first region I is etched, and a first substrate 209 and a first fin portion 210 protruding from the first substrate 209 are formed. Between the first fins 210 is a first groove 215.
The step of forming the first fin portion 210 includes: forming a second mask layer 211 on the substrate 200 in the first region I; and etching the substrate 200 in the first region I by using the second mask layer 211 as a mask to form a first fin portion 210.
In this embodiment, the second mask layer 211 is made of silicon nitride. In other embodiments, the material of the second mask layer may also be one or more of silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
It should be noted that, in the process of forming the second mask layer 211, a fin protection layer 212 is formed on the filling layer 208 in the second region II.
In the process of forming the first fin portion 210 by etching the substrate 200 in the first region I, the fin portion protection layer 212 protects the second fin portion 206 from being etched.
It should be noted that, after the first fin portion 210 is formed, the filling layer 208 is removed.
In this embodiment, the filling layer 208 is removed by ashing.
Referring to fig. 20, an isolation layer 213 is formed in the first recess 215 (shown in fig. 19) and the second recess 214 (shown in fig. 17).
The isolation layer 213 is used to electrically isolate adjacent devices.
In this embodiment, the step of forming the isolation layer 213 includes: forming an isolation material layer (not shown) covering the first fin portion 210 and the second fin portion 206, and performing planarization on the isolation material layer until the fin protection layer 212 and the second mask layer 211 are exposed; after the fin portion protection layer 212 and the second mask layer 211 are exposed, the isolation material layer with a certain thickness is etched back by using the fin portion protection layer 212 and the second mask layer 211 as masks, the remaining isolation material layer located in the second region II serves as an isolation layer, and the remaining isolation material layer located in the first region I serves as a second isolation layer.
In this embodiment, the isolation material layer is formed by a flow chemical vapor deposition process.
The forming method of the semiconductor structure comprises the following steps: after the filling layer 208 is formed and before the isolation layer 213 is formed, the fin protection layer 212 and the second mask layer 211 are removed.
In this embodiment, the second mask layer 211 and the fin protection layer 212 are removed by a wet etching process.
Specifically, the first fin portion 210 and the fin portion protection layer 212 are made of silicon nitride, and correspondingly, the wet etching solution is a phosphoric acid solution.
In this embodiment, a first isolation layer is formed in the second groove 214, and a second isolation layer is formed in the first groove 215.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure comprises a substrate, wherein the substrate comprises a first area I and a second area II, the first area I is used for forming a first device, the second area II is used for forming a second device, and the power of the second device is lower than that of the first device; first fins 101 located on the substrate in the first region I, a region between the first fins 101 being a first groove 110 (as shown in fig. 10); second fin portions 107 located on the substrate in the second region II, a region between the second fin portions 107 being a second groove 102 (as shown in fig. 4), the second fin portions 107 including bottom fin portions 1071 and top fin portions 1072 located on the bottom fin portions 1071, a width of the bottom fin portions 1071 being greater than a width of the first fin portions 101 in an extending direction perpendicular to the second fin portions 107; wherein the depth of the second groove 102 is greater than the depth of the first groove 110; an isolation layer in the first and second grooves 110, 102, the isolation layer covering at least the bottom fin portion 1071.
The isolation layer is generally subjected to annealing treatment, and the annealing treatment breaks Si-H bonds and Si-O bonds in the isolation layer, so that the material of the isolation layer becomes denser, but the isolation layer is also easily deformed, so that the isolation layer has larger stress. The second fin portion 107 includes a bottom fin portion 1071 and a top fin portion 1072 located on the bottom fin portion 1071, and the bottom fin portion 1071 is wider than the top fin portion 1072 along a direction perpendicular to an extending direction of the second fin portion 107, and compared with a case where the overall width of the second fin portion 107 is equal to the width of the top fin portion 1072, the embodiment of the present invention increases the width of the bottom fin portion 1071 to increase the rigidity of the second fin portion 107, and accordingly the ability of the second fin portion 107 to bear the stress of the isolation layer is greater, thereby reducing the probability that the second fin portion 107 is bent due to the stress of the isolation layer, and further facilitating improvement of the performance and the uniformity of the performance of the device.
In this embodiment, the first device is located in the first region I, the second device is located in the second region II, and the power of the second device is lower than that of the first device.
In this embodiment, the substrate, the first fin 101, and the second fin 107 are made of the same material. In other embodiments, the materials of the substrate, the first fin 101 and the second fin 107 may also be different.
In this embodiment, the substrate is made of silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, in order to improve the performance of the device, a SiGe channel technology may be further adopted, that is, the material of the substrate includes silicon germanium, and the material of the corresponding fin portion and the channel layer formed subsequently is SiGe. The surface of the substrate can also be provided with an interface layer, and the interface layer is made of silicon oxide, silicon nitride, silicon oxynitride or the like.
In this embodiment, the top fin 1072 and the first fin 101 have the same width.
The difference between the widths of the top fin portion 1072 and the bottom fin portion 1071 should not be too large or too small. If the width difference between the top fin portion 1072 and the bottom fin portion 1071 is too large, the rigidity difference between the top fin portion 1072 and the bottom fin portion 1071 is too great, and the rigidity of the top fin portion 3032 is relatively insufficient; if the difference between the top fin portion 1072 and the bottom fin portion 1071 is too small, the width of the bottom fin portion 1071 will be too small, the rigidity of the bottom fin portion 1071 will be insufficient, and the stress in the isolation layer will bend the bottom fin portion 1071, resulting in a less uniform performance of the semiconductor device. In this embodiment, the width difference between the top fin portion 1072 and the bottom fin portion 1071 is 6 nm to 20 nm.
In this embodiment, the isolation layer is made of an insulating material, and the isolation layer is used to achieve electrical isolation between the fin portions on the substrate.
In this embodiment, the isolation layer is made of silicon oxide. In other embodiments, the material of the isolation layer may also be an insulating material such as silicon oxynitride, silicon nitride, silicon oxycarbonitride, or amorphous carbon.
The thermal coefficient of the isolation layer is generally less than the thermal coefficient of the second fin 107. By making the width of the bottom fin portion 1071 larger than the width of the top fin portion 1072, the volume of the bottom fin portion 1071 and the contact area between the second fin portion 107 and the second substrate at the bottom of the second fin portion 107 are increased, so that the heat dissipation performance of the device is correspondingly improved, the self-heating effect (self-heating effect) of the device is improved, and the electrical performance of the semiconductor structure is further optimized.
The thermal coefficient of the silicon is greater than the thermal coefficient of the silicon oxide, the bottom fin portion 1071 is wider than the top fin portion 1072 in a direction perpendicular to the extending direction of the second fin portion 107, and the volume of the second fin portion 107 is larger than that in a case where the entire width of the second fin portion is equal to that of the top fin portion 1072, so that the second fin portion 107 has a higher thermal dissipation capability.
It should be noted that the isolation layer located in the first groove 110 is the second isolation layer 105, and the isolation layer located in the second groove 102 is the second isolation layer 105. The top surface of the second spacer layer 105 is lower than the top surface of the first spacer layer 112. In other embodiments, the top surfaces of the isolation layer in the first recess 110 and the isolation layer in the second recess 102 are flush.
In the present embodiment, the depth of the first recess 110 is greater than the depth of the second recess 102, and generally, the thickness of the second isolation layer 105 in the first recess 110 is less than the thickness of the first isolation layer 112 in the second recess 102. The first isolation layer 112 is thicker than the second isolation layer 105, so that the source and the drain in the second region II are not easily penetrated, and the first isolation layer 112 can better isolate the device.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and it is intended that the scope of the embodiments of the invention be limited only by the terms of the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for forming a first device, the second area is used for forming a second device, and the power of the second device is lower than that of the first device;
etching the substrate of the first region to form first fin parts and first grooves located among the first fin parts;
etching the substrate of the second region to form second fin parts and second grooves located among the second fin parts, wherein the second fin parts comprise bottom fin parts and top fin parts located on the bottom fin parts, and the width of the bottom fin parts is larger than that of the top fin parts in the extending direction perpendicular to the second fin parts; wherein the depth of the second groove is greater than the depth of the first groove;
forming a first isolation layer in the second groove, wherein the first isolation layer at least covers the bottom fin part;
the step of forming the first and second fin portions includes:
etching the bases of the first region and the second region to form a first substrate and an initial fin portion located on the first substrate, wherein the initial fin portion located on the first region serves as the first fin portion;
forming a cap layer on the side wall of the initial fin part of the second region;
etching the first substrate exposed from the initial fin portion in the second region by using the cap layer as a mask, wherein the rest of the first substrate after etching is used as a second substrate, and the protrusion on the second substrate is used as the second fin portion;
after the second fin part is formed, removing the cap layer; or,
the step of forming the first and second fin portions includes:
etching the base of the second region to form a second substrate and an initial fin part protruding out of the second substrate;
forming a protective layer on the second substrate exposed out of the initial fin portion, wherein the protective layer covers part of the side wall of the initial fin portion;
oxidizing the exposed side wall of the initial fin part of the protective layer, converting the initial fin part with partial width into an oxide layer, and taking the rest initial fin part as the second fin part;
removing the oxide layer and the protective layer;
after the oxide layer and the protective layer are removed, a filling layer is formed on the second substrate exposed out of the second fin portion, and the filling layer covers the side wall of the second fin portion;
and after the filling layer is formed, etching the base of the first region to form a first substrate and a first fin part protruding out of the first substrate.
2. The method of forming a semiconductor structure of claim 1,
forming the second fin portion after forming the first fin portion;
or forming the first fin portion after forming the second fin portion.
3. The method of forming a semiconductor structure of claim 1, wherein the step of forming the cap layer comprises: forming a cap material layer conformally covering the initial fin portion;
and in the second region, removing the cap material layer on the top of the initial fin part, and reserving the cap material layer on the side wall of the initial fin part in the second region as the cap layer.
4. The method of claim 3, wherein after forming the cap material layer, prior to removing the cap material layer on top of the initial fin, further comprising: forming a protective layer on the cap material layer of the first area;
and removing the protective layer after removing the cap layer.
5. The method of forming a semiconductor structure of claim 1, wherein after forming the initial fin portion and before forming the cap layer, further comprising: forming a second isolation layer on the first substrate exposed out of the initial fin part;
in the step of forming a first isolation layer in the second recess, a top of the first isolation layer is lower than a top of the second isolation layer.
6. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a first isolation layer, the first isolation layer is also formed in the first recess.
7. The method of claim 1, wherein the cap layer is made of one or more of SiN, siCN, siOCN, or SiBCN.
8. The method of claim 3, wherein the capping material layer is formed using a chemical vapor deposition process or an atomic layer deposition process.
9. The method of forming a semiconductor structure of claim 1, wherein the cap layer has a thickness of 3 nm to 10 nm.
10. The method of forming a semiconductor structure of claim 1, wherein the cap layer is removed using a wet etch process.
11. The method of forming a semiconductor structure of claim 10, wherein the cap layer is removed using a phosphoric acid solution.
12. The method for forming a semiconductor structure according to claim 4, wherein a material of the protective layer is an organic material.
13. The method of claim 4, wherein the protective layer is formed of a BARC material, an ODL material, a photoresist, a DARC material, a DUO material, or an APF material.
14. The method of forming a semiconductor structure of claim 1, wherein said oxidizing process is a thermal oxidation process.
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