CN104124210A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN104124210A CN104124210A CN201310156924.6A CN201310156924A CN104124210A CN 104124210 A CN104124210 A CN 104124210A CN 201310156924 A CN201310156924 A CN 201310156924A CN 104124210 A CN104124210 A CN 104124210A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 170
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 137
- 230000002093 peripheral effect Effects 0.000 claims abstract description 69
- 238000003860 storage Methods 0.000 claims abstract description 62
- 230000005669 field effect Effects 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 13
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 125000006850 spacer group Chemical group 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000012528 membrane Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000005641 tunneling Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 109
- 238000001312 dry etching Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A method for forming a semiconductor structure comprises the steps of providing a semiconductor substrate, forming a plurality of split stacking structures on the semiconductor substrate, enabling first silicon oxide layers in the stacking structures of a storage region to serve as tunneling oxidation layers of a flash memory unit, and enabling a first polycrystalline silicon layer to serve as a floating gate of the flash memory unit; utilizing the stacking structures as masks to etch the semiconductor substrate, forming first grooves in a peripheral region and the storage region of the semiconductor substrate, enabling the semiconductor substrate between the adjacent first grooves in the peripheral region to form a first fin; forming an isolation layer on the semiconductor substrate and performing etching to remove part of the isolation layer of the peripheral region; removing the stacking structures on the peripheral region and exposing the top surface of the first fin; forming a first gate structure of a fin type field-effect transistor on a side wall and the top surface of the first fin of the peripheral region, and forming a control gate of the flash memory unit on the floating gate of the storage region. A process for forming the flash memory unit is compatible with a process for manufacturing the fin type field-effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of semiconductor structure.
Background technology
In current semiconductor industry, integrated circuit (IC) products mainly can be divided into three major types type: analog circuit, digital circuit and DA combination circuit, wherein memory device is an important kind in digital circuit.In recent years, in memory device, the development of flash memory (flash memory is called for short flash cell) is particularly rapid.The main feature of flash cell is can keep for a long time canned data in the situation that not powering up; And have that integrated level is high, access speed is fast, be easy to wipe and the advantage such as rewriting, thereby be widely used in multinomial fields such as microcomputer, automation controls.
Erasable Programmable Read Only Memory EPROM (Electrically Erasable Programmable ROM, EEPROM) has obtained applying very widely as the important flash memory of one.Fig. 1 is the cross-sectional view of a memory cell of the Erasable Programmable Read Only Memory EPROM (EEPROM) of prior art formation, and described EEPROM memory cell, comprising: Semiconductor substrate 100, be positioned at the discrete memory transistor 10 in described Semiconductor substrate 100 and select transistor 20, described memory transistor 10 comprises the gate stack that is positioned at Semiconductor substrate 100 surfaces and drain region and the source region 109 that is positioned at gate stack semiconductor substrates on two sides 100, described selection transistor 20 comprises the gate stack that is positioned at Semiconductor substrate 100 surfaces and drain region 107 and the source region that is positioned at gate stack semiconductor substrates on two sides 100, the source region of the drain region of described memory transistor 10 and selection transistor 20 is mutually overlapping, form co-doped district 108, described co-doped district 108 realizes memory transistor 10 and selects the connection between transistor 20.The gate stack of described memory transistor 10 comprises the tunnel oxide 101, floating boom 102, control gate oxide layer 103 and the control gate 104 that are positioned at successively Semiconductor substrate 100 surfaces, and described floating boom 102 is for stored charge; The gate stack of described selection transistor 20 comprises gate oxide 105 and the gate electrode 106 on Semiconductor substrate 100 surfaces successively.Described Semiconductor substrate 100 is also formed with N trap, and described drain region 107, source region 109 and co-doped district 108 are the doping of P type.
The process that described memory cell is carried out erase operation is: selecting the gate electrode 106(of transistor 20 to be connected with word line) be connected with source line with the source region 109(of memory transistor 10) positive voltage applied, control gate at memory transistor 10 applies negative voltage, the drain region 107(that selects transistor 20 is connected with bit line simultaneously) be set to open a way, in the floating boom 102 of memory transistor 10, the electronics of storage is transferred in drain region 109 by tunnel oxide 101, realizes memory cell and carries out erase operation process.
The manufacture craft of existing flash memory conventionally can be compatible mutually with the manufacture craft of peripheral circuit midplane MOS transistor; but in the time that semiconductor technology enters 30 nanometers with lower node; traditional plane formula MOS transistor dies down to the control ability of channel current, causes serious leakage current.And fin formula field effect transistor (FinFET) is as a kind of emerging multiple-grid device, compared with plane MOS transistor, fin formula field effect transistor can improve drive current in the very low cut-off current of maintenance, can effectively suppress short-channel effect, therefore fin formula field effect transistor is applied in the peripheral circuit of flash memory also must become a kind of trend in the future.Fig. 2 shows the perspective view of a kind of fin formula field effect transistor of prior art.As shown in Figure 2, comprising: Semiconductor substrate 10, in described Semiconductor substrate 10, be formed with the fin 14 of protrusion, fin 14 is generally by obtaining after Semiconductor substrate 10 etchings; Dielectric layer 11, covers the part of the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across on described fin 14, covers top and the sidewall of described fin 14, and grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.
The fin 14 of existing fin formula field effect transistor normally forms by etching semiconductor substrate 10.
Due to the huge otherness of the structure of fin formula field effect transistor and the structure of flash memory, therefore, both compatible manufacture crafts of fin formula field effect transistor and flash memory face great challenge.
Summary of the invention
The problem that the present invention solves is to provide a kind of compatible technology of making fin formula field effect transistor transistor and flash memory.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of semiconductor structure, the formation method of semiconductor structure, comprise: Semiconductor substrate is provided, described Semiconductor substrate comprises outer peripheral areas and storage area, on the outer peripheral areas of described Semiconductor substrate and storage area, be formed with some the first discrete silicon oxide layers, be positioned at the first polysilicon layer in the first oxide layer and be positioned at the stacked structure that the first mask layer on the first polysilicon layer forms, the first silicon oxide layer in the stacked structure of the storage area of Semiconductor substrate is as the tunnel oxide of flash cell, the first polysilicon layer is as the floating boom of flash cell, taking described some discrete stacked structures as mask, Semiconductor substrate described in etching, in the outer peripheral areas of Semiconductor substrate and storage area, form some the first discrete grooves, Semiconductor substrate in the outer peripheral areas of Semiconductor substrate between adjacent the first groove forms the first fin, and the Semiconductor substrate between adjacent the first groove in the storage area of Semiconductor substrate forms the second fin, in described Semiconductor substrate, form separator, described separator covers described stacked structure and fills full the first groove, and the surface of separator is concordant with the surface of the first mask layer, etching is removed the part separator of outer peripheral areas of Semiconductor substrate, exposes stacked structure in the outer peripheral areas of Semiconductor substrate and the partial sidewall surface of the first fin, remove the stacked structure in the outer peripheral areas of Semiconductor substrate, expose the top surface of the first fin, the first mask layer on the storage area of removal Semiconductor substrate, form the first grid structure of fin formula field effect transistor at the sidewall of the first fin of the outer peripheral areas of Semiconductor substrate and top surface, on the floating boom of the storage area of described Semiconductor substrate, form the control gate of flash cell.
Optionally, the formation method of described stacked structure is: in described Semiconductor substrate, be formed with the first silicon oxide film, the first polysilicon membrane and the first mask film; Etching is removed part described the first mask film, the first polysilicon layer film and the first silicon oxide film successively, on the outer peripheral areas of Semiconductor substrate and storage area, forms the stacked structure that some the first discrete silicon oxide layers, the first polysilicon layer and the first mask layer form.
Optionally, the material of described separator is silica.
Optionally, the forming process of described separator is: form the spacer material layer that covers described stacked structure and Semiconductor substrate, described spacer material layer is filled full the first groove; Spacer material layer described in planarization, taking the first mask layer as stop-layer, forms separator.
Optionally, before etching is removed the part separator of outer peripheral areas of Semiconductor substrate, also comprise: on described separator, form the second mask layer, in the second mask layer, there is the outer peripheral areas insulation surface of exposing semiconductor substrate and first opening on stacked structure surface.
Optionally, described the second mask material is photoresist.
Optionally, in described the second mask layer, there are some second openings of the separator of part stacked structure on exposing semiconductor substrate storage area and described part stacked structure both sides.
Optionally, when described etching is removed the part separator of outer peripheral areas of Semiconductor substrate, remove the part separator that the second opening exposes, the surface of the remaining separator of the second open bottom is lower than the top surface of the second fin simultaneously.
Optionally, when stacked structure in the outer peripheral areas of described removal Semiconductor substrate, remove the part stacked structure on the Semiconductor substrate storage area that the second opening exposes, the top surface of exposed portions serve the second fin simultaneously.
Optionally, the forming process of described first grid structure and control gate is: remove described the second mask layer; Form the second silicon oxide film of the floating boom on the storage area that covers described Semiconductor substrate, separator, the first fin and Semiconductor substrate; On described the second silicon oxide film, form the second polysilicon membrane; Etching is removed described the second polysilicon membrane of part and the second silicon oxide film successively, on the sidewall of the first fin of the outer peripheral areas of Semiconductor substrate and top surface, form first grid dielectric layer and be positioned at the first grid electrode on first grid dielectric layer, on the floating boom of the storage area of described Semiconductor substrate, form isolation oxidation silicon layer and be positioned at the control grid on isolation oxidation silicon layer, wherein said first grid dielectric layer and first grid electrode form the first grid structure of fin formula field effect transistor, and isolation oxidation silicon layer and control grid form the control gate of flash cell.
Optionally, in forming first grid structure and control gate, form the second grid structure of the selection MOS transistor of flash cell at the second fin top surface of Semiconductor substrate storage area.
Optionally, described Semiconductor substrate is carried out to Implantation, in the first fin of the both sides of first grid structure, form the source/drain region of fin formula field effect transistor, in the second fin of second grid structure both sides, form the source/drain region of selecting MOS transistor.
Optionally, in forming first grid structure and control gate, at the 3rd grid structure of the second fin sidewall of Semiconductor substrate storage area and the selection fin formula field effect transistor of top surface formation flash cell.
Optionally, described Semiconductor substrate is carried out to Implantation, in the first fin of the both sides of first grid structure, form the source/drain region of fin formula field effect transistor, in the second fin of the 3rd grid structure both sides, form the source/drain region of selecting fin formula field effect transistor.
Optionally, remove the upper first grid structure of the first fin, form the second groove, form high-K gate dielectric layer in sidewall and the bottom of described the second groove, on high-K gate dielectric layer, form metal gates.
Optionally, between described metal gates and high-K gate dielectric layer, be also formed with work function layer.
Optionally, the material of described the first mask layer is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon or carbon silicon oxynitride.
Optionally, the thickness of described the first mask layer is 300～800 dusts.
Optionally, the thickness of described the first silicon oxide layer is 20～60 dusts.
Optionally, the thickness of described the first polysilicon layer is 800～1200 dusts.
Compared with prior art, technical solution of the present invention has the following advantages:
In Semiconductor substrate, form some discrete stacked structures, the first silicon oxide layer in the stacked structure of the storage area of Semiconductor substrate is the floating boom as flash cell as the tunnel oxide of flash cell, the first polysilicon layer, and the stacked structure of the outer peripheral areas of Semiconductor substrate forms the mask of the first fin as etching semiconductor substrate; Then, taking described some discrete stacked structures as mask, Semiconductor substrate described in etching, in the outer peripheral areas of Semiconductor substrate and storage area, form some the first discrete grooves, Semiconductor substrate in the outer peripheral areas of Semiconductor substrate between adjacent the first groove forms the first fin, and the Semiconductor substrate between adjacent the first groove in the storage area of Semiconductor substrate forms the second fin; Then, in described Semiconductor substrate, form separator, etching is removed the part separator of outer peripheral areas of Semiconductor substrate, exposes stacked structure in the outer peripheral areas of Semiconductor substrate and the partial sidewall surface of the first fin; Then, remove the stacked structure in the outer peripheral areas of Semiconductor substrate, expose the top surface of the first fin; Form the first grid structure of fin formula field effect transistor at the sidewall of the first fin of the outer peripheral areas of Semiconductor substrate and top surface, can on the floating boom of the storage area of described Semiconductor substrate, form the control gate of flash cell simultaneously.The formation method of semiconductor structure of the present invention can compatiblely form fin formula field effect transistor in forming flash cell, and technical process is simple and convenient.
Further, in forming first grid structure and control gate, the second fin sidewall exposing at Semiconductor substrate storage area and top surface form the 3rd grid structure of the selection fin formula field effect transistor of flash cell.Because fin formula field effect transistor has the large feature of the little drive current of leakage current, selection transistor using fin formula field effect transistor as flash cell, promote greatly the performance of whole flash cell, and the selection fin formula field effect transistor of storage area can form with the fin formula field effect transistor of outer peripheral areas simultaneously, and processing step is comparatively easy.
Brief description of the drawings
Fig. 1 is the cross-sectional view of a flash cell of Erasable Programmable Read Only Memory EPROM of prior art formation;
Fig. 2 shows the perspective view of a kind of fin formula field effect transistor of prior art;
Fig. 3～Figure 17 is the structural representation of the formation method of embodiment of the present invention semiconductor structure.
Embodiment
Say as background technology, the formation method of existing fin formula field effect transistor and the manufacture method of flash memory are difficult to compatibility.
The embodiment of the present invention provides a kind of formation method of semiconductor structure, in forming flash cell, forms fin formula field effect transistor, and process is simple and convenient.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 3～Figure 17 is the structural representation of the formation method of embodiment of the present invention semiconductor structure.
First, with reference to figure 3, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 comprises outer peripheral areas 31 and storage area 32, outer peripheral areas 31 can be adjacent or non-conterminous with storage area 32, on the outer peripheral areas 31 of described Semiconductor substrate 300 and storage area 32, be formed with some the first discrete silicon oxide layers 301, be positioned at the first polysilicon layer 302 in the first oxide layer 301 and be positioned at the stacked structure 33 that the first mask layer 303 on the first polysilicon layer 302 forms, the first silicon oxide layer 301 in the stacked structure 33 of the storage area 32 of Semiconductor substrate 300 is as the tunnel oxide of flash cell, the first polysilicon layer 302 is as the floating boom of flash cell.
Concrete, described stacked structure 33 forming processes are: in described Semiconductor substrate 300, form successively successively the first silicon oxide film, the first polysilicon membrane, the first mask film, patterned photoresist layer; Taking described patterned photoresist layer as mask, the first mask film, the first polysilicon membrane and the first silicon oxide film described in etching successively, forms the stacked structure 33 that the first silicon oxide layer 301, the first polysilicon layer 302 and the first mask layer 303 form.
The quantity of the stacked structure 33 forming on described storage area 32 is more than or equal to 2, between stacked structure 33, be parallel to each other, and there is equal spacing and identical length and width, the follow-up flash cell that is used to form array arrangement of stacked structure 33, the width of stacked structure 33 and length are set according to concrete application.
The width of the stacked structure 33 forming in described outer peripheral areas 31 is relevant to the width of the fin of fin formula field effect transistor to be formed, the mask when stacked structure 33 forming in outer peripheral areas 31 forms the first fin as subsequent etching Semiconductor substrate 300.Stacked structure 33 quantity that form in outer peripheral areas 31 are more than or equal to 1, between the adjacent stacks structure 33 forming, can be parallel to each other or not parallel in outer peripheral areas 31, and the width of adjacent stacks structure 33 and length can equate or is unequal.
The stacked structure 33 forming in outer peripheral areas 31 equates with the width of the stacked structure 33 forming in outer peripheral areas 31 or is unequal.
The material of described the first mask layer 303 is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon or carbon silicon oxynitride, and in the present embodiment, the material of described the first mask layer 303 is silicon nitride, and the thickness of described the first mask layer 303 is 300～800 dusts.
The thickness of described the first silicon oxide layer 301 is 20～60 dusts.
The thickness of described the first polysilicon layer 303 is 800～1200 dusts.
Then, with reference to figure 4 and Fig. 5, Fig. 5 is the cross-sectional view of Fig. 4 along line of cut AB direction, taking described some discrete stacked structures 33 as mask, Semiconductor substrate 300 described in etching, in the outer peripheral areas 31 of Semiconductor substrate 300 and storage area 32, form some the first discrete grooves 304, Semiconductor substrate 300 in the outer peripheral areas 31 of Semiconductor substrate 300 between adjacent the first groove 304 forms the first fin 305, and the Semiconductor substrate 300 between adjacent the first groove 304 in the storage area 32 of Semiconductor substrate 300 forms the second fin 306.
In the present embodiment, mask while adopting the stacked structure 33 of outer peripheral areas 31 can etching semiconductor substrate 300 to form the first fin 305 and the first groove 304 for mask, the first fin 305 forming can be used as the fin of fin formula field effect transistor in peripheral circuit, the follow-up filling isolated material of groove of the first fin 305 both sides forms fleet plough groove isolation structure, for the adjacent fin formula field effect transistor of electric isolation and the electric isolation of outer peripheral areas and memory area, in forming the first fin 305, taking the stacked structure 33 of storage area 32 as mask, form the first groove 304 and the second fin 306, the follow-up filling isolated material of described the first groove 304 forms isolation structure for the adjacent row of electric isolation or the memory array cell of row, floating boom and the control gate of follow-up formation flash cell on a part of top surface of described the second fin 306, the selection MOS transistor of the follow-up formation flash cell of another part of described the second fin 306 or selection fin formula field effect transistor.
Described in etching, the method for Semiconductor substrate is dry etching, and the gas that dry etching adopts is HBr and/or Cl
2.
Described the first groove 304 be shaped as rectangle or U-shaped or V-type, the degree of depth of the first groove 304 is 50～500 nanometers.
With reference to figure 6 and Fig. 7, Fig. 7 is the cross-sectional view of Fig. 6 along line of cut AB direction, in described Semiconductor substrate 300, form separator 307, described separator 307 covers described stacked structure 33 and fills full the first groove 304(with reference to figure 4), the surface of separator 307 is concordant with the surface of the first mask layer 303; On described separator 307, form separator 307 surfaces of outer peripheral areas 31 and first opening 34 on stacked structure surface in the second mask layer 308, the second mask layers 308 with exposing semiconductor substrate.
The material of described separator 307 is silica or other suitable materials.
The forming process of described separator 307 is: the spacer material layer (not shown) of the described stacked structure 33 of described covering and Semiconductor substrate 300, described spacer material layer is filled full the first groove, and the surface of spacer material layer is higher than stacked structure 33 top surfaces; Spacer material layer described in the planarization of employing chemical mechanical milling tech, taking the first mask layer 303 as stop-layer, forms separator 307.
Described spacer material layer is individual layer or double stacked structure, because the degree of depth sum of the opening between first groove 304 degree of depth and stacked structure 33 is larger, when described spacer material layer is single layer structure, the optimal process that forms described spacer material layer is plasma enhanced chemical vapor deposition processes (PECVD), can effectively prevent from occurring in deposition process opening blockage effect (overhang).
When described spacer material layer is double stacked structure, the first-selected spin coating proceeding that adopts forms the first spacer material layer (such as silica glass); Then using plasma enhanced chemical vapor deposition processes forms the second spacer material layer on the first spacer material layer.Because spin coating proceeding has good filling perforation performance, therefore adopt spin coating proceeding and plasma enhanced chemical vapor deposition processes in the time of the first darker groove 304 of depth of cracking closure and stacked structure 33, in the spacer material layer that can make to form, the defect such as space is less, and the surperficial uniformity of the spacer material layer forming is better, when cmp planarization spacer material layer, reduced the generation of grinding phenomenon.
In the present embodiment, described the second mask layer 308 be photoresist mask, in the second mask layer 308, there is separator 307 surfaces of outer peripheral areas 31 of exposure and first opening 34 on stacked structure surface, the follow-up separator 307 that can remove along the first opening 34 etchings the segment thickness of outer peripheral areas 31 forms isolation structure in the first groove 304 of outer peripheral areas 31.
In described the second mask layer 308, also there are some second openings 35 of the separator 307 of part stacked structure 33 on exposing semiconductor substrate storage area 32 and described part stacked structure 33 both sides, some the second openings 35 and the second mask layer 308 are spaced apart along the length direction of the second fin 306, between two adjacent the second openings 35, be the second mask layer 308 of part, follow-uply cut apart storage area 32 along the second opening 35 etchings and can form some flash cell tunnel oxides and floating boom.In the present embodiment, using second opening 35 as embodiment, in follow-up etching technics, the first silicon oxide layer 301 and the first polysilicon layer 302 in storage area 32 stacked structures 33 that the second mask layer 308 covers are retained, as tunnel oxide and the floating boom of flash cell, and the separator 307 of the storage area 32 that the second mask layer 308 covers is also retained, as the isolation structure between flash cell in the adjacent column or row of flash array, the stacked structure 33 that the second opening 35 exposes is removed in subsequent technique, the part surface of the second fin 306 is exposed, thereby on the second fin 306 exposing, form the selection MOS transistor of flash cell or the source/drain electrode of selection fin formula field effect transistor and flash cell, and remove the storage area 32 segment thickness separators 307 that the second opening 35 exposes, in the first groove 304 of storage area 32, in the adjacent column or row of remaining separator 307 as flash array, select MOS transistor or select the isolation structure between fin formula field effect transistor.
In other embodiments of the invention, described the second mask layer 308 can also be other suitable materials, such as: the hard mask material layers such as titanium nitride, amorphous carbon, silicon nitride, boron nitride.
Then, with reference to figure 8 and Fig. 9, Fig. 9 is the cross-sectional view along Fig. 8 line of cut AB direction, along the first opening 34(with reference to figure 6) etching removes the part separator 307 of outer peripheral areas 31 of Semiconductor substrate, expose stacked structure in the outer peripheral areas 31 of Semiconductor substrate and the partial sidewall surface of the first fin 305, the first groove 304(of outer peripheral areas 31 is with reference to figure 4) in remaining part separator 307 as isolation structure between adjacent fin formula field effect transistor and between outer peripheral areas 31 and storage area 32, simultaneously along the second opening 35(with reference to figure 6) remove the part separator 307 that the second opening 35 exposes, the surface of the second opening 35 remaining separators 307 in bottom is lower than the top surface of the second fin 306.
Described in etching, separator 307 is dry etching, the CF that dry etching adopts
4and CHF
3, the gas that described dry etching adopts can also be NF
3and CHF
3.
In other embodiments of the invention, the surface of described remaining separator 307 also can be higher than the first fin 305 or the second fin 306 top surfaces, follow-up in the time removing the part stacked structure that the first opening 34 and the second opening 35 expose, can return etching to remaining separator 307 simultaneously, make remaining separator 307 surfaces lower than the first fin 305 or the second fin 306 top surfaces.
Then, with reference to Figure 10, Figure 11 and Figure 12, Figure 11 is the cross-sectional view of Figure 10 along AB direction, Figure 12 is the cross-sectional view of Figure 11 along CD direction, remove the first opening 34(with reference to figure 6) stacked structure in the outer peripheral areas 31 of Semiconductor substrate that exposes, expose the top surface of the first fin 305, remove the second opening 35(with reference to figure 6 simultaneously) expose Semiconductor substrate storage area 32 on part stacked structure, the top surface of exposed portions serve the second fin 306.
Removing described stacked structure is dry etching, and other of dry etching employing comprise fluorine-containing and/or chloride gas.
Then, please refer to Figure 13, Figure 14 and Figure 15, Figure 14 is the cross-sectional view of Figure 13 along AB direction, Figure 15 is the cross-sectional view of Figure 13 along CD direction, removes the second mask layer 308(on the storage area 32 of Semiconductor substrate with reference to figure 8) and stacked structure in the first mask layer 303(with reference to figure 8); Form the first grid structure 309 of fin formula field effect transistor at the sidewall of the first fin 305 of the outer peripheral areas 31 of Semiconductor substrate and top surface, on the floating boom 302 of the storage area 32 of described Semiconductor substrate, form isolation oxidation silicon layer 311 and be positioned at the control grid 312 on isolation oxidation silicon layer 311, isolation oxidation silicon layer 311 and control grid 312 and form the control gate of flash cell.
Concrete, the forming process of described first grid structure 309 and control gate is: remove described the second mask layer 308 and the first mask layer 313, form the second silicon oxide film (not shown) of the floating boom 302 on the storage area 32 that covers described Semiconductor substrate 300, separator 307, the first fin 305 and Semiconductor substrate, on described the second silicon oxide film, form the second polysilicon membrane (not shown), etching is removed described the second polysilicon membrane of part and the second silicon oxide film successively, on the sidewall of the first fin 305 of the outer peripheral areas 31 of Semiconductor substrate and top surface, form first grid dielectric layer and be positioned at the first grid electrode on first grid dielectric layer, on the floating boom 302 of the storage area 32 of described Semiconductor substrate, form isolation oxidation silicon layer 311 and be positioned at the control grid 312 on isolation oxidation silicon layer 311, wherein said first grid dielectric layer and first grid electrode form the first grid structure 309 of fin formula field effect transistor, isolation oxidation silicon layer 311 and control grid 312 form the control gate of flash cell.Before the second polysilicon membrane described in etching and the second silicon oxide film, form patterned the 3rd mask layer on described the second polysilicon membrane surface.
In the present embodiment, in forming first grid structure 309 and control gate, the second fin sidewall exposing at Semiconductor substrate storage area 32 and top surface form the 3rd grid structure 310 of the selection fin formula field effect transistor of flash cell.Because fin formula field effect transistor has the large feature of the little drive current of leakage current, selection transistor using fin formula field effect transistor as flash cell, promote greatly the performance of whole flash cell, and the selection fin formula field effect transistor of storage area 32 can form with the fin formula field effect transistor of outer peripheral areas 31 simultaneously, and processing step is comparatively easy.
In other embodiments of the invention, in forming first grid structure and control gate, form the second grid structure of the selection MOS transistor (plane MOS transistor) of flash cells at the second fin 306 top surfaces of the exposure of Semiconductor substrate storage area 32.
Finally, with reference to Figure 16 and Figure 17, Figure 16 is Figure 13 forms fin formula field effect transistor source/drain region schematic diagram along the sectional structure chart of EF direction, Figure 17 is that Figure 13 forms along the sectional structure chart of CD direction the schematic diagram of selecting transistor source/drain region, described Semiconductor substrate 300 is carried out to Implantation, in the source/drain region 313 of the interior formation fin formula field effect transistor of the first fin 305 of the both sides of first grid structure 309, select source region 314 and the drain region 315(of fin formula field effect transistor or in the second fin of second grid structure both sides, form the source/drain region of selecting MOS transistor in the interior formation of the second fin 306 of the 3rd grid structure 310 both sides).
The doping ion of described Implantation is N-type foreign ion or p type impurity ion, according to the type of the type selecting doping ion of the fin formula field effect transistor forming.
Source region 314 between floating boom 302 and the 3rd grid structure 310 is as flash cell general character doped region, and the source region in the second fin 306 of the other side of floating boom is not shown in Figure 17.
In other embodiments of the invention, also comprise: remove the first grid structure on the first fin, form the second groove, form high-K gate dielectric layer in sidewall and the bottom of described the second groove; On high-K gate dielectric layer, form work function layer; On work function layer, form metal gates, metal gates is filled full remaining the second groove.It should be noted that, in the first grid structure of removing on the first fin, can also remove second grid structure or the 3rd grid structure on the second fin, form the 3rd groove, and then interior high-K gate dielectric layer and the metal gates of forming of the 3rd groove, make the selection transistor (select MOS transistor or select fin formula field effect transistor) of storage area there is metal gates, to reduce to select the parasitic capacitance of transistor gate, improve the transistorized speed of selection, thereby improve the performance of whole flash cell.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate comprises outer peripheral areas and storage area, on the outer peripheral areas of described Semiconductor substrate and storage area, be formed with some the first discrete silicon oxide layers, be positioned at the first polysilicon layer in the first oxide layer and be positioned at the stacked structure that the first mask layer on the first polysilicon layer forms, the first silicon oxide layer in the stacked structure of the storage area of Semiconductor substrate is the floating boom as flash cell as the tunnel oxide of flash cell, the first polysilicon layer;
Taking described some discrete stacked structures as mask, Semiconductor substrate described in etching, in the outer peripheral areas of Semiconductor substrate and storage area, form some the first discrete grooves, Semiconductor substrate in the outer peripheral areas of Semiconductor substrate between adjacent the first groove forms the first fin, and the Semiconductor substrate between adjacent the first groove in the storage area of Semiconductor substrate forms the second fin;
In described Semiconductor substrate, form separator, described separator covers described stacked structure and fills full the first groove, and the surface of separator is concordant with the surface of the first mask layer;
Etching is removed the part separator of outer peripheral areas of Semiconductor substrate, exposes stacked structure in the outer peripheral areas of Semiconductor substrate and the partial sidewall surface of the first fin;
Remove the stacked structure in the outer peripheral areas of Semiconductor substrate, expose the top surface of the first fin;
The first mask layer on the storage area of removal Semiconductor substrate;
Form the first grid structure of fin formula field effect transistor at the sidewall of the first fin of the outer peripheral areas of Semiconductor substrate and top surface, on the floating boom of the storage area of described Semiconductor substrate, form the control gate of flash cell.
2. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the formation method of described stacked structure is: in described Semiconductor substrate, be formed with the first silicon oxide film, the first polysilicon membrane and the first mask film; Etching is removed part described the first mask film, the first polysilicon layer film and the first silicon oxide film successively, on the outer peripheral areas of Semiconductor substrate and storage area, forms the stacked structure that some the first discrete silicon oxide layers, the first polysilicon layer and the first mask layer form.
3. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the material of described separator is silica.
4. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the forming process of described separator is: form the spacer material layer that covers described stacked structure and Semiconductor substrate, described spacer material layer is filled full the first groove; Spacer material layer described in planarization, taking the first mask layer as stop-layer, forms separator.
5. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, before etching is removed the part separator of outer peripheral areas of Semiconductor substrate, also comprise: on described separator, form the second mask layer, in the second mask layer, there is the outer peripheral areas insulation surface of exposing semiconductor substrate and first opening on stacked structure surface.
6. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, described the second mask material is photoresist.
7. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, has some second openings of the separator of part stacked structure on exposing semiconductor substrate storage area and described part stacked structure both sides in described the second mask layer.
8. the formation method of semiconductor structure as claimed in claim 7, it is characterized in that, when described etching is removed the part separator of outer peripheral areas of Semiconductor substrate, remove the part separator that the second opening exposes, the surface of the remaining separator of the second open bottom is lower than the top surface of the second fin simultaneously.
9. the formation method of semiconductor structure as claimed in claim 7, it is characterized in that, when stacked structure in the outer peripheral areas of described removal Semiconductor substrate, remove the part stacked structure on the Semiconductor substrate storage area that the second opening exposes, the top surface of exposed portions serve the second fin simultaneously.
10. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, the forming process of described first grid structure and control gate is: remove described the second mask layer; Form the second silicon oxide film of the floating boom on the storage area that covers described Semiconductor substrate, separator, the first fin and Semiconductor substrate; On described the second silicon oxide film, form the second polysilicon membrane; Etching is removed described the second polysilicon membrane of part and the second silicon oxide film successively, on the sidewall of the first fin of the outer peripheral areas of Semiconductor substrate and top surface, form first grid dielectric layer and be positioned at the first grid electrode on first grid dielectric layer, on the floating boom of the storage area of described Semiconductor substrate, form isolation oxidation silicon layer and be positioned at the control grid on isolation oxidation silicon layer, wherein said first grid dielectric layer and first grid electrode form the first grid structure of fin formula field effect transistor, and isolation oxidation silicon layer and control grid form the control gate of flash cell.
The formation method of 11. semiconductor structures as described in claim 8 or 9 or 10, it is characterized in that, in forming first grid structure and control gate, form the second grid structure of the selection MOS transistor of flash cell at the second fin top surface of Semiconductor substrate storage area.
The formation method of 12. semiconductor structures as claimed in claim 11, it is characterized in that, described Semiconductor substrate is carried out to Implantation, in the first fin of the both sides of first grid structure, form the source/drain region of fin formula field effect transistor, in the second fin of second grid structure both sides, form the source/drain region of selecting MOS transistor.
The formation method of 13. semiconductor structures as described in claim 8 or 9 or 10, it is characterized in that, in forming first grid structure and control gate, at the 3rd grid structure of the second fin sidewall of Semiconductor substrate storage area and the selection fin formula field effect transistor of top surface formation flash cell.
The formation method of 14. semiconductor structures as claimed in claim 13, it is characterized in that, described Semiconductor substrate is carried out to Implantation, in the first fin of the both sides of first grid structure, form the source/drain region of fin formula field effect transistor, in the second fin of the 3rd grid structure both sides, form the source/drain region of selecting fin formula field effect transistor.
The formation method of 15. semiconductor structures as claimed in claim 10, it is characterized in that, remove the first grid structure on the first fin, form the second groove, high-K gate dielectric layer is formed on sidewall and bottom at described the second groove, forms metal gates on high-K gate dielectric layer.
The formation method of 16. semiconductor structures as claimed in claim 15, is characterized in that, is also formed with work function layer between described metal gates and high-K gate dielectric layer.
The formation method of 17. semiconductor structures as claimed in claim 1, is characterized in that, the material of described the first mask layer is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon or carbon silicon oxynitride.
The formation method of 18. semiconductor structures as claimed in claim 1, is characterized in that, the thickness of described the first mask layer is 300～800 dusts.
The formation method of 19. semiconductor structures as claimed in claim 1, is characterized in that, the thickness of described the first silicon oxide layer is 20～60 dusts.
The formation method of 20. semiconductor structures as claimed in claim 1, is characterized in that, the thickness of described the first polysilicon layer is 800～1200 dusts.
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