CN104103678A - U-shaped trench type semiconductor device and manufacture method thereof - Google Patents
U-shaped trench type semiconductor device and manufacture method thereof Download PDFInfo
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- CN104103678A CN104103678A CN201310111150.5A CN201310111150A CN104103678A CN 104103678 A CN104103678 A CN 104103678A CN 201310111150 A CN201310111150 A CN 201310111150A CN 104103678 A CN104103678 A CN 104103678A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000007667 floating Methods 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000009413 insulation Methods 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 2
- 238000013500 data storage Methods 0.000 abstract 1
- 238000007599 discharging Methods 0.000 abstract 1
- 230000015654 memory Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000005465 channeling Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 108010022579 ATP dependent 26S protease Proteins 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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Abstract
The invention pertains to the technical field of semiconductor memories, and specifically relates to a U-shaped trench type semiconductor device which comprises at least one semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a U-shaped trench region and a gate-control p-n junction diode for connecting the floating gate and the drain region. The U-shaped trench type semiconductor device provided in the invention uses the floating gate to store information, and perform charging and discharging on the floating gate through the gate-control p-n junction diode, so advantages of small unit area, high chip density, low operating voltage during data storage and good data rentation capability can be realized.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly a kind of semiconductor device of U-shaped raceway groove and manufacture method thereof, belong to semiconductor memory technologies field.
Background technology
Semiconductor memory is widely used among various electronic products.There is different requirements in different application field to the structure of semiconductor memory, performance and density.Such as, static random access memory (SRAM) has very high arbitrary access speed and lower integration density, and the dynamic random access memory of standard (DRAM) has very high density and medium arbitrary access speed.
Fig. 1 be prior art a kind of semiconductor memory of planar channeling, comprise: in the 501He drain region, source region 502 with the contrary doping type of Semiconductor substrate that has of Semiconductor substrate 500 interior formation, Semiconductor substrate 500 can or be the silicon on insulator for monocrystalline silicon, polysilicon.In Semiconductor substrate 500, between 501He drain region, source region 502, be formed with the planar channeling district 601 of device, planar channeling district 601 is this semiconductor memory inversion layers in Semiconductor substrate 500 interior formation when carrying out work.In 501He drain region, source region 502, be also formed with respectively the 509He doped region, doped region 510 of high-dopant concentration, 501He drain region, 510Yu source region, 509He doped region, doped region 502 has identical doping type.
On source region 501,601He drain region, channel region 502, be formed with ground floor insulation film 503, and be formed with a floating boom open area 504 in the ground floor insulation film 503 on drain region 502.On ground floor insulation film 503, cover whole planar channeling district 601 and floating boom open area 504 is formed with one as the floating boom 505 of charge-storage node, floating boom 505 has the doping type contrary with drain region 502, and the impurity in floating boom 505 can be diffused to and in drain region 502, be formed diffusion region 602 by floating boom open area 504, thereby by floating boom open area 504, between floating boom 505 and drain region 502, forms a p-n junction diode.
Cover floating boom 205 and described p-n junction diode structure and be formed with second layer insulation film 506.On second layer insulation film 506, cover and surround the control gate 507 that floating boom 505 is formed with device.Both sides at control gate 507 are also formed with grid curb wall 508.This semiconductor memory also comprise by electric conducting material, formed for the contact 511 in source region that source region 501, control gate 507, drain region 502, Semiconductor substrate 500 are connected with outer electrode, the contact 513 in the contact 512 of control gate, drain region and the contact 514 of Semiconductor substrate.
For guaranteeing the performance of semiconductor memory, the channel length that the semiconductor memory of planar channeling need to be longer, this makes the cellar area of semiconductor memory larger, thereby has reduced chip density, is unfavorable for that chip is to microminiaturized future development.
Summary of the invention
In view of this, the object of the invention is to propose a kind of semiconductor memory of U-shaped raceway groove, thereby can reduce the cellar area of semiconductor memory, improve chip density.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of semiconductor device of U-shaped raceway groove, specifically comprise:
A Semiconductor substrate with the first doping type;
The source region with the second doping type and the drain region that in described Semiconductor substrate, form;
Be recessed in described Semiconductor substrate and the U-shaped channel region forming between described source region and drain region;
On described source region and drain region and cover the ground floor insulation film that whole U-shaped channel region forms;
The floating boom open area forming at the ground floor insulation film being arranged on described drain region, described open area can be on the level semiconductor surface in drain region or on the madial wall on described U-shaped groove top;
On described ground floor insulation film, cover the floating boom with the first doping type as charge-storage node that described U-shaped channel region and described floating boom open area form, the p-n junction diode forming by described floating boom open area between described floating boom and drain region;
Cover the second layer insulation film that described floating boom and described p-n junction diode form;
On described second layer insulation film, cover and surround the control gate that described floating boom forms;
With electric conducting material, form for the contact in source region that described source region, control gate, drain region, Semiconductor substrate are connected with outer electrode, the contact in the contact of control gate, drain region and the contact of Semiconductor substrate.
The semiconductor device of U-shaped raceway groove as above, described ground floor insulation film, second layer insulation film are formed by the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k, and its physical thickness range is 1-20 nanometer.
The semiconductor device of U-shaped raceway groove as above, described floating boom is formed by polysilicon, and described control gate is formed by the polysilicon of metal, alloy or doping.
The semiconductor device of U-shaped raceway groove as above, described the first doping type is N-shaped, described the second doping type is p-type; Or described the first doping type is p-type, described the second doping type is N-shaped.
The semiconductor device of U-shaped raceway groove as above, described p-n junction diode, second layer insulation film and control gate have formed one and have usingd the gate control diode of described control gate as grid, the anode of described gate control diode is connected with described floating boom, and the negative electrode of described gate control diode is connected with described drain region; Or the negative electrode of described gate control diode is connected with described floating boom, the anode of described gate control diode is connected with described drain region.
Further, the invention allows for the manufacture method of the semiconductor device of above-mentioned U-shaped raceway groove, comprising:
In the Semiconductor substrate with the first doping type, form the light doping section with the second doping type;
At described semiconductor substrate surface deposit one hard mask layer and define the position of the U-shaped channel region of device by photoetching process and etching technics;
The Semiconductor substrate that the described hard mask layer of take exposes as mask etching, forms and is recessed in the U-shaped groove in Semiconductor substrate;
Etch away remaining hard mask layer;
On the exposed surface of Semiconductor substrate, form the formed ground floor insulation film of ground floor insulation film etching and form floating boom open area;
Then, deposit ground floor conductive film on the exposed surface of formed structure, this conductive film is the polysilicon with the first doping type;
The floating boom that forms device by photoetching process and the formed ground floor conductive film of etching technics etching, wherein, floating boom at least covers formed U-shaped groove and floating boom open area;
Then, on the exposed surface that forms structure, deposit forms second layer insulation film;
On described second layer insulation film, deposit forms second layer conductive film, then by photoetching process and the formed second layer conductive film of etching technics etching to form the control gate of device, wherein, control gate surpasses floating boom in the length along on channel direction, covers and surround floating boom;
Carry out the Implantation of the second doping type, control gate and the Semiconductor substrate that do not covered by control gate are adulterated to form to the doped structure of source region, drain region and the control gate of device;
The contact in source region that is formed for described source region, control gate, drain region, Semiconductor substrate to be connected with outer electrode with electric conducting material is, the contact in the contact of control gate, drain region and the contact of Semiconductor substrate.
The manufacture method of the semiconductor device of U-shaped raceway groove as above, described the first doping type is N-shaped, described the second doping type is p-type; Or described the first doping type is p-type, described the second doping type is N-shaped.
The manufacture method of the semiconductor device of U-shaped raceway groove as above, described ground floor insulation film, second layer insulation film be silicon dioxide, silicon nitride, silicon oxynitride or be the insulating material of high-k, its physical thickness range is 1-20 nanometer.
The manufacture method of the semiconductor device of U-shaped raceway groove as above, described second layer conductive film is metal, alloy or the polysilicon for adulterating.
The semiconductor device by using floating boom storage information of U-shaped raceway groove proposed by the invention, and carry out charge or discharge by grid-control p-n junction diode pair floating boom, have that cellar area is little, chip density is high, an advantage such as operating voltage is low when data are stored, data holding ability is strong.
Accompanying drawing explanation
Fig. 1 be prior art a kind of profile of semiconductor memory of planar channeling.
Fig. 2 is the profile of first embodiment of the semiconductor device of U-shaped raceway groove proposed by the invention.
Fig. 3 is the profile of second embodiment of the semiconductor device of U-shaped raceway groove proposed by the invention.
Fig. 4 is the profile of the 3rd embodiment of the semiconductor device of U-shaped raceway groove proposed by the invention.
Fig. 5 is the equivalent circuit diagram of the semiconductor device of U-shaped raceway groove proposed by the invention.
Fig. 6 to Figure 13 is the process chart of an embodiment of manufacture method of the semiconductor device of the U-shaped raceway groove that proposes of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation.In the drawings, for convenience of description, amplified the thickness in layer and region, shown in size do not represent actual size.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in region shown in figure, but comprises resulting shape, the deviation causing such as manufacture.The curve that for example etching obtains has crooked or mellow and full feature conventionally, but in embodiments of the present invention, all with rectangle, represents, the expression in figure is schematically, but this should not be considered to limit the scope of the invention.
Fig. 2, Fig. 3 and Fig. 4 are three embodiment of the semiconductor device of U-shaped raceway groove proposed by the invention, and they are the profiles along device channel length direction.As shown in Figure 2, Figure 3 and Figure 4, the semiconductor device of U-shaped raceway groove proposed by the invention comprises a Semiconductor substrate 200 with the first doping type and in the 201He drain region, source region 202 with the second doping type of Semiconductor substrate 200 interior formation.Semiconductor substrate 200 can or be the silicon on insulator for monocrystalline silicon, polysilicon.Described the first doping type is N-shaped, and described the second doping type is p-type, or described the first doping type is p-type, and described the second doping type is N-shaped.
Be recessed in Semiconductor substrate 200 and the U-shaped groove forming between 201He drain region, source region 202, in Semiconductor substrate, the surface of U-shaped groove is formed with the U-shaped channel region 401 of device, and U-shaped channel region 401 is the semiconductor device of this U-shaped raceway groove inversion layers in Semiconductor substrate 200 interior formation when carrying out work.
On 201He drain region, source region 202 and cover whole U-shaped channel region 401 and be formed with ground floor insulation film 203, at the ground floor insulation film 203 being arranged on drain region 202, be formed with a floating boom open area 204.Floating boom open area 204 can be formed at the ground floor insulation film 203 being arranged on 202 surfaces, drain region, structure as shown in Figures 2 and 3, also can be formed at and be positioned on 202 sides, drain region, be arranged in the ground floor insulation film 203 in U-shaped recess sidewall, structure as shown in Figure 4.
On ground floor insulation film 203 and cover whole U-shaped channel region 401 and floating boom open area 204 is formed with one as the floating boom with the first doping type 205 of charge-storage node.Ground floor insulation film 203 can or be the insulating material of the high-ks such as hafnium oxide for silicon dioxide, silicon nitride, silicon oxynitride, and its physical thickness range is preferably 1-20 nanometer.Floating boom 205 has the doping type contrary with drain region 202, and the impurity in floating boom 205 can be diffused in drain region 202 and be formed and have the diffusion region 402 of the first doping type by floating boom open area 204, thereby by floating boom open area 204, between floating boom 205 and drain region 202, forms a p-n junction diode.
Cover floating boom 205 and described p-n junction diode structure and be formed with second layer insulation film 206, second layer insulation film 206 can or be the insulating material of the high-ks such as hafnium oxide for silicon dioxide, silicon nitride, silicon oxynitride, and its physical thickness range is preferably 1-20 nanometer.On second layer insulation film 206 and cover and surround the control gate 207 that floating boom 205 is formed with device, control gate 207 can be metal, alloy or be the polysilicon of doping.
Control gate 207 can surround floating boom in the both sides of floating boom 205 simultaneously, to improve control gate coupling efficiency, structure as shown in Figure 2 and Figure 4.Control gate 207 also can only surround floating boom 205, structure as shown in Figure 3 at floating boom 205 near a side in drain region.
In the both sides of control gate 207, be also formed with the grid curb wall 208 of device, grid curb wall 208 can be silicon dioxide or silicon nitride, and grid curb wall is the known structure of industry, for other conductive layer isolation with device by control gate 207.
In 201He drain region, source region 202, be also formed with respectively the 209He doped region, doped region 210 with 201He drain region, source region 202 identical doping types, the doping content of 209He doped region, doped region 210 is apparently higher than the doping content in 201He drain region, source region 202, for reducing the ohmic contact of device.
The semiconductor device of U-shaped raceway groove of the present invention also comprise by electric conducting material, formed for the contact 211 in source region that described source region, control gate, drain region, Semiconductor substrate are connected with outer electrode, the contact 213 in the contact 212 of control gate, drain region and the contact 214 of Semiconductor substrate.
For describing in further detail the 26S Proteasome Structure and Function of the semiconductor device of U-shaped raceway groove disclosed in this invention, Fig. 5 has shown the equivalent circuit diagram of the semiconductor device of U-shaped raceway groove of the present invention.As shown in Figure 5, the semiconductor device of U-shaped raceway groove of the present invention comprises a MOSFET336 with source electrode 332, drain electrode 330, floating boom 333 and control gate 331 and one and take the gate control diode 335 that the control gate 331 of MOSFET336 is grid.The floating boom 333 of MOSFET336 can be connected with the anode of gate control diode 335, also can be connected with the negative electrode of gate control diode 335, and in the embodiment shown in Fig. 5 of the present invention, floating boom 333 is connected with the anode of gate control diode 335.By control gate 331, drain electrode 330 and source electrode 331 are applied to suitable voltage, gate control diode 335 can carry out charge or discharge to floating boom 333 and change with this amount of charge being stored in floating boom 333, and this amount of charge has determined the logic state of the semiconductor device of this U-shaped raceway groove.
The semiconductor device of U-shaped raceway groove disclosed in this invention can be manufactured by a lot of methods, and below what narrate is the manufacture technological process of an embodiment of the semiconductor device of the U-shaped raceway groove with N-shaped raceway groove of structure as shown in Figure 3 proposed by the invention.
First, as shown in Figure 6, in the Semiconductor substrate with the first doping type 200 providing, by shallow trench isolation, from (STI) operation, be formed with source region (not shown), this STI technique is that industry is known.Then by ion implantation technology, in the interior formation of Semiconductor substrate 200, there is the light doping section 300 of the second doping type.Semiconductor substrate 200 can or be the silicon on insulator for monocrystalline silicon, polysilicon.Described the first doping type is p-type, and described the second doping type is N-shaped.
Next, at surface deposition one deck hard mask layer 301 of Semiconductor substrate 200, hard mask layer 301 is such as being silicon nitride.Then on hard mask layer 301, deposit one deck photoresist 302 mask, exposure, development define the position of the U-shaped channel region of device, then etch away the hard mask layer 301 of exposure, and take the Semiconductor substrate 200 that method etching that hard mask layer 301 combines by wet etching and dry etching as mask exposes, thereby form the U-shaped groove that is recessed in Semiconductor substrate 200, this U-shaped groove is isolated into two parts by the light doping section 300 with the second doping type, respectively as the 201He drain region, source region 202 of device, as shown in Figure 7.
Next, divest photoresist 303 and continue and etch away remaining hard mask layer 301, follow growth regulation one deck insulation film 203 on the exposed surface of Semiconductor substrate 200, ground floor insulation film 203 can or be the insulating material of the high-ks such as hafnium oxide for silica, silicon nitride, silicon oxynitride, and its physical thickness is preferably 1-20 nanometer.Then deposit one deck photoresist define the position of floating boom open area by photoetching process on ground floor insulation film 203, then the ground floor insulation film 203 that the photoresist of take falls to expose as mask etching, thereby at the ground floor insulation film 203 being arranged on drain region 202, form a floating boom open area 204, then divest photoresist.By controlling the figure on lithography mask version, floating boom open area 204 can be formed at the ground floor insulation film 203 being arranged on 202 surfaces, drain region, structure as shown in Figure 8 a, also can be formed at and be positioned on 202 sides, drain region, be arranged in the ground floor insulation film 203 in U-shaped recess sidewall, structure as shown in Figure 8 b.
After the floating boom open area 204 forming as shown in Figure 8 b, by forming the structure of U-shaped channel semiconductor devices as shown in Figure 4 with described identical processing step below, the structure in each technical process while preparing this structure is not described in detail in the present embodiment
Next, on the exposed surface that forms structure, deposit one deck has the ground floor conductive film of the first doping type, and this conductive film is the polysilicon with p-type doping type.Then deposit one deck photoresist define the position of floating boom by photoetching process on formed ground floor conductive film, then the ground floor conductive film that the photoresist of take falls to expose as mask etching, after etching, remaining ground floor conductive film forms the floating boom 205 of device.Floating boom 205 at least covers whole U-shaped groove and floating boom open area 204.Impurity in floating boom 205 can diffuse to by the floating boom open area 204 under floating boom 205 and in drain region 202, form p-type diffusion region 402, and the p-n junction diode forming between floating boom 205 and drain region 202 by floating boom open area 204.Then continue to etch away the ground floor insulation film 203 exposing, divest after photoresist as shown in Figure 9.
Next, on the exposed surface that forms structure, deposit forms second layer insulation film 206, second layer insulation film 206 can or be the insulating material of the high-ks such as hafnium oxide for silica, silicon nitride, silicon oxynitride, and its physical thickness is preferably 1-20 nanometer.Then on second layer insulation film 206, deposit forms second layer conductive film 207, and second layer conductive film 207 can be metal, alloy or the polysilicon for adulterating.Then deposit one deck photoresist define the position of the control gate of device by photoetching process on second layer conductive film 207, then the second layer conductive film that the photoresist of take falls to expose as mask etching, after etching, remaining second layer conductive film forms the control gate 207 of device, control gate 207 should surpass floating boom 205 in the length along on channel direction, cover also and surround floating boom 205 in the both sides of floating boom 205, divest after photoresist as shown in Figure 10 a.
By controlling the figure on lithography mask version, when second layer insulation film 206 is carried out to etching, also can etch away the second layer conductive film 206 near source region 201 1 sides at floating boom 205, and be only retained in floating boom 205 near the second layer conductive film 206 of drain region 202 1 sides, thereby form, only at floating boom 205, near a side in drain region, surround the control gate 207 of floating boom 205, as shown in Figure 10 b, then by forming the structure of U-shaped channel semiconductor devices as shown in Figure 2 with described identical processing step below, structure in each technical process while preparing this structure is not described in detail in the present embodiment.
Next, on the exposed surface that forms structure, deposit forms three-layer insulated film, then deposit one deck photoresist form figure by photoetching process on formed three-layer insulated film, then etch away the three-layer insulated film exposing, and continue to etch away the second layer insulation film 206 exposing, after etching, remaining three-layer insulated film forms grid curb wall 208 in the both sides of control gate 207, and this technique is that industry is known, divests after photoresist as shown in figure 10.Grid curb wall 208 can be silica or silicon nitride.
Next, the foreign ion that carries out the second doping type (N-shaped) injects, control gate 207 and the Semiconductor substrate 200 that do not covered by control gate 207 are adulterated, the doped structure of formation control grid 207, and in 201He drain region, source region 202, form respectively the 209He doped region, doped region 210 of high concentration, as shown in figure 12.
Finally, with electric conducting material, be formed for the contact 211 in source region that source region 201, control gate 207, drain region 202, Semiconductor substrate 200 are connected with outer electrode, the contact 213 in the contact 212 of control gate, drain region and the contact 214 of Semiconductor substrate, as shown in figure 13.
As mentioned above, in the situation that not departing from spirit and scope of the invention, can also form many embodiment that have very big difference.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in specification.
Claims (9)
1. a semiconductor device for U-shaped raceway groove, comprising:
A Semiconductor substrate with the first doping type;
The source region with the second doping type and the drain region that in described Semiconductor substrate, form;
It is characterized in that, also comprise:
Be recessed in described Semiconductor substrate and the U-shaped channel region forming between described source region and drain region;
On described source region and drain region and cover the ground floor insulation film that whole U-shaped channel region forms;
The floating boom open area forming at the ground floor insulation film being arranged on described drain region, described open area can be on the level semiconductor surface in drain region or on the madial wall of described U-shaped groove top;
On described ground floor insulation film, cover the floating boom with the first doping type as charge-storage node that described U-shaped channel region and described floating boom open area form, the p-n junction diode forming by described floating boom open area between described floating boom and drain region;
Cover the second layer insulation film that described floating boom and described p-n junction diode form;
On described second layer insulation film, cover and surround the control gate that described floating boom forms;
With electric conducting material, form for the contact in source region that described source region, control gate, drain region, Semiconductor substrate are connected with outer electrode, the contact in the contact of control gate, drain region and the contact of Semiconductor substrate.
2. the semiconductor device of U-shaped raceway groove according to claim 1, it is characterized in that, described ground floor insulation film, second layer insulation film are formed by the insulating material of silicon dioxide, silicon nitride, silicon oxynitride or high-k, and its physical thickness range is 1-20 nanometer.
3. the semiconductor device of U-shaped raceway groove according to claim 1, is characterized in that, described floating boom is formed by polysilicon, and described control gate is formed by the polysilicon of metal, alloy or doping.
4. the semiconductor device of U-shaped raceway groove according to claim 1, is characterized in that, described the first doping type is N-shaped, and described the second doping type is p-type; Or described the first doping type is p-type, described the second doping type is N-shaped.
5. the semiconductor device of U-shaped raceway groove according to claim 1, it is characterized in that, described p-n junction diode, second layer insulation film and control gate have formed one and have usingd the gate control diode of described control gate as grid, the anode of described gate control diode is connected with described floating boom, and the negative electrode of described gate control diode is connected with described drain region; Or the negative electrode of described gate control diode is connected with described floating boom, the anode of described gate control diode is connected with described drain region.
6. the manufacture method of the semiconductor device of U-shaped raceway groove as claimed in claim 1, is characterized in that, comprising:
In the Semiconductor substrate with the first doping type, form the light doping section with the second doping type;
At described semiconductor substrate surface deposit one hard mask layer and define the position of the U-shaped channel region of device by photoetching process and etching technics;
The Semiconductor substrate that the described hard mask layer of take exposes as mask etching, forms and is recessed in the U-shaped groove in Semiconductor substrate;
Etch away remaining hard mask layer;
On the exposed surface of Semiconductor substrate, form the formed ground floor insulation film of ground floor insulation film etching and form floating boom open area;
Then, deposit ground floor conductive film on the exposed surface of formed structure, this conductive film is the polysilicon with the first doping type;
The floating boom that forms device by photoetching process and the formed ground floor conductive film of etching technics etching, wherein, floating boom at least covers formed U-shaped groove and floating boom open area;
Then, on the exposed surface that forms structure, deposit forms second layer insulation film;
On described second layer insulation film, deposit forms second layer conductive film, then by photoetching process and the formed second layer conductive film of etching technics etching to form the control gate of device, wherein, control gate surpasses floating boom in the length along on channel direction, covers and surround floating boom;
Carry out the Implantation of the second doping type, control gate and the Semiconductor substrate that do not covered by control gate are adulterated to form to the doped structure of source region, drain region and the control gate of device;
The contact in source region that is formed for described source region, control gate, drain region, Semiconductor substrate to be connected with outer electrode with electric conducting material is, the contact in the contact of control gate, drain region and the contact of Semiconductor substrate.
7. the manufacture method of the semiconductor device of U-shaped raceway groove according to claim 6, is characterized in that, described the first doping type is N-shaped, and described the second doping type is p-type; Or described the first doping type is p-type, described the second doping type is N-shaped.
8. the manufacture method of the semiconductor device of U-shaped raceway groove according to claim 6, it is characterized in that, described ground floor insulation film, second layer insulation film be silicon dioxide, silicon nitride, silicon oxynitride or be the insulating material of high-k, and its physical thickness range is 1-20 nanometer.
9. the manufacture method of the semiconductor device of U-shaped raceway groove according to claim 6, is characterized in that, described second layer conductive film is metal, alloy or the polysilicon for adulterating.
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| CN201310111150.5A CN104103678A (en) | 2013-04-02 | 2013-04-02 | U-shaped trench type semiconductor device and manufacture method thereof |
| PCT/CN2014/074529 WO2014161471A1 (en) | 2013-04-02 | 2014-04-01 | Semiconductor device having u-shaped channel |
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| CN201310111150.5A CN104103678A (en) | 2013-04-02 | 2013-04-02 | U-shaped trench type semiconductor device and manufacture method thereof |
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