CN110993600B - ESD protection structure, manufacturing method of ESD protection structure and display device - Google Patents
ESD protection structure, manufacturing method of ESD protection structure and display device Download PDFInfo
- Publication number
- CN110993600B CN110993600B CN201911298835.9A CN201911298835A CN110993600B CN 110993600 B CN110993600 B CN 110993600B CN 201911298835 A CN201911298835 A CN 201911298835A CN 110993600 B CN110993600 B CN 110993600B
- Authority
- CN
- China
- Prior art keywords
- transistor
- layer
- conductive
- semiconductor layer
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 181
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 abstract description 18
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 20
- 239000010409 thin film Substances 0.000 description 16
- 239000010408 film Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 239000011810 insulating material Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000007667 floating Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- -1 polyethylene naphthalate Polymers 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- DTBNBXWJWCWCIK-UHFFFAOYSA-N Phosphoenolpyruvic acid Natural products OC(=O)C(=C)OP(O)(O)=O DTBNBXWJWCWCIK-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 2
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 239000002096 quantum dot Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000008204 material by function Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an ESD protection structure, a manufacturing method of the ESD protection structure and a display device. The ESD protection structure is connected with a circuit to be protected and a peripheral circuit of the display, wherein a substrate, a first semiconductor layer, a gate insulating layer and a conductive gate layer of the ESD protection structure are sequentially laminated; the first semiconductor layer comprises a source-drain electrode region and a channel region; the middle dielectric layer is arranged on one side of the conductive grid layer far away from the grid insulating layer; the second semiconductor layer sequentially penetrates through the intermediate dielectric layer and the gate insulating layer to be connected with the source drain region, so that a first diode and a second diode are formed; the first semiconductor layer, the gate insulating layer and the conductive gate layer form a first transistor and a second transistor, compared with the ESD protection structure of four transistors in the prior art, the structure has smaller volume, can play the role of electrostatic discharge protection, and is more beneficial to the design of a narrow-frame display.
Description
Technical Field
The present invention relates to the field of transistor technologies, and in particular, to an ESD protection structure, a method for manufacturing the ESD protection structure, and a display device.
Background
Electrostatic Discharge (ESD) is a potential hazard that affects the stability and long-term performance of displays and flat panel displays, and it has been counted that approximately five display and flat panel display failures are caused by ESD, which causes damage to the display and flat panel display and its components attempt to be prohibitive.
In the current flat panel display technology, a thin film transistor is widely used as a basis for active driving display, so that high-speed image conversion and higher-resolution display effects are obtained. In the electrostatic discharge protection structure, four thin film transistors are usually used to be connected to the protected circuit and the peripheral circuit of the display respectively, so that the charges of the protected circuit are discharged to the peripheral circuit of the display under the condition of electrostatic discharge, but the design requires a large space, so that the display screen is large in size, and the design of the narrow-frame display is not facilitated.
Disclosure of Invention
The invention mainly aims to provide an ESD protection structure, a manufacturing method of the ESD protection structure and a display device, and aims to solve the technical problem that the ESD protection structure in the prior art is large in size.
In order to achieve the above objective, the present invention provides an ESD protection structure, which is respectively connected to a line to be protected, a first level line and a second level line, wherein the ESD protection structure comprises a substrate, a first semiconductor layer, a gate insulating layer, a conductive gate layer, an intermediate dielectric layer, a second semiconductor layer, a source-drain conductive electrode layer and a passivation layer; wherein,
The substrate, the first semiconductor layer, the gate insulating layer and the conductive gate layer are sequentially stacked; the first semiconductor layer comprises a source-drain electrode region and a channel region; the intermediate dielectric layer is arranged on one side of the conductive gate layer far away from the gate insulating layer; the second semiconductor layer sequentially penetrates through the intermediate dielectric layer and the gate insulating layer to be connected with the source drain region, so that a first diode and a second diode are formed; the first semiconductor layer, the gate insulating layer, and the conductive gate layer form a first transistor and a second transistor.
Preferably, the source-drain conductive electrode layer comprises a first conductive electrode, a second conductive electrode, a third conductive electrode and a fourth conductive electrode; the first end of the first conductive electrode is connected with the first level line, the first end of the third conductive electrode is connected with the line to be protected, and the first end of the fourth conductive electrode is connected with the second level line.
Preferably, the first semiconductor layer is made of polysilicon material.
Preferably, the second end of the first conductive electrode is connected with the first source-drain electrode of the first transistor, two ends of the second conductive electrode are respectively connected with the gate electrode of the first transistor and the second source-drain electrode of the first transistor, the second end of the third conductive electrode is connected with the first diode, the third end of the third conductive electrode is connected with the first source-drain electrode of the second transistor, the third end of the third conductive electrode is also overlapped with the gate electrode of the second transistor, and the second end of the fourth conductive electrode is connected with the second diode.
Preferably, the conductive properties of the first semiconductor layer are opposite to the conductive properties of the second semiconductor layer.
Preferably, the source-drain conductive electrode layer further includes a fifth conductive electrode, a second end of the first conductive electrode is connected to a first source drain of the first transistor, two ends of the second conductive electrode are respectively connected to a gate of the first transistor and a second source drain of the first transistor, a second end of the third conductive electrode is connected to the first diode, a third end of the third conductive electrode is connected to the second diode, a first end of the fifth conductive electrode is connected to a first source drain of the second transistor, a second end of the fifth conductive electrode is connected to a gate of the second transistor, and a second end of the fourth conductive electrode is connected to a second source drain of the second transistor.
Preferably, the first semiconductor layer in the first transistor has a conductivity opposite to that of the second semiconductor layer in the first diode, and the first semiconductor layer in the second transistor has a conductivity opposite to that of the second semiconductor layer in the second diode.
The invention also provides a manufacturing method of the ESD protection structure, which comprises the following steps:
forming a patterned first semiconductor layer on a substrate;
forming a gate insulating layer and a patterned conductive gate layer on the first semiconductor layer;
performing first ion doping on the source-drain electrode region of the first semiconductor;
forming an intermediate dielectric layer on the conductive gate layer and forming two patterned first via structures;
forming a second semiconductor layer in the first via structure, and performing second ion doping on the second semiconductor layer;
forming a plurality of patterned second via structures in the intermediate dielectric layer and the gate insulating layer;
forming a patterned source-drain conductive electrode layer on the second semiconductor layer and in the second via structure;
and forming a passivation layer on the source-drain conductive electrode.
Preferably, the step of forming the patterned first semiconductor layer on the substrate employs a low temperature polysilicon process.
The invention also provides a display device which comprises the ESD protection structure, or the display device is manufactured by applying the manufacturing method of the ESD protection structure.
The ESD protection structure is connected with a circuit to be protected and a peripheral circuit of the display, wherein a substrate, a first semiconductor layer, a gate insulating layer and a conductive gate layer of the ESD protection structure are sequentially laminated; the first semiconductor layer comprises a source-drain electrode region and a channel region; the middle dielectric layer is arranged on one side of the conductive grid layer far away from the grid insulating layer; the second semiconductor layer sequentially penetrates through the intermediate dielectric layer and the gate insulating layer to be connected with the source drain region, so that a first diode and a second diode are formed; the first semiconductor layer, the gate insulating layer and the conductive gate layer form a first transistor and a second transistor, compared with the ESD protection structure of four transistors in the prior art, the structure has smaller volume, can play the role of electrostatic discharge protection, and is more beneficial to the design of a narrow-frame display.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of a first embodiment of an ESD protection structure according to the present invention;
FIG. 2 is a schematic circuit diagram of a first embodiment of an ESD protection structure of the present invention;
FIG. 3 is a flow chart illustrating a first embodiment of an ESD protection structure of the present invention;
fig. 4 is a schematic structural view of a second embodiment of an ESD protection structure according to the present invention;
FIG. 5 is a schematic circuit diagram illustrating a second embodiment of an ESD protection structure of the present invention;
FIG. 6 is a flow chart illustrating a second embodiment of an ESD protection structure of the present invention;
fig. 7 is a schematic structural view of a third embodiment of an ESD protection structure according to the present invention;
FIG. 8 is a schematic circuit diagram of a third embodiment of an ESD protection structure of the present invention;
FIG. 9 is a flow chart illustrating a third embodiment of an ESD protection structure of the present invention;
fig. 10 is a schematic structural view of a fourth embodiment of an ESD protection structure according to the present invention;
FIG. 11 is a schematic circuit diagram of a fourth embodiment of an ESD protection structure of the present invention;
fig. 12 is a flow chart illustrating a fourth embodiment of an ESD protection structure according to the present invention.
Reference numerals illustrate:
| reference numerals | Name of the name | Reference numerals | Name of the name |
| 110 | Substrate and method for manufacturing the same | 120a | First source drain electrode of first transistor |
| 120 | First semiconductor layer | 120b | Channel of first transistor |
| 130 | Gate insulating layer | 120c | Second source drain electrode of first transistor |
| 140 | Conductive gate layer | 120d | First source drain electrode of second transistor |
| 150 | Intermediate dielectric layer | 120e | Channel of second transistor |
| 160 | Second semiconductor layer | 120f | Second source/drain of second transistor |
| 170 | Source drain conductive electrode layer | 140a | The grid electrode of the first transistor |
| 180 | Passivation layer | 140b | Grid electrode of second transistor |
| T1 | First transistor | 160a | Second semiconductor layer of first diode |
| T2 | Second transistor | 160b | Second semiconductor layer of second diode |
| D1 | First diode | 170a | First conductive electrode |
| D2 | Second diode | 170b | Second conductive electrode |
| Vin | Line voltage to be protected | 170c | Third conductive electrode |
| Vss | Continuous low level line voltage | 170d | Fourth conductive electrode |
| Vdd | Continuous high level line voltage |
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The invention provides an ESD protection structure which is respectively connected with a circuit to be protected, a first level circuit and a second level circuit to realize the electrostatic discharge protection of the circuit to be protected.
Referring to fig. 1, fig. 2, fig. 7 and fig. 8, the ESD protection structure includes a substrate 110, a first semiconductor layer 120, a gate insulating layer 130, a conductive gate layer 140, an intermediate dielectric layer 150, a second semiconductor layer 160, a source/drain conductive electrode layer 170 and a passivation layer 180; wherein the substrate 110, the first semiconductor layer 120, the gate insulating layer 130, and the conductive gate layer 140 are sequentially stacked; the first semiconductor layer 120 includes a source/drain region and a channel region; the middle dielectric layer 150 is disposed on a side of the conductive gate layer 140 away from the gate insulating layer 130; the second semiconductor layer 160 sequentially passes through the intermediate dielectric layer 150 and the gate insulating layer 130 to be connected with the source/drain region, so as to form a first diode D1 and a second diode D2; the first semiconductor layer 120, the gate insulating layer 130, and the conductive gate layer 140 form a first transistor T1 and a second transistor T2.
Further, a plurality of via structures may be disposed in the middle dielectric layer 150 and the gate insulating layer 130, each via structure is disposed in the second semiconductor layer 160 or the source-drain conductive electrode layer 170 correspondingly, and the source-drain conductive electrode layer 170 is further disposed on the upper portion of the via structure; the source-drain conductive electrode layer 170 is electrically connected with the source-drain region through the via structure; the passivation layer 180 covers the upper portion of the source/drain conductive electrode layer 170; the second semiconductor layer 160 is connected to the source/drain region through the via structure to form a first diode D1 and a second diode D2.
In this embodiment, the first semiconductor layer 120, the gate insulating layer 130, and the conductive gate layer 140 may be formed in various manners when forming the first transistor T1 and the second transistor T2, wherein the first transistor T1 is formed by the first source/drain 120a, the channel 120b, the second source/drain 120c, the gate 140a, and the gate insulating layer 130, and the second transistor T2 is formed by the first source/drain 120d, the channel 120e, the second source/drain 120f, the gate 140b, and the gate insulating layer 130. The first source/drain and the second source/drain may be set according to actual needs, for example, set 120a and 120f as sources, set 120c and 120d as drains, set 120a and 120f as drains, set 120c and 120d as sources, or other setting manners, which is not limited in this embodiment.
It should be understood that the substrate 110 is used to carry a thin film transistor (Thin Film Transistor, TFT), an Organic Light-Emitting Diode (OLED), a quantum dot Light-Emitting Diode (Quantum Dot Light Emitting Diodes, QLED), or a liquid crystal component, and may be a rigid substrate or a flexible substrate. The rigid substrate may be made of ceramics, various glass materials, etc., and the flexible substrate may be made of PI (polyimide film) and derivatives thereof, PEN (polyethylene naphthalate), PEP (phosphoenolpyruvic acid), diphenylene ether resin, etc., which is not limited in this embodiment.
The first semiconductor layer 120 is a semiconductor thin film material, and may be amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, molybdenum sulfide semiconductor, or the like. In general, if a voltage is applied to the source/drain portion of the semiconductor, no current flows in the semiconductor, and only a very small leakage current is generated; when the voltage drop of the grid electrode relative to the source electrode and the drain electrode part reaches a threshold voltage (Vth), the resistivity of the semiconductor is reduced under the influence of the grid electrode, so that the current quantity change of more than 10-4, namely the source electrode and the drain electrode are conducted, and the function of controlling whether the source electrode and the drain electrode are conducted or not through the grid electrode is achieved.
The first semiconductor layer 120 in this embodiment is preferably made of a polysilicon material, because the polysilicon material has higher mobility, and the semiconductor characteristics thereof are better controllable than those of amorphous silicon and oxide semiconductor materials, and the semiconductor characteristics can be controlled by ion doping, metal-induced doping, and the like.
The first semiconductor layer 120 is divided into 2 major parts, which are semiconductor parts belonging to 2 transistors in the general sense, respectively. Each major portion is divided into 3 minor portions 120a, 120b, 120c and 120d, 120e, 120f, respectively. 120a, 120b is a channel of the first transistor T1, 120c is a second source-drain of the first transistor T1, 120d is a first source-drain of the second transistor T2, 120e is a channel of the second transistor T2, and 120f is a second source-drain of the second transistor T2. The first source drain 120a of the first transistor T1 and the second source drain 120c of the first transistor T1 are materials of the semiconductor after being subjected to the semiconducting process, and the first source drain 120d of the second transistor T2 and the second source drain 120f of the second transistor T2 are materials of the semiconductor after being subjected to the conducting process, which are also referred to as source drain regions in the first semiconductor layer 120; the channel 120b of the first transistor T1 and the channel 120e of the second transistor T2 are channel regions in the first semiconductor layer 120. The source and the drain of the first transistor T1 and the source and the drain of the second transistor T2 may be switched according to practical situations.
The gate insulating layer 130 is typically an insulating material covering a substantial portion of the first semiconductor layer 120. On the one hand, it serves to isolate the first semiconductor layer 120 and the conductive gate layer 140 so that they can only interact by electric field induction; on the other hand, its thickness, film properties, etc. have a very large influence on the electrical properties of the thin film transistor, such as mobility, leakage current, threshold voltage, etc. of the thin film transistor. The gate insulating layer 130 may be an organic insulating material or an inorganic insulating material, wherein the inorganic insulating material may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, or the like, which is not limited in this embodiment.
The conductive gate layer 140 is a conductive material, and when a threshold voltage (Vth) is applied to the conductive gate 140, the first semiconductor layer 120 changes its conductive property due to the threshold voltage, and functions to control the current of the first semiconductor layer 120. The conductive gate 140 is divided into 2 parts, and belongs to the gate parts of 2 transistors respectively, wherein 140a is the gate of the first transistor T1, and 140b is the gate of the second transistor T2. The conductive gate layer 140 may be an inorganic material, an organic material, a nanowire, etc., wherein the inorganic material may be a conductive metal such as aluminum, molybdenum, titanium, copper, silver, gold, etc., an alloy thereof, or a combination stack thereof, which is not limited in this embodiment. Note that the conductive gate layer 140 covers the upper portion of the channel regions (120 b and 120 e), and a gate insulating layer 130 is provided between the conductive gate layer 140 and the channel regions.
The intermediate dielectric layer 150 is an insulating material, and is used for isolating the conductive gate 140 from electrical connection with other conductive electrodes thereon; the material of the intermediate dielectric layer 150 may be an organic insulating material or an inorganic insulating material, wherein the inorganic insulating material may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, a combination stack thereof, or the like. In this embodiment, the intermediate dielectric layer 150 is preferably a combination stack of silicon nitride and silicon oxide, because the silicon nitride film is easy to prepare and has a high dielectric constant.
The via structure is a hole structure with a certain depth dug by an insulating layer (such as the middle dielectric layer 150 and the gate insulating layer 130) at a place where the upper electrode and the lower electrode are required to be connected by using a semiconductor photoetching process, and then conductive or functional materials are filled in the hole structure to realize the functions of conducting the upper electrode and the lower electrode and realizing other functions.
The second semiconductor layer 160 is a semiconductor material, and may be amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, molybdenum sulfide semiconductor, or the like. The second semiconductor layer 160 is divided into 2 most parts, and belongs to 2 diodes respectively, wherein 160a is the second semiconductor layer of the first diode D1, and 160b is the second semiconductor layer of the second diode D2.
In the present embodiment, in the single combined device (the first transistor T1 and the first diode D1 or the second transistor T2 and the second diode D2), the conductive characteristic of the second semiconductor layer 160 is opposite to the conductive characteristic of the first semiconductor layer 120. Thus, the second source/drain 120c of the first transistor T1 forms a PN junction with the second semiconductor layer 160a of the first diode D1, and the second source/drain 120f of the second transistor T2 forms a PN junction, i.e., a diode structure, with the second semiconductor layer 160b of the second diode D2. Depending on the structure and conductivity characteristics of the diode, macroscopic current can only flow from the P-type semiconductor side to the N-type semiconductor side, which is the unidirectional conductivity of the diode. Therefore, according to the conductive characteristics of the first and second semiconductor layers 120 and 160, the direction of the diode in the circuit of the ESD protection structure can be determined. Of course, the characteristic variation of the diode, such as the threshold voltage, the maximum forward average current, etc., of the diode can also be controlled by controlling the doping concentrations of 120c and 120d in the first semiconductor layer 120 and the doping concentration of the second semiconductor layer 160 in the present embodiment.
The source-drain conductive electrode layer 170 is a conductive material, and generally has functions of inputting data voltage and conducting peripheral current of the display screen, and is a thin film conductive layer with lower resistance and better conductive property, and its material may be conductive metals such as aluminum, molybdenum, titanium, copper, silver, gold, and the like, and alloys, combined stacks, and the like, which are not limited in this embodiment.
The passivation layer 180 is a thin film insulating material, and mainly plays a role in protecting the electrode material under the passivation layer 180 from external pollution, and its material may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, etc., which is not limited in this embodiment.
Further, the source-drain conductive electrode layer 170 includes a first conductive electrode 170a, a second conductive electrode 170b, a third conductive electrode 170c, and a fourth conductive electrode 170d; the first end of the first conductive electrode 170a is connected to a first level line, the first end of the third conductive electrode 170c is connected to a line to be protected, and the first end of the fourth conductive electrode 170d is connected to a second level line.
It should be noted that the first level line may be a low level line or a high level line of the peripheral circuit of the display, the second level line is a high level line or a low level line of the peripheral circuit of the display, and the line to be protected is a thin film line in the display screen that needs electrostatic protection. When the line to be protected generates an excessively strong positive current or negative current due to electrostatic discharge and changes the voltage drop at the third conductive electrode 170c, the excessively strong positive current or negative current can be discharged through the combined device of the first diode D1 and the first transistor T1 or the combined device of the second diode D2 and the second transistor T2 by the ESD protection structure in the present embodiment.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of an ESD protection structure according to the present invention.
In the first embodiment, the first semiconductor layer 120 is a P-type semiconductor, and the second semiconductor layer 160 is an N-type semiconductor.
Specifically, the second end of the first conductive electrode 170a is connected to the first source-drain electrode 120a of the first transistor T1, the two ends of the second conductive electrode 170b are respectively connected to the gate 140a of the first transistor T1 and the second source-drain electrode 120c of the first transistor T1, the second end of the third conductive electrode 170c is connected to the first diode D1, the third end of the third conductive electrode 170c is connected to the first source-drain electrode 120D of the second transistor T2, the third end of the third conductive electrode 170c also overlaps the gate 140b of the second transistor T2, and the second end of the fourth conductive electrode 170D is connected to the second diode D2.
It should be noted that, in this embodiment, since the third conductive electrode 170c has a certain overlapping area with the gate 140b of the second transistor T2, a capacitance structure of a floating gate is formed with a portion of the intermediate dielectric layer 150, and the floating gate is utilized to induce charges of the third conductive electrode 170c from the gate 140b of the second transistor T2, and the polarities are opposite. The second end of the fourth conductive electrode 170D is connected to an end of the second semiconductor 160b of the second diode D2 remote from the second source-drain electrode 120f of the second transistor T2.
Referring to fig. 2, fig. 2 is a schematic circuit connection diagram of an ESD protection structure according to a first embodiment of the invention.
The first conductive electrode 170a in this embodiment is connected to a continuous low level line in the peripheral circuitry of the display, typically in a low level state; the fourth conductive electrode 170d is connected to a continuous high level line in the peripheral circuitry of the display, typically in a high level state; the third conductive electrode 170c in this embodiment is used to connect the thin film circuit, i.e. the circuit to be protected, in the display screen that needs electrostatic protection.
The first transistor T1 is composed of a gate 140a of the first transistor T1, a first source drain 120a of the first transistor T1, a channel 120b of the first transistor T1, a second source drain 120c of the first transistor T1, and a gate insulating layer 130; the first diode D1 is composed of the second source/drain electrode 120c of the first transistor T1 and the second semiconductor layer 160a of the first diode D1; the second transistor T2 is composed of a gate 140b of the second transistor T2, a gate insulating layer 130, a first source drain 120d of the second transistor T2, a channel 120e of the second transistor T2, and a second source drain 120f of the second transistor T2; the second diode D2 is composed of the second semiconductor layer 160b of the second diode D2 and the second source-drain electrode 120f of the second transistor T2.
The working principle of the ESD protection structure in this embodiment is as follows:
when the line to be protected is in a current and voltage state where no electrostatic discharge (i.e. normal line) is generated, the line voltage Vin to be protected is generally smaller than the continuous high-level line voltage Vdd and larger than the continuous low-level line voltage Vss, and even if |vin| is larger than the threshold voltage of the first diode D1 or the second diode T2, the first transistor T1 or the second diode D2 is not turned on. For example, the line voltage Vin to be protected may be a gate voltage Vgate or a data voltage Vdata for driving the thin film transistor in the display panel, which are generally within ±3v, and the continuous low level line voltage Vss may be generally set to-8V and the continuous high level line voltage Vdd may be set to 4V. At this time, the circuit to be protected is normal and low in loss, and the ESD protection structure connected in parallel to the circuit to be protected does not influence the normal operation of the circuit to be protected.
When the circuit to be protected generates electrostatic discharge in the use process, if negative charge discharge occurs, the voltage Vin of the circuit to be protected is pulled to a very low level instantly, at this time, the N3 end of the first diode D1 belongs to floating point voltage, which is generally larger than the voltage Vin of the circuit to be protected at this time, and the first diode D1 is turned on. Meanwhile, because Vin < < Vss, the threshold voltage vth=vss-Vin < <0 of the first transistor T1, the source-drain of the first transistor T1 is turned on, and negative charge is discharged from the channel 120b of the first transistor T1 to the continuous low-level line, thereby playing a role of protection. Similarly, when the positive charge is discharged, the positive charge generated by the third conductive electrode 170c will induce the negative charge to the gate 140b of the second transistor T2, so that the second transistor T2 is turned on, and as Vin > Vdd, the second diode D2 is turned on, so that the positive charge is discharged to the continuous high-level line, and the line to be protected is protected.
Referring to fig. 3, fig. 3 is a flow chart illustrating a manufacturing process of an ESD protection structure according to a first embodiment of the invention.
In this embodiment, the method for manufacturing the ESD protection structure includes the following steps:
s1, forming a patterned first semiconductor layer on a substrate.
Referring to fig. 1 and fig. 3a together, a patterned first semiconductor layer 120 is formed on a substrate 110 and two large portions 120A and 120B are patterned. The first semiconductor layer 120 is preferably formed by a low temperature polysilicon process, which includes: the first step: plasma chemical vapor deposition of amorphous silicon film; and a second step of: forming a polysilicon film layer after excimer laser annealing; and a third step of: patterning using photolithography; fourth step: the polysilicon film layer is subjected to semiconductor characteristic adjustment by utilizing ion implantation doped with B (boron) and P (phosphorus) ions.
And S2, forming a gate insulating layer and a patterned conductive gate layer on the first semiconductor layer.
Referring to fig. 1 and fig. 3b, the gate insulating layer 130 and the conductive gate layer 140 are coated by chemical vapor deposition, magnetron sputtering, evaporation, and the like, and the conductive gate layer 140 is patterned by photolithography. The gate insulation layer 130 is preferably formed by a slow deposition process of the plasma chemical vapor deposition in this embodiment, and has a thickness of about 110 nm.
S3, performing first ion doping on the source electrode and the drain electrode of the first semiconductor.
Referring to fig. 1, 3B and 3c, the doping changes the film properties of some portions of the first semiconductor layer 120, and changes 120A and 120B to 6 portions 120A, 120B, 120c, 120d, 120e and 120f, respectively. The first ions are B ions, and the doping method can be ion implantation, namely the ions generated after gas ionization are accelerated and then scanned on the whole surface of the substrate, so that the ionized ions are driven into the film. If B ions are doped into a semiconductor film (such as a polysilicon film layer), and the concentration is high, the polysilicon film layer is conductive, and the resistivity is reduced greatly, so that ohmic contact is formed when the conductive semiconductor is contacted with metal, the contact resistance between the semiconductor and the metal is reduced, the energy consumption is reduced, and the on-state current of the thin film transistor is improved. At the same time, the doping of the B ions causes the semiconductor conductivity of this portion to behave as a P-type semiconductor, with holes mainly participating in the conductivity. If the implantation of ions encounters the metal film, the implantation cannot be continued, and thus the conductive gate layer 140 forms a mask so that ions can be implanted only into the regions 120a, 120c, 120d and 120f, thereby forming the channel region of the first semiconductor layer 120.
S4, forming an intermediate dielectric layer on the conductive grid layer and forming two patterned first via structures.
As shown in fig. 3c, the intermediate dielectric layer 150 is coated by chemical vapor deposition, magnetron sputtering, evaporation, etc., and 2 patterned first via structures, such as holes, are formed by photolithography, wherein the first via structures are disposed inside the intermediate dielectric layer 150, inside the gate insulating layer 130, and above the source/drain regions 120c and 120f, respectively.
S5, forming a second semiconductor layer in the first via structure, and carrying out second ion doping on the second semiconductor layer.
Referring to fig. 1 and 3d, the second semiconductor layer 160 is coated by chemical vapor deposition, magnetron sputtering, evaporation, and the like, and then patterned to form 160a and 160b, which are two portions of the second semiconductor, 160a and 160b are respectively connected with 120c and 120f, and form two PN junctions. In this embodiment, the second semiconductor layer 160 is an N-type semiconductor, in order to form a more reliable diode structure, an intermittent film-forming process using chemical vapor deposition is preferred in this embodiment, siH4, PH3 and H2 are used as main film-forming gas sources, 30% of the time is in normal film-forming during the whole film-forming process, 70% of the time is in H2 plasma surface treatment, and the film-forming material is denser by continuously performing film-forming and H2 plasma treatment, so that a microcrystalline structure can be generally formed, and the microcrystalline structure has better stability and better conductivity characteristics of the semiconductor. The material of the second semiconductor layer 160 in this embodiment is preferably a microcrystalline silicon film doped with phosphorus.
Further, it is a preferred embodiment of the present invention to etch the second semiconductor layer 160 not protected by the photoresist by using an isotropic etching method, so that the etching area can be controlled to be performed on the surface of the film, and finally the illustrated structure is formed. Wherein the height of the second semiconductor layer 160 within the via structure may be controlled by the etching time. Generally, the isotropic etching process includes wet etching, ECP plasma etching, and the like, which is not limited in this embodiment.
S6, forming a plurality of patterned second via structures in the intermediate dielectric layer and the gate insulating layer.
As shown in fig. 3e, a second patterning of the second via structure is formed in the middle dielectric layer 150, the gate insulating layer 130 using a semiconductor lithography technique, wherein the etching process uses a plasma physical etching method.
And S7, forming a patterned source-drain conductive electrode layer on the second semiconductor layer and in the second via hole structure.
Referring to fig. 1 and fig. 3f, the plating of the source/drain conductive electrode layer 170 is completed by chemical vapor deposition, magnetron sputtering, evaporation, and the like, and the patterning of the source/drain conductive electrode layer 170 is performed by photolithography to form four parts 170a, 170b, 170c, and 170 d.
S8, forming a passivation layer on the source-drain conductive electrode.
The ESD protection structure is connected with the circuit to be protected and the peripheral circuit of the display, wherein a substrate, a first semiconductor layer, a gate insulating layer and a conductive gate layer of the ESD protection structure are sequentially stacked; the first semiconductor layer comprises a source-drain electrode region and a channel region; the middle dielectric layer is arranged on one side of the conductive grid layer far away from the grid insulating layer; the second semiconductor layer sequentially penetrates through the intermediate dielectric layer and the gate insulating layer to be connected with the source drain region, so that a first diode and a second diode are formed; the first semiconductor layer, the gate insulating layer and the conductive gate layer form a first transistor and a second transistor, compared with the ESD protection structure of four transistors in the prior art, the structure has smaller volume, can play the role of electrostatic discharge protection, and is more beneficial to the design of a narrow-frame display.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a second embodiment of an ESD protection structure according to the present invention.
In the second embodiment, the first semiconductor layer 120 is an N-type semiconductor, and the second semiconductor layer 160 is a P-type semiconductor.
The ESD protection structure in this embodiment is the same as that in the first embodiment, and will not be described here again.
Referring to fig. 4 and fig. 5 together, fig. 5 is a schematic circuit connection diagram of an ESD protection structure according to a second embodiment of the invention.
The first conductive electrode 170a in this embodiment is connected to a continuous high level line in the peripheral circuit of the display; the fourth conductive electrode 170d is connected to a continuous low level line in the display peripheral circuitry; the third conductive electrode 170c is connected to the line to be protected.
The first transistor T1 is composed of a gate 140a of the first transistor T1, a first source drain 120a of the first transistor, a channel 120b of the first transistor T1, a second source drain 120c of the first transistor T1, and a gate insulating layer 130; the first diode D1 is composed of the second source-drain electrode 120c of the first transistor D1 and the second semiconductor layer 160a of the first diode D1; the second transistor T2 is composed of a gate 140b of the second transistor T2, a gate insulating layer 130, a first source drain 120d of the second transistor T2, a channel 120e of the second transistor T2, and a second source drain 120f of the second transistor T2; the second diode D2 is composed of the second semiconductor layer 160b of the second diode D2 and the second source drain 120f of the second transistor T2.
The working principle of the ESD protection structure in this embodiment is as follows:
when the line to be protected is in a current and voltage state where no electrostatic discharge (i.e. normal line) is generated, the line voltage Vin to be protected is generally smaller than the continuous high-level line voltage Vdd and larger than the continuous low-level line voltage Vss, and even if |vin| is larger than the threshold voltage of the first diode D1 or the second diode T2, the first transistor T1 or the second diode D2 is not turned on. For example, the line voltage Vin to be protected may be a gate voltage Vgate or a data voltage Vdata for driving the thin film transistor in the display panel, which are generally within ±3v, and the continuous low level line voltage Vss may be generally set to-8V and the continuous high level line voltage Vdd may be set to 4V. At this time, the circuit to be protected is normal and low in loss, and the ESD protection structure connected in parallel to the circuit to be protected does not influence the normal operation of the circuit to be protected.
When the circuit to be protected generates electrostatic discharge in the use process, if the circuit to be protected is positively charged discharge, the voltage Vin of the circuit to be protected can be instantaneously pulled to a very high level, at this time, the N3 end of the first diode D1 belongs to floating point voltage, and is usually smaller than the voltage Vin of the circuit to be protected at this time, and the first diode D1 is conducted. Meanwhile, because Vin > Vdd, the threshold voltage vth=vin-Vdd >0 of the first transistor T1, the source-drain of the first transistor T1 is turned on, and positive charges are discharged from the channel 120b of the first transistor T1 to the continuous high-level line, thereby playing a role of protection. Similarly, when the negative charge discharges, the negative charge generated by the third conductive electrode 170c will induce the positive charge to the gate 140b of the second transistor, so that the second transistor T2 is turned on, and as Vin < < Vss, the second diode D2 is turned on, so that the negative charge is discharged to the continuous high-level line, and the line to be protected is protected.
Referring to fig. 4, fig. 5 and fig. 6 together, fig. 6 is a flow chart illustrating a manufacturing process of an ESD protection structure according to a second embodiment of the invention.
In this embodiment, the manufacturing method of the ESD protection structure is different from that of the first embodiment only in that the first ion is a phosphorus ion in step S3 and the second ion is a boron ion in step S5.
In the embodiment, by changing the conductive characteristics of the first semiconductor layer and the second semiconductor layer in the ESD protection structure and connecting the first conductive electrode 170a in the ESD protection structure with the continuous high-level line in the peripheral circuit of the display, the fourth conductive electrode 170d is connected with the continuous low-level line in the peripheral circuit of the display, and the third conductive electrode 170c is connected with the line to be protected, the effect of discharging the charge of the protected line to the high-level or low-level line under the condition of generating electrostatic discharge is achieved, and the electrostatic discharge protection effect is achieved.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a third embodiment of an ESD protection structure according to the present invention.
In the third embodiment, the conductive characteristics of the first semiconductor layers (120 a and 120 c) in the first transistor T1 are opposite to those of the second semiconductor layer 160a in the first diode D1, and the conductive characteristics of the first semiconductor layers (120D and 120 f) in the second transistor T2 are opposite to those of the second semiconductor layer 160b in the second diode D2. Specifically, the first semiconductor layers (120 a and 120 c) in the first transistor T1 are P-type semiconductors, the first semiconductor layers (120D and 120 f) in the second transistor T2 are N-type semiconductors, the second semiconductor layer 160a in the first diode D1 is an N-type semiconductor, and the second semiconductor layer 160b in the second diode D2 is a P-type semiconductor.
In this embodiment, the source-drain conductive electrode layer 170 further includes a fifth conductive electrode 170e, the second end of the first conductive electrode 170a is connected to the first source-drain electrode 120a of the first transistor T1, two ends of the second conductive electrode 170b are respectively connected to the gate 140a of the first transistor T1 and the second source-drain electrode 120c of the first transistor T1, the second end of the third conductive electrode 170c is connected to the first diode D1, the third end of the third conductive electrode 170c is connected to the second diode D2, the first end of the fifth conductive electrode 170e is connected to the first source-drain electrode 120D of the second transistor T2, the second end of the fifth conductive electrode 170e is connected to the gate 140b of the second transistor T2, and the second end of the fourth conductive electrode 170D is connected to the second source-drain electrode 120f of the second transistor T2.
Referring to fig. 7 and fig. 8 together, fig. 8 is a schematic circuit connection diagram of an ESD protection structure according to a third embodiment of the invention.
The first conductive electrode 170a is connected to the continuous low level line in this embodiment; the fourth conductive electrode 170d is connected to the continuous high level line; the third conductive electrode 170c is connected to the protected line.
The first transistor T1 is composed of a gate 140a of the first transistor T1, a first source drain 120a of the first transistor T1, a channel 120b of the first transistor, a second source drain 120c of the first transistor T1, and a gate insulating layer 130; the first diode D1 is composed of the second source-drain electrode 120c of the first transistor T1 and the second semiconductor layer 160a of the first diode D1; the second transistor T2 is composed of a gate 140b of the second transistor T2, a gate insulating layer 130, a first source drain 120d of the second transistor T2, a channel 120e of the second transistor T2, and a second source drain 120f of the second transistor T2; the second diode D2 is composed of the second semiconductor layer 160b of the second diode D2 and the first source drain electrode 120D of the second transistor T2.
The working principle of the ESD protection structure in this embodiment is as follows:
when the line to be protected is in a current and voltage state where no electrostatic discharge (i.e. normal line) is generated, the line voltage Vin to be protected is generally smaller than the continuous high-level line voltage Vdd and larger than the continuous low-level line voltage Vss, and even if |vin| is larger than the threshold voltage of the first diode D1 or the second diode T2, the first transistor T1 or the second transistor T2 is not turned on. For example, the line voltage Vin to be protected may be a gate voltage Vgate or a data voltage Vdata for driving the thin film transistor in the display panel, which are generally within ±3v, and the continuous low level line voltage Vss may be generally set to-8V and the continuous high level line voltage Vdd may be set to 4V. At this time, the circuit to be protected is normal and low in loss, and the ESD protection structure connected in parallel to the circuit to be protected does not influence the normal operation of the circuit to be protected.
When the circuit to be protected generates electrostatic discharge in the use process, if negative charge discharge occurs, the voltage Vin of the circuit to be protected is pulled to a very low level instantly, at this time, the N3 end of the first diode D1 belongs to floating point voltage, which is generally larger than the voltage Vin of the circuit to be protected at this time, and the first diode D1 is turned on. Meanwhile, because Vin < < Vss, the threshold voltage vth=vin-Vss < <0 of the first transistor T1, the source-drain of the first transistor T1 is turned on, and negative charge is discharged from the channel 120b of the first transistor T1 to the continuous low-level line, thereby playing a role of protection. Similarly, when positive charges are discharged, the second diode D2 is conducted, and as Vin > VDD, the second transistor T2 is conducted, positive charges are discharged to a continuous high-level line, and the line to be protected is protected.
Referring to fig. 7, fig. 8 and fig. 9 together, fig. 9 is a flow chart illustrating a manufacturing process of an ESD protection structure according to a third embodiment of the invention.
In this embodiment, the difference between the manufacturing method of the ESD protection structure and the manufacturing method of the first embodiment is that the doping ions of the first semiconductor layer in the first transistor T1 and the second transistor T2 are different in step S3, and a patterning operation is required to be added because the first semiconductor layer is doped twice in step S3. In addition, in step S5, the second semiconductor layer 160a of the first diode D1 and the second semiconductor layer 160b of the second diode D2 are doped with different ions, and thus, in step S5, the second semiconductor layer is doped twice, which also requires an additional patterning operation.
In the embodiment, by changing the conductive characteristics of the first semiconductor layer and the second semiconductor layer in the ESD protection structure and connecting the first conductive electrode 170a in the ESD protection structure with the continuous low-level line in the peripheral circuit of the display, the fourth conductive electrode 170d is connected with the continuous high-level line in the peripheral circuit of the display, and the third conductive electrode 170c is connected with the line to be protected, the effect of discharging the charge of the protected line to the high-level or low-level line under the condition of generating electrostatic discharge is achieved, and the electrostatic discharge protection effect is achieved.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a fourth embodiment of an ESD protection structure according to the present invention.
In this embodiment, the first semiconductor layers (120 a and 120 c) in the first transistor T1 are N-type semiconductors, the first semiconductor layers (120D and 120 f) in the second transistor T2 are P-type semiconductors, the second semiconductor layer 160a in the first diode D1 is a P-type semiconductor, and the second semiconductor layer 160b in the second diode D2 is an N-type semiconductor.
The ESD protection structure in this embodiment is the same as that in the third embodiment, and will not be described here again.
Referring to fig. 10 and fig. 11 together, fig. 11 is a schematic circuit connection diagram of an ESD protection structure according to a fourth embodiment of the invention.
The first conductive electrode 170a is connected to the continuous high level line in this embodiment; the fourth conductive electrode 170d is connected to the continuous low level line; the third conductive electrode 170c is connected to the protected line.
The first transistor T1 is composed of a gate 140a of the first transistor T1, a first source drain 120a of the first transistor T1, a channel 120b of the first transistor T1, a second source drain 120c of the first transistor T1, and a gate insulating layer 130; the first diode D1 is composed of the second source-drain electrode 120c of the first transistor and the second semiconductor layer 160a of the first diode D1; the second transistor T2 is composed of a gate 140b of the second transistor T2, a gate insulating layer 130, a first source drain 120d of the second transistor T2, a channel 120e of the second transistor T2, and a second source drain 120f of the second transistor T2; the second diode D2 is composed of the second semiconductor layer 160b of the second diode D2 and the first source drain electrode 120D of the second transistor T2.
The working principle of the ESD protection structure in this embodiment is as follows:
when the line to be protected is in a current and voltage state where no electrostatic discharge (i.e. normal line) is generated, the line voltage Vin to be protected is generally smaller than the continuous high-level line voltage Vdd and larger than the continuous low-level line voltage Vss, and even if |vin| is larger than the threshold voltage of the first diode D1 or the second diode T2, the first transistor T1 or the second transistor T2 is not turned on. For example, the line voltage Vin to be protected may be a gate voltage Vgate or a data voltage Vdata for driving the thin film transistor in the display panel, which are generally within ±3v, and the continuous low level line voltage Vss may be generally set to-8V and the continuous high level line voltage Vdd may be set to 4V. At this time, the circuit to be protected is normal and low in loss, and the ESD protection structure connected in parallel to the circuit to be protected does not influence the normal operation of the circuit to be protected.
When the circuit to be protected generates electrostatic discharge during use, if the circuit to be protected is negatively charged, the voltage Vin of the circuit to be protected is instantaneously pulled to a very high level, at this time, the N6 end of the second diode D2 belongs to a floating point voltage, which is generally smaller than the voltage Vin of the circuit to be protected at this time, and the second diode D2 is turned on. Meanwhile, because Vin < < Vss, the threshold voltage vth=vin-Vss < <0 of the second transistor T2, the source drain of the second transistor T2 is turned on, and negative charge is discharged from the channel 120e of the second transistor T2 to the continuous low-level line, thereby playing a role of protection. Similarly, when positive charges are discharged, the first diode D1 is conducted, and as Vin > VDD, the first transistor T1 is conducted, positive charges are discharged to a continuous high-level line, and the line to be protected is protected.
Referring to fig. 10, 11 and 12, fig. 12 is a flowchart illustrating a manufacturing process of an ESD protection structure according to a fourth embodiment of the invention.
In this embodiment, the manufacturing method of the ESD protection structure is different from that of the third embodiment only in that the first semiconductor layer of the first transistor T1 and the second transistor T2 has the opposite conductive polarity of the doping ions. In addition, the second semiconductor layer 160a of the first diode D1 and the second semiconductor layer 160b of the second diode D2 are doped with ions of a conductivity polarity opposite to that in the third embodiment.
In the embodiment, by changing the conductive characteristics of the first semiconductor layer and the second semiconductor layer in the ESD protection structure and connecting the first conductive electrode 170a in the ESD protection structure with the continuous high-level line in the peripheral circuit of the display, the fourth conductive electrode 170d is connected with the continuous low-level line in the peripheral circuit of the display, and the third conductive electrode 170c is connected with the line to be protected, the effect of discharging the charge of the protected line to the high-level or low-level line under the condition of generating electrostatic discharge is achieved, and the electrostatic discharge protection effect is achieved.
The invention also provides a display device which comprises the ESD protection structure or a manufacturing method applying the ESD protection structure. It is easy to understand that the display device has at least the advantageous effects brought by the above-described embodiments.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. An ESD protection structure is respectively connected with a circuit to be protected, a first level circuit and a second level circuit, and is characterized by comprising a substrate, a first semiconductor layer, a gate insulating layer, a conductive gate layer, an intermediate dielectric layer, a second semiconductor layer, a source-drain conductive electrode layer and a passivation layer; wherein,
The substrate, the first semiconductor layer, the gate insulating layer and the conductive gate layer are sequentially stacked; the first semiconductor layer comprises a source-drain electrode region and a channel region; the intermediate dielectric layer is arranged on one side of the conductive gate layer far away from the gate insulating layer; the second semiconductor layer sequentially penetrates through the intermediate dielectric layer and the gate insulating layer to be connected with the source drain region, so that a first diode and a second diode are formed; the first semiconductor layer, the gate insulating layer, and the conductive gate layer form a first transistor and a second transistor.
2. The ESD protection structure of claim 1, wherein the source-drain conductive electrode layer comprises a first conductive electrode, a second conductive electrode, a third conductive electrode, and a fourth conductive electrode; the first end of the first conductive electrode is connected with the first level line, the first end of the third conductive electrode is connected with the line to be protected, and the first end of the fourth conductive electrode is connected with the second level line.
3. The ESD protection structure of claim 2, wherein the first semiconductor layer is a polysilicon material.
4. The ESD protection structure of claim 3, wherein the second end of the first conductive electrode is connected to the first source-drain of the first transistor, the two ends of the second conductive electrode are connected to the gate of the first transistor and the second source-drain of the first transistor, respectively, the second end of the third conductive electrode is connected to the first diode, the third end of the third conductive electrode is connected to the first source-drain of the second transistor, the third end of the third conductive electrode further overlaps the gate of the second transistor, and the second end of the fourth conductive electrode is connected to the second diode.
5. The ESD protection structure of claim 4, wherein the first semiconductor layer has a conductive characteristic opposite to a conductive characteristic of the second semiconductor layer.
6. The ESD protection structure of claim 3, wherein the source-drain conductive electrode layer further comprises a fifth conductive electrode, the second end of the first conductive electrode is connected to the first source-drain electrode of the first transistor, the two ends of the second conductive electrode are connected to the gate electrode of the first transistor and the second source-drain electrode of the first transistor, the second end of the third conductive electrode is connected to the first diode, the third end of the third conductive electrode is connected to the second diode, the first end of the fifth conductive electrode is connected to the first source-drain electrode of the second transistor, the second end of the fifth conductive electrode is connected to the gate electrode of the second transistor, and the second end of the fourth conductive electrode is connected to the second source-drain electrode of the second transistor.
7. The ESD protection structure of claim 6, wherein the first semiconductor layer in the first transistor has a conductive characteristic opposite to a conductive characteristic of the second semiconductor layer in the first diode, and wherein the first semiconductor layer in the second transistor has a conductive characteristic opposite to a conductive characteristic of the second semiconductor layer in the second diode.
8. A method for manufacturing an ESD protection structure, the method comprising the steps of:
forming a patterned first semiconductor layer on a substrate;
forming a gate insulating layer and a patterned conductive gate layer on the first semiconductor layer;
performing first ion doping on the source-drain electrode region of the first semiconductor;
forming an intermediate dielectric layer on the conductive gate layer and forming two patterned first via structures;
forming a second semiconductor layer in the first via structure, and performing second ion doping on the second semiconductor layer;
forming a plurality of patterned second via structures in the intermediate dielectric layer and the gate insulating layer;
forming a patterned source-drain conductive electrode layer on the second semiconductor layer and in the second via structure;
And forming a passivation layer on the source-drain conductive electrode.
9. The method of claim 8, wherein the step of forming the patterned first semiconductor layer on the substrate uses a low temperature polysilicon process.
10. A display device characterized in that the display device comprises the ESD protection structure according to any one of claims 1 to 7 or the display device applies the ESD protection structure manufacturing method according to claims 8 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911298835.9A CN110993600B (en) | 2019-12-16 | 2019-12-16 | ESD protection structure, manufacturing method of ESD protection structure and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911298835.9A CN110993600B (en) | 2019-12-16 | 2019-12-16 | ESD protection structure, manufacturing method of ESD protection structure and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110993600A CN110993600A (en) | 2020-04-10 |
| CN110993600B true CN110993600B (en) | 2024-03-15 |
Family
ID=70094430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911298835.9A Active CN110993600B (en) | 2019-12-16 | 2019-12-16 | ESD protection structure, manufacturing method of ESD protection structure and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110993600B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116364780A (en) * | 2023-03-27 | 2023-06-30 | 惠科股份有限公司 | Thin film transistor, manufacturing method thereof, electrostatic discharge protection circuit and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365941B1 (en) * | 1998-09-29 | 2002-04-02 | Samsung Electronics Co., Ltd. | Electro-static discharge circuit of semiconductor device, structure thereof and method for fabricating the structure |
| US6781805B1 (en) * | 1999-09-22 | 2004-08-24 | Kabushiki Kaisha Toshiba | Stacked MOSFET protection circuit |
| KR20110097506A (en) * | 2010-02-25 | 2011-08-31 | 주식회사 하이닉스반도체 | Hybride protection device for esd and eos |
| CN104103678A (en) * | 2013-04-02 | 2014-10-15 | 苏州东微半导体有限公司 | U-shaped trench type semiconductor device and manufacture method thereof |
| CN105911787A (en) * | 2016-07-05 | 2016-08-31 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN105977938A (en) * | 2016-06-17 | 2016-09-28 | 中国电子科技集团公司第二十四研究所 | ESD protection circuit for chip |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4917709B2 (en) * | 2000-03-06 | 2012-04-18 | ローム株式会社 | Semiconductor device |
| JP3660566B2 (en) * | 2000-06-30 | 2005-06-15 | 新電元工業株式会社 | Overcurrent limiting semiconductor device |
| TWI247411B (en) * | 2004-07-01 | 2006-01-11 | Toppoly Optoelectronics Corp | Electrostatic discharge protecting device |
| TWI548057B (en) * | 2011-04-22 | 2016-09-01 | 半導體能源研究所股份有限公司 | Semiconductor device |
-
2019
- 2019-12-16 CN CN201911298835.9A patent/CN110993600B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365941B1 (en) * | 1998-09-29 | 2002-04-02 | Samsung Electronics Co., Ltd. | Electro-static discharge circuit of semiconductor device, structure thereof and method for fabricating the structure |
| US6781805B1 (en) * | 1999-09-22 | 2004-08-24 | Kabushiki Kaisha Toshiba | Stacked MOSFET protection circuit |
| KR20110097506A (en) * | 2010-02-25 | 2011-08-31 | 주식회사 하이닉스반도체 | Hybride protection device for esd and eos |
| CN104103678A (en) * | 2013-04-02 | 2014-10-15 | 苏州东微半导体有限公司 | U-shaped trench type semiconductor device and manufacture method thereof |
| CN105977938A (en) * | 2016-06-17 | 2016-09-28 | 中国电子科技集团公司第二十四研究所 | ESD protection circuit for chip |
| CN105911787A (en) * | 2016-07-05 | 2016-08-31 | 厦门天马微电子有限公司 | Array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110993600A (en) | 2020-04-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10038046B2 (en) | Organic light emitting diode display | |
| US10672849B2 (en) | Organic light emitting display device comprising multi-type thin film transistor | |
| US9589995B2 (en) | TFT substrate having three parallel capacitors | |
| CN109326624B (en) | Pixel circuit, manufacturing method thereof and display device | |
| CN106486495B (en) | Thin film transistor base plate, display and its manufacturing method | |
| US10573640B2 (en) | Electro-static discharge assembly with semiconductor layer, array substrate and fabrication method thereof, and display panel | |
| WO2020103909A1 (en) | Array substrate, electrostatic discharge protection circuit and display apparatus | |
| CN105280137A (en) | Organic light emitting display and method of fabricating the same | |
| CN111403418B (en) | Array substrate, manufacturing method thereof and display device | |
| US10937813B2 (en) | Active matrix substrate, liquid crystal display device, organic electroluminescent display device and method for producing active matrix substrate | |
| US9070775B2 (en) | Thin film transistor | |
| US9166181B2 (en) | Hybrid junction field-effect transistor and active matrix structure | |
| JP2006269808A (en) | Semiconductor device and image display device | |
| US20150372021A1 (en) | Display device, array substrate and method for manufacturing the same | |
| KR20130041711A (en) | Thin film semiconductor device for display apparatus and method thereof | |
| JP2011071440A (en) | Organic el display device | |
| CN104347813B (en) | Transistor, the method for manufacturing transistor and the electronic device including transistor | |
| US20220302321A1 (en) | Thin film transistor array substrate, display panel and display device | |
| KR20140037600A (en) | Capacitor and organic light diode display having the same | |
| CN109509793B (en) | Thin film transistor, method of manufacturing the same, and electronic device | |
| CN110993600B (en) | ESD protection structure, manufacturing method of ESD protection structure and display device | |
| CN102214677A (en) | Thin film transistor and display device having the same | |
| CN113192986B (en) | Display panel and preparation method thereof | |
| JP2016025100A (en) | Semiconductor device, display device, and electronic apparatus | |
| CN111092077B (en) | Double-thin-film transistor, preparation method thereof and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |