KR20110097506A - Hybride protection device for esd and eos - Google Patents

Hybride protection device for esd and eos Download PDF

Info

Publication number
KR20110097506A
KR20110097506A KR1020100017383A KR20100017383A KR20110097506A KR 20110097506 A KR20110097506 A KR 20110097506A KR 1020100017383 A KR1020100017383 A KR 1020100017383A KR 20100017383 A KR20100017383 A KR 20100017383A KR 20110097506 A KR20110097506 A KR 20110097506A
Authority
KR
South Korea
Prior art keywords
scr
gate
transistor
unit
diode
Prior art date
Application number
KR1020100017383A
Other languages
Korean (ko)
Inventor
최낙헌
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100017383A priority Critical patent/KR20110097506A/en
Publication of KR20110097506A publication Critical patent/KR20110097506A/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

SUMMARY OF THE INVENTION The present invention provides a hybrid electrostatic discharge protection device capable of simultaneously preventing damage to a semiconductor device by electro-static discharge (ESD) and electric over-stress (EOS), wherein a first diode and a gate are connected to a drain. A silicon-controlled rectifier (SCR) having a structure in which a transistor having a structure is connected in series; A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And a sensing unit connected between the drain and the gate of the transistor in the N-th (N is a natural number except 0) SCR of the discharge unit, and having a structure in which a plurality of second diodes are connected in series. do.

Description

HYBRIDE PROTECTION DEVICE FOR ESD AND EOS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a hybrid electrostatic discharge protection device capable of simultaneously preventing damage to a semiconductor device caused by electro-static discharge (ESD) and electric over-stress (EOS).

The semiconductor device is essentially provided with an electrostatic discharge protection device for protecting the semiconductor device from electrostatic discharge and electric shock. In this case, electrostatic discharge (ESD), which is an electrostatic discharge phenomenon, is a discharge phenomenon in which a finite amount of charge rapidly moves between two objects having different potentials, which is performed for several hundred pico seconds (ps) to several micro seconds (μs). It means discharge phenomenon. In addition, EOS (Electric Over-Stress), which is an electric shock phenomenon, is an electric shock such as leakage current and abnormal transient current voltage caused by a voltage of a power supply equipment, and is usually used for several nanoseconds (ns) to several milliseconds (ms). Is done.

As such, ESD and EOS differ in the electrical transient pulse width. For this reason, various techniques have been developed for electrostatic discharge protection devices for protecting semiconductor devices from ESD because it is very important to detect a fast ESD pulse and operate quickly. However, the technology for the electrostatic discharge protection device for protecting the semiconductor device from EOS is relatively poorly developed. On the contrary, ESD technology has been developed to cope with a high operating speed, and there is a problem in that EOS, which is a relatively slow pulse with a small magnitude of voltage and / or current, cannot operate.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a hybrid electrostatic discharge protection device capable of simultaneously preventing damage to a semiconductor device by ESD and EOS.

According to an aspect of the present invention, there is provided a hybrid electrostatic discharge protection device of a semiconductor-controlled rectifier (SCR) having a structure in which a transistor having a structure in which a first diode and a gate are connected to a drain is connected in series; A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And a sensing unit connected between the drain and the gate of the transistor in the N-th (N is a natural number except 0) SCR of the discharge unit, and having a structure in which a plurality of second diodes are connected in series.

The sensing unit may have a structure connected in a forward direction between the drain and the gate of the transistor in the N-th SCR of the discharge unit.

The second diode may include a transistor having a structure in which a gate and a drain are connected (ie, a MOS diode), and the transistor may include an NMOS transistor. The body region of the transistor may be connected to a ground portion.

The detector includes a drain of the first diode connected to the drain of the Nth SCR, a source of the second diode connected to the gate of the Nth SCR, and N (N is a natural number except 0). The source of the second diode may have a structure connected to the drain of the N + first second diode.

The first diode may have a structure connected in a forward direction to the transistor, the first diode may include a PN junction diode, and the transistor may include an NMOS transistor. The body region of the transistor may be connected to a ground portion.

A discharge part having a structure in which a plurality of the SCRs are connected in series includes a first diode in the SCR connected between the pad part and the internal circuit part, and a source of a transistor in the SCR is connected to the ground part. N may be a natural number excluding 0) and the source of the transistor in the SCR and the diode in the N + 1 th SCR may be connected in series.

According to another aspect of the present invention, a hybrid electrostatic discharge protection device of the present invention is formed on a substrate and adjacent to each other of the first well of the second conductive type and the first well of the first conductive type, and the first well. A first impurity region having a first conductivity type, a first gate formed on the second well, and formed on one side of the first gate to cross the first well and the second well at the same time, and are connected to the first gate An SCR comprising a second impurity region of a second conductivity type and a third impurity region of a second conductivity type formed in the second well of the other side of the first gate; A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and the plurality of SCRs connected in series; And a sensing unit connected between the second impurity region and the first gate of the Nth (N is a natural number except 0) SCR of the discharge unit, and having a structure in which a plurality of diodes are connected in series.

The sensing unit may have a structure connected in a forward direction between the second impurity region and the first gate of the N-th SCR of the discharge unit.

The sensing unit may have a structure in which a plurality of MOS diodes are connected in series. Specifically, the MOS diode is a third well of the first conductive type formed on the substrate, a second gate formed on the third well, a fourth of the second conductive type formed on the third well on both sides of the second gate. It may have a structure including an impurity region, the fourth impurity region formed on one side of the second gate and the second gate.

The semiconductor device may further include a fifth impurity region of the first conductivity type formed in the third well, and the fifth impurity region may be connected to the ground portion.

A discharge part having a structure in which a plurality of the SCRs are connected in series includes a first impurity region of the first SCR connected between the pad portion and the internal circuit portion, and a third impurity region of the SCR last connected to the ground portion. The N (N is a natural number excluding 0) may have a structure in which a third impurity region of the SCR and an N + 1 th impurity region of the SCR are connected in series.

The second well may be connected to a ground.

The second conductive type of the first conductive type may be a complementary conductive type to each other. Specifically, the first conductive type may be a P type, and the second conductive type may be an N type.

The present invention based on the above-described problem solving means can effectively prevent damage to the semiconductor device by ESD and EOS, in particular, ESD by configuring the discharge unit by using an SCR having a larger electrostatic discharge current than a diode and a MOS transistor. It has an effect.

In addition, the present invention can increase the operation holding voltage of the electrostatic discharge protection device by having a discharge unit connected in series with a plurality of SCR, in particular, because the operation holding voltage of the electrostatic discharge protection device can be larger than the power supply voltage. There is an effect that can ensure the operating characteristics of the stable electrostatic discharge protection device. In addition, by increasing the operation holding voltage of the discharge portion, there is an effect that can improve the latch-up characteristics of the electrostatic discharge protection device.

In addition, since the present invention includes a sensing unit 104, since the operation start voltage of the electrostatic discharge protection device can be easily designed (or controlled), the semiconductor by EOS having a relatively small size and slow pulse compared to ESD. There is an effect that can effectively prevent damage to the device.

As a result, the present invention can prevent damage to the semiconductor device by ESD and EOS at the same time, there is an effect that can improve the operating characteristics of the electrostatic discharge protection device.

1 is an equivalent circuit diagram of a hybrid electrostatic discharge protection device according to a first embodiment of the present invention.
2 is a cross-sectional view showing a hybrid electrostatic discharge protection device according to a first embodiment of the present invention.
3 is an equivalent circuit diagram of a hybrid electrostatic discharge protection device according to a second embodiment of the present invention.
4 is a cross-sectional view showing a hybrid electrostatic discharge protection device according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention to be described later, the present invention to be described later provides a hybrid electrostatic discharge protection device that can simultaneously prevent damage to the semiconductor device by the electro-static discharge (ESD) and electrical over-stress (EOS). To this end, the present invention is characterized by configuring an electrostatic discharge protection device using a silicon controlled rectifier (SCR) to control large ESD current and EOS current in a small size. In addition, it is another feature to connect a plurality of SCRs in series so that the operation holding voltage of the electrostatic discharge protection device is greater than the power supply voltage. In addition, the present invention is to control the operation start voltage of the electrostatic discharge protection device to effectively prevent the damage of the semiconductor device by ESD and EOS, in particular EOS, the voltage of the voltage is smaller than the power supply voltage by detecting a slow pulse voltage It is still another feature to have a sensing unit for operating the electrostatic discharge protection device only when applied.

Hereinafter, the technical concept of the present invention will be described in detail by illustrating a case in which a discharge unit and a sensing unit have a structure in which two SCRs and two MOS diodes are connected in series. At this time, in the embodiments of the present invention, but for the convenience of description, the discharge unit and the sensing unit has been illustrated that each has a structure in which two SCR and two MOS diodes are connected in series, electrostatic discharge protection to which the technical idea of the present invention is applied The device may have a structure in which a discharge unit and a sensing unit are each connected with two or more SCRs and a MOS diode in series.

In addition, in the following description, the first conductive type and the second conductive type are complementary conductive types. That is, if the first conductivity type is P type, the second conductivity type is N type. Of course, the first conductive type may be N type and the second conductive type may be P type. In the first and second embodiments of the present invention, the first conductive type is P type and the second conductive type is N type.

1 and 2 are diagrams illustrating a hybrid electrostatic discharge protection device according to a first embodiment of the present invention. FIG. 1 is an equivalent circuit, and FIG. 2 is a cross-sectional view.

First, referring to FIG. 1, the hybrid electrostatic discharge protection device according to the first embodiment of the present invention is described in terms of circuits. In this case, the first diode 25 and the transistor 26 having the structure in which the gate is connected to the drain are connected in series. SCR (103A, 103B) having a connected structure, one side is connected between the pad portion 101 and the internal circuit portion 105, the other side is connected to the ground portion 102, a plurality of SCR (103A, 103B) in series The discharge part 103 and the Nth (N is a natural number excluding 0) of the discharge part 103 connected between the drain and the gate of the transistor 26 in the SCR 103A, 103B. The two diodes 27 include a sensing unit 104 having a structure connected in series.

The SCR constituting the discharge unit 103 has a larger electrostatic discharge current per unit area and a smaller junction capacitance than a diode, a MOS transistor, and the like, which are commonly used in an electrostatic discharge protection device. It has the advantage of low operating resistance. Therefore, by configuring the discharge unit 103 in the SCR, it is possible to effectively prevent damage to the semiconductor device by ESD and EOS.

In addition, the SCRs 103A and 103B constituting the discharge unit 103 have a structure in which the first diode 25 and the transistor 26 whose gate is connected to the drain are connected in series. In this case, the first diode 25 may include a PN junction diode, and the transistor 26 may include an NMOS transistor. The N region of the PN junction diode and the drain of the NMOS transistor are connected in series, that is, the first diode 25 is connected to the transistor 26 in the forward direction. For reference, the transistor 26 having the gate connected to the drain has an operating characteristic similar to that of the first diode 25.

In addition, the body region of the transistor 26 in the SCRs 103A and 103B is connected to the ground portion 102. In this case, the body region of the transistor 26 means a substrate or a well on which the transistor 26 is formed.

As described above, in the discharge part 103 in which a plurality of SCRs 103A and 103B are connected in series, the first diode 25 in the first SCR 103A and 103B is connected between the pad part 101 and the internal circuit part 105. The source of the transistor 26 in the last SCR 103A, 103B is connected to the ground portion 102, and N (N is a natural number excluding 0) and the source of the transistor 26 in the SCR 103A, 103B. The first diode 25 in the N + 1th SCRs 103A, 103B is connected in series.

Here, since the operation holding voltage of the discharge unit 103, that is, the operation holding voltage of the electrostatic discharge protection device increases in proportion to the number of SCRs 103A and 103B connected in series, the operation holding voltage of the discharge unit 103 is increased. It is preferable to adjust the number of SCRs 103A and 103B connected in series so as to be larger than the power supply voltage applied through the pad unit 101 (power supply voltage <operation holding voltage). For reference, when the operation holding voltage of the discharge unit 103 is smaller than the power supply voltage, the ESD protection device maintains the bypass path continuously without being turned off after the ESD protection device is operated once by the ESD or EOS. A problem occurs.

The sensing unit 104 controls the operation start voltage of the electrostatic discharge protection device so as to effectively prevent damage of the semiconductor device caused by ESD and EOS, in particular, EOS. Only when a large voltage is applied to the pad portion 101 serves to operate the electrostatic discharge protection device. That is, in order to effectively prevent damage to the semiconductor device by ESD and EOS which are larger than the power supply voltage, the start voltage of the electrostatic discharge protection device is larger than the power supply voltage (power supply voltage <operation start voltage), but the difference between them is as small as possible. It is preferable. Accordingly, the detector 104 controls the operation start voltage of the electrostatic discharge protection device so that the operation start voltage of the electrostatic discharge protection device is greater than the power supply voltage, but the difference therebetween is as small as possible.

The sensing unit 104 performing the above-described role may have a structure in which a plurality of second diodes 27 are connected in series. At this time, since the operation start voltage of the electrostatic discharge protection device increases in proportion to the number of the second diodes 27 connected in series, the second device connected in series considering the power supply voltage and the operation holding voltage of the discharge unit 103. It is desirable to adjust the number of diodes 27. For reference, in order for the electrostatic discharge protection device to operate normally, it is preferable that the operation start voltage is larger than the operation holding voltage, but the difference therebetween is small (power supply voltage <operation holding voltage <operation start voltage).

The second diode 27 constituting the sensing unit 104 may use a PN junction diode or a MOS diode, that is, a transistor having a gate connected to a drain. In this case, the second diode 27 constituting the sensing unit 104 may be formed of a MOS diode for the connection relationship between the sensing unit 104 and the discharge unit 103 and process efficiency. Here, the MOS diode may be an NMOS transistor.

The body region of the MOS diode constituting the second diode 27 is connected to the ground portion 102. In this case, the body region of the MOS diode refers to a substrate or a well on which the MOS diode is formed.

The sensing unit 104 is preferably connected in a forward direction between the gate and the drain of the transistor 26 in the N-th SCRs 103A and 103B of the discharge unit 103. That is, when the second diode 27 is a MOS diode, the drain of the first second diode 27 is connected to the drain of the transistor 26 in the SCRs 103A and 103B, and the last of the second diode 27 The source is connected to the gate of the SCR, and the source of the N (N is a natural number excluding 0) second diode 27 is connected to the drain of the N + 1 second diode 27.

An example of a method of designing an operation start voltage of an electrostatic discharge protection device including the operation and detection unit 104 of the hybrid electrostatic discharge protection device according to the first embodiment of the present invention having the above-described structure is as follows.

When an abnormal voltage greater than the power supply voltage, that is, an ESD voltage or an EOS voltage is applied to the pad unit 101, the first SCR 103A of the discharge unit 103 operates to bypass the current, and the bypassed current detects the sensing unit ( The second SCR 103B of the discharge portion 103 is passed through 104 to cause a voltage difference between the gate of the transistor 26 in the second SCR 103B of the discharge portion 103 and the ground portion 102 -or the source-. As the transistor 26 of FIG. 7 is turned on, an abnormal voltage applied to the pad unit 101 is bypassed to the ground unit 102.

At this time, assuming that both the first diodes 25 and the start voltages of the transistors 26 constituting the SCRs 103A and 103B are 0.7 (V), the start voltages of the electrostatic discharge protection device are two first diodes. (25), 3.5 (V), which is the sum of the operation start voltages of each of the second transistors 27 in the transistor 26 and the sensing unit 104 of the first SCR 103A.

Next, referring to the structure of the hybrid electrostatic discharge protection device according to the first embodiment of the present invention with reference to Figure 2, the first well 13 and the second conductive type formed on the substrate 11 adjacent to each other The second well 14 of the first conductivity type, the first impurity region 17 of the first conductivity type formed in the first well 13, and the second well 14 are formed on the second well 14 and the gate insulating film 22 and the gate. The electrode 23 is formed on one side of the first gate 24A and the first gate 24A having a stacked structure to cross the first well 13 and the second well 14 at the same time, and the first gate 24A. SCR 103A including a second impurity region 18 of the second conductivity type connected to the second impurity region 18 and a third impurity region 19 of the second conductivity type formed in the second second well 14 of the first gate 24A. , 103B), a discharge part having a structure in which one side is connected between the pad portion 101 and the internal circuit portion 105, the other side is connected to the ground portion 102, and a plurality of SCRs 103A and 103B are connected in series ( 103) and N of the discharge part 103, where N is 0 The sensing unit 104 is connected between the second impurity region 18 and the first gate 24A of the second SCR 103A, 103B, and has a structure in which a plurality of second diodes 27 are connected in series. Include.

The sensing unit 104 has a structure connected in a forward direction between the second impurity region 18 of the Nth SCRs 103A and 103B of the discharge unit 103 and the first gate 24A, and the gate of the transistor is connected to the drain. Multiple connected MOSFETs may have a structure connected in series.

Specifically, the second diode 27 made of MOS diode is formed on the third well 15 and the third well 15 of the first conductivity type formed on the substrate 11, and the gate insulating film 22 and the gate are formed. A second impurity region 20 of a second conductivity type formed in the second gate 24B having the structure in which the electrodes 23 are stacked, and the third well 15 on both sides of the second gate 24B, The fourth impurity region 20 formed on one side of the gate 24B and the second gate 24B are connected to each other. In this case, the third well 15 has a structure connected to the ground portion 102.

In the discharge part 103 in which a plurality of SCRs 103A and 103B are connected in series, the first impurity region 17 in the first SCR 103A and 103B is connected between the pad part 101 and the internal circuit part 105. The third impurity region 19 in the last SCR 103A, 103B is connected to the ground portion 102, and N (N is a natural number except 0) in the third impurity region 19 in the SCR 103A, 103B. And the first impurity region 17 in the N + 1 th SCRs 103A and 103B are connected in series.

Here, the first diode 25 in the SCRs 103A and 103B is a PN junction diode formed by the junction of the first impurity region 17 and the first well 13, and the transistor 26 in the SCRs 103A and 103B. Is composed of a first gate 24A, a second impurity region 18 and a third impurity region 19. In this case, the second impurity region 18 serves as a drain, the third impurity region 19 serves as a source, and the second well 14 in which the transistor 26 is formed is connected to the ground portion 102. Has The reason why the second impurity region 18 is formed to cross the first well 13 and the second well 14 at the same time is to connect the first diode 25 and the transistor 26 in series. .

In addition, the hybrid electrostatic discharge protection device according to the first embodiment of the present invention is the fourth well 16, the third conductive type formed on the substrate 11 under the first and second wells 13, 14 Between the fifth impurity region 21 of the first conductivity type formed in the well 15 and the adjacent SCRs 103A and 103B, between the first impurity region 17 and the second impurity region 18, the discharge portion 103. The device isolation layer 12 may further include a separation between the detection unit 104 and the fourth impurity region 20 and the fifth impurity region 21. In this case, the fourth well 16 may have a higher impurity doping concentration than the first and second wells 13 and 14. In addition, the fifth impurity region 21 may serve as a pick-up region and may be connected to the ground portion 102.

The hybrid electrostatic discharge protection device according to the first embodiment of the present invention having the structure shown in FIGS. 1 and 2 uses the SCRs 103A and 103B having a larger electrostatic discharge current compared to diodes and morph transistors. ), It is possible to effectively prevent damage to the semiconductor device by ESD and EOS, in particular ESD.

In addition, since the plurality of SCRs 103A and 103B include a discharge unit 103 connected in series, it is possible to increase the operation holding voltage of the electrostatic discharge protection device. Since it can be taken larger, the operating characteristics of the stable electrostatic discharge protection device can be secured. In addition, by increasing the operation holding voltage of the discharge unit 103, it is possible to improve the latch-up characteristics of the electrostatic discharge protection device.

In addition, since the sensing unit 104 can easily design (or control) the operation start voltage of the electrostatic discharge protection device, damage to the semiconductor device due to EOS having a relatively small size and slow pulse compared to ESD can be achieved. Can be effectively prevented.

As a result, the electrostatic discharge protection device according to the first embodiment of the present invention can prevent damage to the semiconductor device by ESD and EOS at the same time, it is possible to improve the operating characteristics of the electrostatic discharge protection device.

Hereinafter, in the second embodiment of the present invention, the configuration of the discharge unit and the sensing unit controls the operation start voltage of the electrostatic discharge protection device by adjusting the connection position of the sensing unit 104 in the same structure as the first embodiment of the present invention. The case will be described. Therefore, for the convenience of description, the same reference numerals are used for the same components as those of the first embodiment of the present invention, and detailed description thereof will be omitted.

3 and 4 illustrate a hybrid electrostatic discharge protection device according to a second embodiment of the present invention. FIG. 3 is an equivalent circuit diagram and FIG. 4 is a sectional view.

3 and 4, the overall configuration is the same as in the first embodiment of the present invention. However, in the first exemplary embodiment of the present invention, the sensing unit 104 is connected to the last SCR 103B of the discharging unit 103. However, in the second exemplary embodiment of the present invention, the sensing unit 104 is a discharge unit ( It is a structure connected to the first SCR 103A of 103.

An example of the method of designing the operation start voltage of the electrostatic discharge protection device according to the operation and detection unit 104 of the hybrid electrostatic discharge protection device according to the second embodiment of the present invention having the above-described structure is as follows.

When an abnormal voltage larger than the power supply voltage, that is, an ESD voltage or an EOS voltage is applied to the pad unit 101, a current flows through the first diode 25 of the first SCR 103A of the discharge unit 103, and the flowed current flows into the pad unit 101. Of the first SCR 103A of the discharge section 103 by passing through the sensing section 104 and causing a voltage difference between the gate of the transistor 26 in the first SCR 103A and the ground section 102 -or source. Transistor 26 is turned on. Subsequently, as the transistor 26 of the first SCR 103A is turned on, the second SCR 103B of the discharge unit 103 is operated by the current bypassed through the first SCR 103A to operate on the pad unit 101. The applied abnormal voltage is bypassed to the ground portion 102.

At this time, if it is assumed that the operating voltages of the first diodes 25 and the transistors 26 of the SCRs 103A and 103B are 0.7 (V), the operating voltage of the electrostatic discharge protection device is one first diode. Denoted at 2.1 (V) which is the sum of the operation start voltages of the two second diodes 27 in the 25 and the sensing unit 104, respectively.

Comparing the first embodiment and the second embodiment of the present invention, as the configuration of the discharge unit 103 and the detection unit 104 adjusts the connection position of the detection unit 104 under the same conditions of the electrostatic discharge protection device It can be seen that the operation start voltage can be adjusted.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

11 substrate 12 device isolation film
13: first well 14: second well
15: third well 16: fourth well
17: first impurity region 18: second impurity region
19: third impurity region 20: fourth impurity region
21: fifth impurity region 22: gate insulating film
23: gate electrode 24A: first gate
24B: second gate 25: first diode
26 transistor 27 second diode
101: pad portion 102: ground portion
103: discharge unit 103A, 103B: SCR
104: detecting unit 105: internal circuit unit

Claims (19)

A silicon-controlled rectifier (SCR) having a structure in which a transistor having a structure in which a first diode and a gate are connected to a drain is connected in series;
A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And
N-th (N is a natural number except 0) of the discharge portion is a sensing unit having a structure connected between the drain and the gate of the transistor in the SCR, a plurality of second diodes connected in series
Hybrid electrostatic discharge protection device comprising a.
The method of claim 1,
And the sensing unit is connected in a forward direction between the drain and the gate of the transistor in the Nth SCR of the discharge unit.
The method of claim 1,
And the second diode includes a transistor having a structure in which a gate and a drain are connected to each other.
The method of claim 3,
And said transistor comprises an NMOS transistor.
The method of claim 3,
And a body region of the transistor is connected to ground.
The method of claim 3,
The detector includes a drain of the first diode connected to the drain of the Nth SCR, a source of the second diode connected to the gate of the Nth SCR, and N (N is a natural number except 0). And a source of the second diode connected to a drain of the N + first second diode.
The method of claim 1,
And the first diode has a structure connected in a forward direction to the transistor.
The method of claim 1,
And said first diode comprises a PN junction diode and said transistor comprises an NMOS transistor.
The method of claim 1,
And a body region of the transistor is connected to ground.
The method of claim 1,
A discharge unit having a structure in which a plurality of the SCRs are connected in series,
The first diode in the SCR is connected between the pad part and the internal circuit part, the last source of the transistor in the SCR is connected to the ground part, and the N (N is a natural number except 0) source of the transistor in the SCR. And a N + 1 th diode in the SCR, the hybrid electrostatic discharge protection device having a structure connected in series.
A first well of a second conductive type and a second well of a first conductive type formed on a substrate and adjacent to each other, a first impurity region of a first conductive type formed in the first well, and a first formed on the second well A second impurity region of a second conductivity type connected to the first gate and the second well connected to the first gate, the gate being formed at one side of the first gate and simultaneously crossing the first well and the second well; An SCR including a third impurity region of a second conductivity type formed in the second conductive region;
A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And
The sensing unit having a structure connected between the second impurity region and the first gate of the N-th (N is a natural number except 0) SCR of the discharge unit, and a plurality of diodes are connected in series
Hybrid electrostatic discharge protection device comprising a.
The method of claim 11,
And the sensing unit is connected in a forward direction between the second impurity region and the first gate of the N-th SCR of the discharge unit.
The method of claim 11,
The sensing unit has a hybrid electrostatic discharge protection device having a structure in which a plurality of MOS diodes are connected in series.
The method of claim 13,
The MOS diodes may include a third well of the first conductive type formed on the substrate, a second gate formed on the third well, and a fourth impurity region of the second conductive type formed in the third well on both sides of the second gate. And a fourth impurity region formed on one side of the second gate and the second gate connected thereto.
The method of claim 14,
Further comprising a fifth impurity region of the first conductivity type formed in the third well,
And the fifth impurity region is connected to a ground.
The method of claim 11,
A discharge unit having a structure in which a plurality of the SCRs are connected in series
A first impurity region of the first SCR is connected between the pad portion and the internal circuit portion, a third impurity region of the last SCR is connected to the ground portion, and N (N is a natural number except 0) the SCR. And a third impurity region of the NCR and the first impurity region of the SCR in series.
The method of claim 11,
And the second well is connected to a ground.
The method according to any one of claims 11 to 17,
And the second conductive type of the first conductive type is a conductive type complementary to each other.
The method of claim 18,
And the first conductive type is P type, and the second conductive type is N type.

KR1020100017383A 2010-02-25 2010-02-25 Hybride protection device for esd and eos KR20110097506A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100017383A KR20110097506A (en) 2010-02-25 2010-02-25 Hybride protection device for esd and eos

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100017383A KR20110097506A (en) 2010-02-25 2010-02-25 Hybride protection device for esd and eos

Publications (1)

Publication Number Publication Date
KR20110097506A true KR20110097506A (en) 2011-08-31

Family

ID=44932515

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100017383A KR20110097506A (en) 2010-02-25 2010-02-25 Hybride protection device for esd and eos

Country Status (1)

Country Link
KR (1) KR20110097506A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101272762B1 (en) * 2013-02-20 2013-06-11 주식회사 아나패스 An electronic apparatus equipped with esd and eos protection circuit unit
TWI511262B (en) * 2012-06-26 2015-12-01 Globalfoundries Sg Pte Ltd Latch-up free esd protection
CN106158850A (en) * 2016-08-26 2016-11-23 华为技术有限公司 Electrostatic discharge protective equipment and multi-power domain integrated circuit
CN110993600A (en) * 2019-12-16 2020-04-10 广东聚华印刷显示技术有限公司 ESD protection structure, preparation method and display device
CN110993600B (en) * 2019-12-16 2024-03-15 广东聚华印刷显示技术有限公司 ESD protection structure, manufacturing method of ESD protection structure and display device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI511262B (en) * 2012-06-26 2015-12-01 Globalfoundries Sg Pte Ltd Latch-up free esd protection
KR101272762B1 (en) * 2013-02-20 2013-06-11 주식회사 아나패스 An electronic apparatus equipped with esd and eos protection circuit unit
CN106158850A (en) * 2016-08-26 2016-11-23 华为技术有限公司 Electrostatic discharge protective equipment and multi-power domain integrated circuit
CN106158850B (en) * 2016-08-26 2019-06-11 华为技术有限公司 Electrostatic discharge protective equipment and multi-power domain integrated circuit
US10784679B2 (en) 2016-08-26 2020-09-22 Huawei Technologies Co., Ltd. Electrostatic discharge protection apparatus and integrated circuit with multiple power domains
CN110993600A (en) * 2019-12-16 2020-04-10 广东聚华印刷显示技术有限公司 ESD protection structure, preparation method and display device
CN110993600B (en) * 2019-12-16 2024-03-15 广东聚华印刷显示技术有限公司 ESD protection structure, manufacturing method of ESD protection structure and display device

Similar Documents

Publication Publication Date Title
CN108701693B (en) Embedded PMOS-triggered silicon controlled rectifier for electrostatic discharge protection
TWI713189B (en) Low capacitance transient voltage suppressor
CN101290933B (en) Electrostatic discharge protection device
CN107230673B (en) Electrostatic discharge protection apparatus and method using a protection region
JP5242675B2 (en) ESD protection circuit with reduced trigger voltage
US7274546B2 (en) Apparatus and method for improved triggering and leakage current control of ESD clamping devices
TWI469308B (en) Power-rail esd clamp circuit
CN103579224B (en) ESD protects
JP2006319330A (en) Device for protecting from electrostatic discharge
CN102195280B (en) Electro-static discharge protection circuit and semiconductor device
TWI609475B (en) An esd device for a semiconductor structure
CN105655325A (en) Electrostatic discharge protection circuit, and electrostatic discharge protection structure and manufacturing method thereof
US9035363B2 (en) JFET ESD protection circuit for low voltage applications
CN108091647B (en) Self-biased bi-directional ESD protection circuit
US20080198519A1 (en) Electrostatic discharge protection element having an improved area efficiency
KR20110097506A (en) Hybride protection device for esd and eos
WO2016017386A1 (en) Protection element, protection circuit, and semiconductor integrated circuit
JP5532566B2 (en) Semiconductor device
CN102148226A (en) Semiconductor device
US10446539B2 (en) Electrostatic discharge (ESD) protection device and method for operating an ESD protection device
JP2008172216A (en) Well potential triggered esd protection
US8866200B2 (en) JFET ESD protection circuit for low voltage applications
CN108987393B (en) Bidirectional ESD structure for protecting power integrated circuit output LDMOS device
KR20110097505A (en) Hybride protection device for esd and eos
CN101394081A (en) Electro-static discharge protection design with low capacitance

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination