KR20110097506A - Hybride protection device for esd and eos - Google Patents
Hybride protection device for esd and eos Download PDFInfo
- Publication number
- KR20110097506A KR20110097506A KR1020100017383A KR20100017383A KR20110097506A KR 20110097506 A KR20110097506 A KR 20110097506A KR 1020100017383 A KR1020100017383 A KR 1020100017383A KR 20100017383 A KR20100017383 A KR 20100017383A KR 20110097506 A KR20110097506 A KR 20110097506A
- Authority
- KR
- South Korea
- Prior art keywords
- scr
- gate
- transistor
- unit
- diode
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Abstract
SUMMARY OF THE INVENTION The present invention provides a hybrid electrostatic discharge protection device capable of simultaneously preventing damage to a semiconductor device by electro-static discharge (ESD) and electric over-stress (EOS), wherein a first diode and a gate are connected to a drain. A silicon-controlled rectifier (SCR) having a structure in which a transistor having a structure is connected in series; A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And a sensing unit connected between the drain and the gate of the transistor in the N-th (N is a natural number except 0) SCR of the discharge unit, and having a structure in which a plurality of second diodes are connected in series. do.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a hybrid electrostatic discharge protection device capable of simultaneously preventing damage to a semiconductor device caused by electro-static discharge (ESD) and electric over-stress (EOS).
The semiconductor device is essentially provided with an electrostatic discharge protection device for protecting the semiconductor device from electrostatic discharge and electric shock. In this case, electrostatic discharge (ESD), which is an electrostatic discharge phenomenon, is a discharge phenomenon in which a finite amount of charge rapidly moves between two objects having different potentials, which is performed for several hundred pico seconds (ps) to several micro seconds (μs). It means discharge phenomenon. In addition, EOS (Electric Over-Stress), which is an electric shock phenomenon, is an electric shock such as leakage current and abnormal transient current voltage caused by a voltage of a power supply equipment, and is usually used for several nanoseconds (ns) to several milliseconds (ms). Is done.
As such, ESD and EOS differ in the electrical transient pulse width. For this reason, various techniques have been developed for electrostatic discharge protection devices for protecting semiconductor devices from ESD because it is very important to detect a fast ESD pulse and operate quickly. However, the technology for the electrostatic discharge protection device for protecting the semiconductor device from EOS is relatively poorly developed. On the contrary, ESD technology has been developed to cope with a high operating speed, and there is a problem in that EOS, which is a relatively slow pulse with a small magnitude of voltage and / or current, cannot operate.
SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a hybrid electrostatic discharge protection device capable of simultaneously preventing damage to a semiconductor device by ESD and EOS.
According to an aspect of the present invention, there is provided a hybrid electrostatic discharge protection device of a semiconductor-controlled rectifier (SCR) having a structure in which a transistor having a structure in which a first diode and a gate are connected to a drain is connected in series; A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And a sensing unit connected between the drain and the gate of the transistor in the N-th (N is a natural number except 0) SCR of the discharge unit, and having a structure in which a plurality of second diodes are connected in series.
The sensing unit may have a structure connected in a forward direction between the drain and the gate of the transistor in the N-th SCR of the discharge unit.
The second diode may include a transistor having a structure in which a gate and a drain are connected (ie, a MOS diode), and the transistor may include an NMOS transistor. The body region of the transistor may be connected to a ground portion.
The detector includes a drain of the first diode connected to the drain of the Nth SCR, a source of the second diode connected to the gate of the Nth SCR, and N (N is a natural number except 0). The source of the second diode may have a structure connected to the drain of the N + first second diode.
The first diode may have a structure connected in a forward direction to the transistor, the first diode may include a PN junction diode, and the transistor may include an NMOS transistor. The body region of the transistor may be connected to a ground portion.
A discharge part having a structure in which a plurality of the SCRs are connected in series includes a first diode in the SCR connected between the pad part and the internal circuit part, and a source of a transistor in the SCR is connected to the ground part. N may be a natural number excluding 0) and the source of the transistor in the SCR and the diode in the N + 1 th SCR may be connected in series.
According to another aspect of the present invention, a hybrid electrostatic discharge protection device of the present invention is formed on a substrate and adjacent to each other of the first well of the second conductive type and the first well of the first conductive type, and the first well. A first impurity region having a first conductivity type, a first gate formed on the second well, and formed on one side of the first gate to cross the first well and the second well at the same time, and are connected to the first gate An SCR comprising a second impurity region of a second conductivity type and a third impurity region of a second conductivity type formed in the second well of the other side of the first gate; A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and the plurality of SCRs connected in series; And a sensing unit connected between the second impurity region and the first gate of the Nth (N is a natural number except 0) SCR of the discharge unit, and having a structure in which a plurality of diodes are connected in series.
The sensing unit may have a structure connected in a forward direction between the second impurity region and the first gate of the N-th SCR of the discharge unit.
The sensing unit may have a structure in which a plurality of MOS diodes are connected in series. Specifically, the MOS diode is a third well of the first conductive type formed on the substrate, a second gate formed on the third well, a fourth of the second conductive type formed on the third well on both sides of the second gate. It may have a structure including an impurity region, the fourth impurity region formed on one side of the second gate and the second gate.
The semiconductor device may further include a fifth impurity region of the first conductivity type formed in the third well, and the fifth impurity region may be connected to the ground portion.
A discharge part having a structure in which a plurality of the SCRs are connected in series includes a first impurity region of the first SCR connected between the pad portion and the internal circuit portion, and a third impurity region of the SCR last connected to the ground portion. The N (N is a natural number excluding 0) may have a structure in which a third impurity region of the SCR and an N + 1 th impurity region of the SCR are connected in series.
The second well may be connected to a ground.
The second conductive type of the first conductive type may be a complementary conductive type to each other. Specifically, the first conductive type may be a P type, and the second conductive type may be an N type.
The present invention based on the above-described problem solving means can effectively prevent damage to the semiconductor device by ESD and EOS, in particular, ESD by configuring the discharge unit by using an SCR having a larger electrostatic discharge current than a diode and a MOS transistor. It has an effect.
In addition, the present invention can increase the operation holding voltage of the electrostatic discharge protection device by having a discharge unit connected in series with a plurality of SCR, in particular, because the operation holding voltage of the electrostatic discharge protection device can be larger than the power supply voltage. There is an effect that can ensure the operating characteristics of the stable electrostatic discharge protection device. In addition, by increasing the operation holding voltage of the discharge portion, there is an effect that can improve the latch-up characteristics of the electrostatic discharge protection device.
In addition, since the present invention includes a
As a result, the present invention can prevent damage to the semiconductor device by ESD and EOS at the same time, there is an effect that can improve the operating characteristics of the electrostatic discharge protection device.
1 is an equivalent circuit diagram of a hybrid electrostatic discharge protection device according to a first embodiment of the present invention.
2 is a cross-sectional view showing a hybrid electrostatic discharge protection device according to a first embodiment of the present invention.
3 is an equivalent circuit diagram of a hybrid electrostatic discharge protection device according to a second embodiment of the present invention.
4 is a cross-sectional view showing a hybrid electrostatic discharge protection device according to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.
The present invention to be described later, the present invention to be described later provides a hybrid electrostatic discharge protection device that can simultaneously prevent damage to the semiconductor device by the electro-static discharge (ESD) and electrical over-stress (EOS). To this end, the present invention is characterized by configuring an electrostatic discharge protection device using a silicon controlled rectifier (SCR) to control large ESD current and EOS current in a small size. In addition, it is another feature to connect a plurality of SCRs in series so that the operation holding voltage of the electrostatic discharge protection device is greater than the power supply voltage. In addition, the present invention is to control the operation start voltage of the electrostatic discharge protection device to effectively prevent the damage of the semiconductor device by ESD and EOS, in particular EOS, the voltage of the voltage is smaller than the power supply voltage by detecting a slow pulse voltage It is still another feature to have a sensing unit for operating the electrostatic discharge protection device only when applied.
Hereinafter, the technical concept of the present invention will be described in detail by illustrating a case in which a discharge unit and a sensing unit have a structure in which two SCRs and two MOS diodes are connected in series. At this time, in the embodiments of the present invention, but for the convenience of description, the discharge unit and the sensing unit has been illustrated that each has a structure in which two SCR and two MOS diodes are connected in series, electrostatic discharge protection to which the technical idea of the present invention is applied The device may have a structure in which a discharge unit and a sensing unit are each connected with two or more SCRs and a MOS diode in series.
In addition, in the following description, the first conductive type and the second conductive type are complementary conductive types. That is, if the first conductivity type is P type, the second conductivity type is N type. Of course, the first conductive type may be N type and the second conductive type may be P type. In the first and second embodiments of the present invention, the first conductive type is P type and the second conductive type is N type.
1 and 2 are diagrams illustrating a hybrid electrostatic discharge protection device according to a first embodiment of the present invention. FIG. 1 is an equivalent circuit, and FIG. 2 is a cross-sectional view.
First, referring to FIG. 1, the hybrid electrostatic discharge protection device according to the first embodiment of the present invention is described in terms of circuits. In this case, the
The SCR constituting the
In addition, the
In addition, the body region of the
As described above, in the
Here, since the operation holding voltage of the
The
The
The
The body region of the MOS diode constituting the
The
An example of a method of designing an operation start voltage of an electrostatic discharge protection device including the operation and
When an abnormal voltage greater than the power supply voltage, that is, an ESD voltage or an EOS voltage is applied to the
At this time, assuming that both the
Next, referring to the structure of the hybrid electrostatic discharge protection device according to the first embodiment of the present invention with reference to Figure 2, the
The
Specifically, the
In the
Here, the
In addition, the hybrid electrostatic discharge protection device according to the first embodiment of the present invention is the
The hybrid electrostatic discharge protection device according to the first embodiment of the present invention having the structure shown in FIGS. 1 and 2 uses the
In addition, since the plurality of
In addition, since the
As a result, the electrostatic discharge protection device according to the first embodiment of the present invention can prevent damage to the semiconductor device by ESD and EOS at the same time, it is possible to improve the operating characteristics of the electrostatic discharge protection device.
Hereinafter, in the second embodiment of the present invention, the configuration of the discharge unit and the sensing unit controls the operation start voltage of the electrostatic discharge protection device by adjusting the connection position of the
3 and 4 illustrate a hybrid electrostatic discharge protection device according to a second embodiment of the present invention. FIG. 3 is an equivalent circuit diagram and FIG. 4 is a sectional view.
3 and 4, the overall configuration is the same as in the first embodiment of the present invention. However, in the first exemplary embodiment of the present invention, the
An example of the method of designing the operation start voltage of the electrostatic discharge protection device according to the operation and
When an abnormal voltage larger than the power supply voltage, that is, an ESD voltage or an EOS voltage is applied to the
At this time, if it is assumed that the operating voltages of the
Comparing the first embodiment and the second embodiment of the present invention, as the configuration of the
The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.
11
13: first well 14: second well
15: third well 16: fourth well
17: first impurity region 18: second impurity region
19: third impurity region 20: fourth impurity region
21: fifth impurity region 22: gate insulating film
23:
24B: second gate 25: first diode
26
101: pad portion 102: ground portion
103:
104: detecting unit 105: internal circuit unit
Claims (19)
A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And
N-th (N is a natural number except 0) of the discharge portion is a sensing unit having a structure connected between the drain and the gate of the transistor in the SCR, a plurality of second diodes connected in series
Hybrid electrostatic discharge protection device comprising a.
And the sensing unit is connected in a forward direction between the drain and the gate of the transistor in the Nth SCR of the discharge unit.
And the second diode includes a transistor having a structure in which a gate and a drain are connected to each other.
And said transistor comprises an NMOS transistor.
And a body region of the transistor is connected to ground.
The detector includes a drain of the first diode connected to the drain of the Nth SCR, a source of the second diode connected to the gate of the Nth SCR, and N (N is a natural number except 0). And a source of the second diode connected to a drain of the N + first second diode.
And the first diode has a structure connected in a forward direction to the transistor.
And said first diode comprises a PN junction diode and said transistor comprises an NMOS transistor.
And a body region of the transistor is connected to ground.
A discharge unit having a structure in which a plurality of the SCRs are connected in series,
The first diode in the SCR is connected between the pad part and the internal circuit part, the last source of the transistor in the SCR is connected to the ground part, and the N (N is a natural number except 0) source of the transistor in the SCR. And a N + 1 th diode in the SCR, the hybrid electrostatic discharge protection device having a structure connected in series.
A discharge unit having one structure connected between the pad unit and the internal circuit unit, the other side connected to the ground unit, and a plurality of the SCRs connected in series; And
The sensing unit having a structure connected between the second impurity region and the first gate of the N-th (N is a natural number except 0) SCR of the discharge unit, and a plurality of diodes are connected in series
Hybrid electrostatic discharge protection device comprising a.
And the sensing unit is connected in a forward direction between the second impurity region and the first gate of the N-th SCR of the discharge unit.
The sensing unit has a hybrid electrostatic discharge protection device having a structure in which a plurality of MOS diodes are connected in series.
The MOS diodes may include a third well of the first conductive type formed on the substrate, a second gate formed on the third well, and a fourth impurity region of the second conductive type formed in the third well on both sides of the second gate. And a fourth impurity region formed on one side of the second gate and the second gate connected thereto.
Further comprising a fifth impurity region of the first conductivity type formed in the third well,
And the fifth impurity region is connected to a ground.
A discharge unit having a structure in which a plurality of the SCRs are connected in series
A first impurity region of the first SCR is connected between the pad portion and the internal circuit portion, a third impurity region of the last SCR is connected to the ground portion, and N (N is a natural number except 0) the SCR. And a third impurity region of the NCR and the first impurity region of the SCR in series.
And the second well is connected to a ground.
And the second conductive type of the first conductive type is a conductive type complementary to each other.
And the first conductive type is P type, and the second conductive type is N type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100017383A KR20110097506A (en) | 2010-02-25 | 2010-02-25 | Hybride protection device for esd and eos |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100017383A KR20110097506A (en) | 2010-02-25 | 2010-02-25 | Hybride protection device for esd and eos |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20110097506A true KR20110097506A (en) | 2011-08-31 |
Family
ID=44932515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100017383A KR20110097506A (en) | 2010-02-25 | 2010-02-25 | Hybride protection device for esd and eos |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20110097506A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101272762B1 (en) * | 2013-02-20 | 2013-06-11 | 주식회사 아나패스 | An electronic apparatus equipped with esd and eos protection circuit unit |
TWI511262B (en) * | 2012-06-26 | 2015-12-01 | Globalfoundries Sg Pte Ltd | Latch-up free esd protection |
CN106158850A (en) * | 2016-08-26 | 2016-11-23 | 华为技术有限公司 | Electrostatic discharge protective equipment and multi-power domain integrated circuit |
CN110993600A (en) * | 2019-12-16 | 2020-04-10 | 广东聚华印刷显示技术有限公司 | ESD protection structure, preparation method and display device |
CN110993600B (en) * | 2019-12-16 | 2024-03-15 | 广东聚华印刷显示技术有限公司 | ESD protection structure, manufacturing method of ESD protection structure and display device |
-
2010
- 2010-02-25 KR KR1020100017383A patent/KR20110097506A/en not_active Application Discontinuation
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI511262B (en) * | 2012-06-26 | 2015-12-01 | Globalfoundries Sg Pte Ltd | Latch-up free esd protection |
KR101272762B1 (en) * | 2013-02-20 | 2013-06-11 | 주식회사 아나패스 | An electronic apparatus equipped with esd and eos protection circuit unit |
CN106158850A (en) * | 2016-08-26 | 2016-11-23 | 华为技术有限公司 | Electrostatic discharge protective equipment and multi-power domain integrated circuit |
CN106158850B (en) * | 2016-08-26 | 2019-06-11 | 华为技术有限公司 | Electrostatic discharge protective equipment and multi-power domain integrated circuit |
US10784679B2 (en) | 2016-08-26 | 2020-09-22 | Huawei Technologies Co., Ltd. | Electrostatic discharge protection apparatus and integrated circuit with multiple power domains |
CN110993600A (en) * | 2019-12-16 | 2020-04-10 | 广东聚华印刷显示技术有限公司 | ESD protection structure, preparation method and display device |
CN110993600B (en) * | 2019-12-16 | 2024-03-15 | 广东聚华印刷显示技术有限公司 | ESD protection structure, manufacturing method of ESD protection structure and display device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108701693B (en) | Embedded PMOS-triggered silicon controlled rectifier for electrostatic discharge protection | |
TWI713189B (en) | Low capacitance transient voltage suppressor | |
CN101290933B (en) | Electrostatic discharge protection device | |
CN107230673B (en) | Electrostatic discharge protection apparatus and method using a protection region | |
JP5242675B2 (en) | ESD protection circuit with reduced trigger voltage | |
US7274546B2 (en) | Apparatus and method for improved triggering and leakage current control of ESD clamping devices | |
TWI469308B (en) | Power-rail esd clamp circuit | |
CN103579224B (en) | ESD protects | |
JP2006319330A (en) | Device for protecting from electrostatic discharge | |
CN102195280B (en) | Electro-static discharge protection circuit and semiconductor device | |
TWI609475B (en) | An esd device for a semiconductor structure | |
CN105655325A (en) | Electrostatic discharge protection circuit, and electrostatic discharge protection structure and manufacturing method thereof | |
US9035363B2 (en) | JFET ESD protection circuit for low voltage applications | |
CN108091647B (en) | Self-biased bi-directional ESD protection circuit | |
US20080198519A1 (en) | Electrostatic discharge protection element having an improved area efficiency | |
KR20110097506A (en) | Hybride protection device for esd and eos | |
WO2016017386A1 (en) | Protection element, protection circuit, and semiconductor integrated circuit | |
JP5532566B2 (en) | Semiconductor device | |
CN102148226A (en) | Semiconductor device | |
US10446539B2 (en) | Electrostatic discharge (ESD) protection device and method for operating an ESD protection device | |
JP2008172216A (en) | Well potential triggered esd protection | |
US8866200B2 (en) | JFET ESD protection circuit for low voltage applications | |
CN108987393B (en) | Bidirectional ESD structure for protecting power integrated circuit output LDMOS device | |
KR20110097505A (en) | Hybride protection device for esd and eos | |
CN101394081A (en) | Electro-static discharge protection design with low capacitance |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |