CN104701316B - Half floating-gate device and its manufacture method of a kind of pair of bathtub construction - Google Patents
Half floating-gate device and its manufacture method of a kind of pair of bathtub construction Download PDFInfo
- Publication number
- CN104701316B CN104701316B CN201510148290.9A CN201510148290A CN104701316B CN 104701316 B CN104701316 B CN 104701316B CN 201510148290 A CN201510148290 A CN 201510148290A CN 104701316 B CN104701316 B CN 104701316B
- Authority
- CN
- China
- Prior art keywords
- lightly doped
- drain
- doping
- region
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses half floating-gate device of a kind of pair of bathtub construction and its manufacture method, including：Active area, Chang Yangqu in Semiconductor substrate；Lightly doped district in active area；Active area both sides are divided into lightly doped drain and source region are lightly doped by the first channel region, and lightly doped drain forms the floating boom of the first insulating barrier with floating boom opening, the first channel region of covering and floating boom opening；Diffusion region below floating boom opening；The second channel region in lightly doped drain；Cover the second insulating barrier and control gate thereon of aforementioned structure, the heavy doping source region of control gate side wall both sides and low energy gap heavy doping drain region.Structure of the present invention uses double grid raceway groove so that device area occupied is smaller, integrated level is higher；The small gap material of drain electrode, interband tunnelling incidence is bigger, improves the read or write speed of half floating-gate device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, more particularly to the half of a kind of pair of bathtub construction are floating
Gate device and its manufacture method.
Background technology
Semiconductor memory is used for various electronic applications.Wherein, non-volatility memorizer (Nonvolatile
Memory, NVM) data can be preserved for a long time in the event of a power failure.Floating transistor (Floating Gate
Transistor, FGT) be the numerous mutation of non-volatility memorizer main flow structure.
FGT and mos field effect transistor (Metal Oxide Semiconductor Field
Effect Transistor, MOSFET) structure is similar, and it can regard individual layer gate dielectric layer in MOSFET as and change into two layers of insulation
" sandwich " grid of an embedded charge storage layer (charge storage layer) in layer (insulator).Wherein, electric charge is deposited
Reservoir is referred to as floating boom due to being surround by insulating barrier.Storage amount of charge in floating boom can adjust transistor threshold electricity
The size of pressure, i.e. " 0 " and " 1 " corresponding to logic.Electric charge in floating boom is injected with two ways：Tunnelling (Fowler-
) and hot carrier in jection Nordheim.Both modes are required for higher operating voltage, and carrier injection efficiency compared with
It is low, therefore there is power consumption and speed issue.
In order to further improve the performance of non-volatility memorizer, it is proposed that half floating transistor (Semi Floating
Gate Transistor, SFGT) concept, i.e., a window is opened at the insulating barrier in drain region and floating transistor, passes through embedded leakage
The plane tunneling field-effect transistor (Tunneling Field Effect Transistor, TFET) in area is realized to floating boom
Discharge and recharge.Half floating transistor uses interband tunneling mechanism, greatly reduces the operating voltage of device, and improve device
Operating rate.
Half floating-gate device can apply to different integrated circuits as a kind of new memory device.It can replace
A part of SRAM (SRAM), improves high speed processor performance；Dynamic RAM can also be applied to
(DRAM) field, improves calculator memory function.
Floating transistor has in fields such as CPU cache (Cache), DRAM and cmos image sensors well should
With prospect, and it is with the obvious advantage.Such as CPU cache, typically now constitutes a memory cell using 6 MOS transistors
(SRAM), integrated level is low, and area occupied is big.The area of about half is forced to give caching occupancy in 28nm Intel XeonCPU,
Greatly waste resource.Therefore, the sram cell area being made up of half floating transistor (SFGT) is smaller, and density is compared to tradition
SRAM can about improve 10 times.Half floating transistor can also be applied to dynamic RAM (DRAM) field.It is substantially single
Member is made up of 1T1C, that is, a transistor adds the structure of an electric capacity.Because its electric capacity needs to keep certain quantity of electric charge
Effectively storage information, it is impossible to persistently reduced the size as MOSFET.Industry generally manufactures special by digging means such as " deep trouths "
The electric capacity of different structure reduces the area of its occupancy, but as storage density is lifted, the technical difficulty and cost of electric capacity processing are big
Amplitude is improved.Therefore, industry always searches for can be used for manufacturing DRAM capacitorless part technology, and half floating transistor structure
Into DRAM traditional DRAM repertoires just can be realized without capacitor, not only cost is greatly reduced, and integrated level is higher, read
Writing rate is faster.
Fig. 1 is a kind of semiconductor memory of planar channeling of prior art, including：Formed in Semiconductor substrate 100
Source region 102 and drain region 103 with Semiconductor substrate opposite dopant type, Semiconductor substrate 100 can be monocrystalline silicon, polysilicon
Or the silicon on insulator.The plane ditch of device is formed with Semiconductor substrate 100, between source region 102 and drain region 103
Road area 116, planar channeling area 116 is the inversion layer that the semiconductor memory is formed when being operated.In source region 102 and drain region
Also form the doped region 111 and doped region 112 of high-dopant concentration in 103 respectively, doped region 111 and doped region 112 and source region and
Drain region has identical doping type.
The first layer insulating 104 is formed with source region 102, channel region 116 and drain region 103, and on drain region 103
The first layer insulating 104 and one floating boom 107 as charge-storage node of formation of floating boom opening 105 are formed, floating boom 107 has
Impurity can diffuse to shape in drain region 103 by floating boom opening 105 in the doping type opposite with drain region 103, and floating boom 107
Into diffusion region 106, so as to form a PN junction diode between floating boom 107 and drain region 103 by floating boom opening 105.
Covering floating boom 107 and the PN-junction diode structure are formed with the second layer insulating 108 in the second layer insulating 108
On, cover and surround the control gate 109 that floating boom 107 is formed with device.Side wall 110 is also formed with the both sides of control gate 109.
The semiconductor memory also includes being used for source region 102, control gate 109, drain region 103, semiconductor lining by what conductive material was formed
The contact 113 for the source region that bottom 100 is connected with outer electrode, the contact 114 of control gate, drain contact 115 and substrate contact
116。
By taking the floating-gate device of N-type half as an example, when control gate 109 applies back bias voltage and drain region 103 applies positive bias, diffusion
Area 106, drain region 103 and the one embedded plane tunneling field-effect transistor (TFET) of formation of drain region doped region 112, are now embedded in
TFET raceway grooves formation P-type channel, and occur interband tunnelling between drain region 103 and drain diffusion regions 112, now electric current is by drain region
Doped region 112 is flowed among half floating boom 107 by raceway groove, the electric charge increase in half floating boom, and the process is write-in logical one；
When control gate 109 applies positive bias and the application of drain region 103 back bias voltage, the PN junction diode that diffusion region 106 is constituted with drain region 103
Positively biased so that the electric charge in the electric charge release stored in half floating boom 107, half floating boom is reduced, the process is write-in logical zero
Process.So electric charge injection and release process is different from conventional floating gate device mode of operation so that the operating voltage of device is significantly
Reduction, storage speed is improved.
But, half floating transistor SFGT of prior art as shown in Figure 1 has following defect：
1st, device is that planar channeling device causes the integration density of chip to reduce, it is necessary to occupy more Substrate Areas.
2nd, embedded tunneling field-effect transistor TFET is planar structure, and chip area increase causes integrated level to reduce；
Under generation tunnelling, leak electricity higher.
3rd, the tunneling field-effect transistor TFET energy gaps of embedded silicon materials are higher causes the incidence of interband tunnelling
It is not high, cause the reduction of device storage speed.
The content of the invention
It is an object of the invention to make up above-mentioned the deficiencies in the prior art, there is provided half floating-gate device of a kind of pair of bathtub construction
And its manufacture method, device area occupied is smaller, and interband tunnelling incidence is bigger, also can effectively prevent element leakage.
To achieve the above object, the present invention provides half floating-gate device of a kind of pair of bathtub construction, and it includes：
Semiconductor substrate with the first doping type；
The Chang Yang areas for device isolation formed in the Semiconductor substrate, Chang Yang forms active area between area；
What is formed in the Semiconductor substrate active area has source region is lightly doped and being lightly doped for second doping type
Drain region；
In first channel region for being lightly doped and being formed between source region and lightly doped drain, for forming flute profile raceway groove,
Source region, the depth of lightly doped drain is lightly doped described in being more than in the depth of first channel region；
The first insulating barrier of source region, lightly doped drain and the formation of flute profile raceway groove is lightly doped described in covering；
The floating boom opening formed above the lightly doped drain at the first insulating barrier of flute profile raceway groove；
Cover the floating boom of first insulating barrier and the first doping type of floating boom opening formation；
The diffusion region with the first doping type formed in the lightly doped drain below the floating boom opening；
The second channel region formed in the lightly doped drain not covered by the floating boom, second channel region
Depth is less than the lightly doped drain depth；
The second insulating barrier that source region, lightly doped drain, floating boom and the second channel region surface are formed is lightly doped described in covering；
Cover the control gate and its side wall of both sides of second of doping type of the second insulating barrier formation；
The heavy doping source region formed in source region and lightly doped drain and heavy doping leakage is lightly doped in the control gate both sides
Area, the heavy doping drain region is small gap material, and second channel region is located between the diffusion region and heavy doping drain region；
And the heavy doping source region, heavy doping drain region, the extraction pole of control gate and Semiconductor substrate.
Further, the small gap material is SiGe.
Further, the first described doping type is N-type, and second of doping type is p-type；Or, described
A kind of doping type is p-type, and second of doping type is N-type.The impurity of the first doping type can be boron, two
Boron fluoride or indium.
Further, first insulating barrier and the second insulating barrier are silica, silicon nitride, silicon oxynitride or high dielectric
Constant material, the floating boom is the polysilicon that the first doping type adulterates, and the control gate is second of doping type doping
Polysilicon, metal or alloy.
Further, the floating boom is connected with the lightly doped drain by the floating boom opening and forms the pole of PN junction two
Pipe, the PN junction diode, the second insulating barrier and control gate constitute the gate control diode using control gate as grid, the grid-control
The anode of diode is connected with the floating boom, and the negative electrode of the gate control diode is connected with the lightly doped drain.
The present invention also provides a kind of manufacture method of half floating-gate device of above-mentioned pair of bathtub construction, and it comprises the following steps：
Step S01, forms the Chang Yang areas for device isolation, field in the Semiconductor substrate with the first doping type
Oxygen forms active area between area；
Step S02, forms the lightly doped district with second of doping type in the active area；
Step S03, by photoetching and etching technics the first channel region of formation in the lightly doped district, for forming groove
Shape raceway groove, the depth of first channel region is more than the depth of the lightly doped district, and is formed in the flute profile raceway groove both sides
Source region and lightly doped drain is lightly doped；
Step S04, in the insulating barrier of semiconductor substrate surface growth regulation one, the first insulating barrier covering is described gently to mix
Miscellaneous source region, lightly doped drain and flute profile raceway groove, are carved above the lightly doped drain at the first insulating barrier of flute profile raceway groove
Erosion forms floating boom opening to expose lightly doped drain；
Step S05, deposits the first conductive layer with the first doping type, and pass through in the semiconductor substrate surface
Chemical wet etching defines the floating boom of device, and the floating boom covers first insulating barrier and floating boom opening, and is opened in the floating boom
The diffusion region with the first doping type is formed in lightly doped drain below mouthful；
Step S06, passes through photoetching and etching technics the second groove of formation in the lightly doped drain not covered by the floating boom
Shape region, the depth of second channel region is less than the lightly doped drain depth；
Step S07, in the insulating barrier of semiconductor substrate surface growth regulation two, the second insulating barrier covering is described gently to mix
Miscellaneous source region, lightly doped drain, floating boom and the second channel region；
Step S08, deposits the second conductive layer, and define device by chemical wet etching on second insulating barrier
Control gate, and form side wall in the control gate both sides；
Step S09, the be lightly doped source region, lightly doped drain covered to the control gate and not controlled grid is carried out second
The ion implanting of doping type, forms heavy doping source region and heavy doping drain region；
Step S10, the heavy doping drain region formation drain recesses that not controlled grid are covered are etched by photoetching and etching technics；
Step S11, grows small gap material, and carry out the ion note of second of doping type in the drain recesses
Enter, form the low energy gap heavy doping drain region with second of doping type；
Step S12, forms the extraction pole of the heavy doping source region, heavy doping drain region, control gate and Semiconductor substrate.
Further, the small gap material is SiGe.
Further, the first described doping type is N-type, and second of doping type is p-type；Or, described
A kind of doping type is p-type, and second of doping type is N-type.
Further, first insulating barrier and the second insulating barrier are silica, silicon nitride, silicon oxynitride or high dielectric
Constant material, the floating boom is the polysilicon that the first doping type adulterates, and the control gate is second of doping type doping
Polysilicon, metal or alloy.
Half floating-gate device and its manufacture method for double bathtub constructions that the present invention is provided, with following technique effect：
1. with flute profile raceway groove, device area occupied is smaller, integrated level is improved, it is adaptable to below 45nm techniques.
2. the tunneling field-effect transistor TFET areas occupied of the flute profile insertion formed by the second channel region are small, reduce device
Part area leaks electricity smaller there is provided the integration density of chip.
3. preferably using SiGe heavy doping drain region, smaller compared with silicon materials energy gap, the incidence of interband tunnelling is bigger,
Improve the read or write speed of half floating-gate device.
4. due to may be such that electric leakage increase using SiGe small gap materials in preferred embodiment, pass through embedded flute profile
TFET can reduce electric leakage simultaneously.
Brief description of the drawings
For that can become apparent from understanding purpose, feature and advantage of the present invention, below with reference to preferable reality of the accompanying drawing to the present invention
Example is applied to be described in detail, wherein：
Fig. 1 is the cross-sectional view of half floating transistor of prior art；
The cross-sectional view of Fig. 2 half floating-gate devices of the present invention；
Fig. 3 is the schematic flow sheet of half floating-gate device manufacture method of the invention；
Fig. 4 to Figure 16 is each step structural representation of half floating-gate device manufacture method of the invention.
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, spy, not according to general scale, and has carried out part to the structure in accompanying drawing
Amplification, deformation and simplified processing, shown structure size do not represent actual size.Meanwhile, accompanying drawing is that the idealization of the present invention is real
The schematic diagram of example is applied, the embodiment shown in the present invention should not be considered limited to the given shape in region shown in figure, but
Including resulting shape, such as deviation etc. caused by manufacturing.For example, etching obtained by curve generally have bending or
Mellow and full the characteristics of, but in an embodiment of the present invention, for convenience of explanation, represented with rectangle.Therefore, should avoid in this, as
Limitation of the invention is understood.
Referring to Fig. 2, half floating-gate device of double bathtub constructions of the present embodiment, it includes：
Semiconductor substrate 200 with the first doping type；
Form active between the Chang Yang areas 201 for device isolation formed in Semiconductor substrate 200, Chang Yang areas 201
Area；
What is formed in the active area of Semiconductor substrate 200 has source region 202 is lightly doped and gently mixing for second doping type
Miscellaneous drain region 203；
The first channel region for being formed between source region 202 and lightly doped drain 203 is being lightly doped, the first channel region is used for
Flute profile raceway groove 204 is formed, its depth, which is more than, is lightly doped source region 202, the depth of lightly doped drain 203；
The first insulating barrier 205 of source region 202, lightly doped drain 203 and the formation of flute profile raceway groove 204, first is lightly doped in covering
The bottom surface of the covering flute profile of insulating barrier 205 raceway groove 204 and side wall；
The floating boom opening 206 formed in the top of lightly doped drain 203 at the first insulating barrier 205 of flute profile raceway groove 204；
The floating boom 207 of the first insulating barrier 205 and the first doping type of the formation of floating boom opening 206 is covered, floating boom 207 is complete
Portion's filling flute profile raceway groove 204；
The diffusion region 208 with the first doping type formed in the lightly doped drain below floating boom opening 206；
The second channel region 209 formed in the lightly doped drain 203 not covered by floating boom 207, for forming insertion
TFET channel regions, the depth of the second channel region 209 is less than the depth of lightly doped drain 203；
Source region 202, lightly doped drain 203, the of the formation of the surface of 207 and second channel region of floating boom 209 is lightly doped in covering
Two insulating barriers 210；
Cover the control gate 211 and its side wall 212 of both sides of second of doping type of the second insulating barrier 210 formation；
The heavy doping source region 213 that is formed in source region 202 and lightly doped drain 203 and again is lightly doped in the both sides of control gate 211
Doped drain, wherein, heavy doping drain region is low energy gap heavy doping drain region 214 ', and the second channel region 209 is located at the He of diffusion region 208
Between low energy gap heavy doping drain region 214 '；
And heavy doping source region 213, low energy gap heavy doping drain region 214 ', the extraction of control gate 211 and Semiconductor substrate 200
Pole：Source electrode 231, drain electrode 232, control gate 233 and underlayer electrode 234.
The floating-gate device of double flute shape half of the present embodiment has flute profile raceway groove, and device area occupied is smaller, and integrated level is improved, and fits
For below 45nm techniques；Embedded flute profile tunneling field-effect transistor TFET areas occupied are formed by the second channel region small, subtracted
Gadget area leaks electricity smaller there is provided the integration density of chip.
Wherein, low-gap semiconductor material, such as SiGe are preferably selected in heavy doping drain region in the present embodiment.Due to using
SiGe etc. is smaller compared with silicon materials energy gap as heavy doping drain region, and the incidence of interband tunnelling is bigger, improves half floating boom device
The read or write speed of part.But, due to may be such that electric leakage increase using small gap materials such as SiGe, pass through the embedding of the present embodiment
Enter flute profile TFET while electric leakage can be reduced.
In the present embodiment, Semiconductor substrate can be the silicon on monocrystalline silicon, polysilicon or insulator.The first of the present embodiment
It is p-type to plant doping type, and second of doping type is N-type；In other embodiments, the first doping type is N-type, second
Doping type is p-type.It is preferred that the impurity of the first doping type can be boron, boron difluoride or indium.
First insulating barrier and the second insulating barrier of the present embodiment can be silica, silicon nitride, silicon oxynitride or Gao Jie
Permittivity material, the polysilicon that floating boom can adulterate for the first doping type, control gate can be mixed for second of doping type
Miscellaneous polysilicon, metal or alloy.
In the present embodiment, floating boom 207 is connected with lightly doped drain 203 by floating boom opening 206 and forms PN junction diode,
Impurity in floating boom 207 can be by floating boom opening 206 by the way that High temperature diffusion is into lightly doped drain 203 and forms the first
The diffusion region 208 of doping type, so that diffusion region 208 forms a PN junction diode with lightly doped drain 203.The pole of PN junction two
Pipe, the second insulating barrier and control gate constitute the gate control diode using control gate as grid, the anode of gate control diode with it is described
Floating boom is connected, and the negative electrode of gate control diode is connected with the lightly doped drain.
It please ask to read Fig. 3 and combine and refer to Fig. 4 to 16, the manufacture method embodiment of above-mentioned half floating-gate device includes following step
Suddenly：
Step S01, as shown in figure 4, passing through shallow trench isolation STI technique in the Semiconductor substrate 200 adulterated with p-type
Formed and active area is formed between the Chang Yang areas 201 for device isolation, Chang Yang areas 201, wherein Semiconductor substrate can be monocrystalline
Silicon on silicon, polysilicon or insulator；
Step S02, as shown in figure 5, by photoetching process and ion implantation technology in the active area of Semiconductor substrate 200
Form the lightly doped district with n-type doping；
Specifically, this step is included in the surface of Semiconductor substrate 200 and sequentially forms one layer of hard mask layer and photoresist layer；Through
Photoetching and etching technics, form in photoresist layer and hard mask layer and source region and lightly doped drain pattern are lightly doped；With photoresist
It is mask with hard mask layer, n-type doping ion is injected into active area, so as to forms the source region that N-type is lightly doped in active area
202 and lightly doped drain 203；Source region 202 that N-type is lightly doped and lightly doped drain 203 are respectively close to Semiconductor substrate both sides
Chang Yang areas 201；Finally, photoresist layer and hard mask layer are removed；
Step S03, as shown in fig. 6, in 200 surface deposition of Semiconductor substrate, one layer of hard mask layer and photoresist, by covering
Masterplate etches away exposed hard mask layer, and the side being combined by mask of hard mask layer by wet etching and dry etching
Method, etches the first channel region of the substrate formation groove exposed in lightly doped district, for forming flute profile raceway groove 204, and
Two parts are formed in the both sides of flute profile raceway groove 204, source region 202 and lightly doped drain 203 is lightly doped as device, wherein, groove
The depth of shape raceway groove have to be larger than the depth of lightly doped district；
Step S04, as shown in fig. 7, in stripping photoresist and after etching remaining hard mask layer, in Semiconductor substrate 200
Source region 202, lightly doped drain 203 and flute profile raceway groove is lightly doped in the first insulating barrier of superficial growth 205, the first insulating barrier 205 covering
204, then, as shown in figure 8, etching shape at the first insulating barrier 205 of flute profile raceway groove 204 in the top of lightly doped drain 203
Into floating boom opening 206 to expose lightly doped drain 203, it is specifically included on the first insulating barrier 205 and deposits one layer of photoresist simultaneously
Defined by photoetching, developing process, the position of floating boom opening, first exposed is then fallen by mask etching of photoresist exhausted
Edge layer 205, to form floating boom opening 206, is finally peeled away photoresist；Wherein, the first insulating barrier can be silica, nitridation
The insulating materials of the high-ks such as silicon, silicon oxynitride, thickness is 1-40 nanometers；
Step S05, as shown in figure 9, there is the polysilicon that p-type is adulterated as first in the surface deposition of Semiconductor substrate 200
Conductive layer, and define by the conductive layer of chemical wet etching first floating boom 207 of device, the covering He of the first insulating barrier 205 of floating boom 207
Floating boom opening 206, and diffusion region 208 is formed in the lightly doped drain below floating boom opening 206, it specifically includes：Deposit
Polysilicon fills whole flute profile raceway groove 204 and floating boom opening 206, and photoresist is then deposited on the polysilicon and passes through photoetching process
The position of floating boom is defined, then falls by mask etching of photoresist the floating boom 207 of unnecessary polysilicon formation device, floating boom 207
Middle impurity can form p type diffusion region 208 to lightly doped drain 203 by the High temperature diffusion of floating boom opening 206, such as Fig. 9 institutes
Show, and a PN junction diode is formed between floating boom 207 and lightly doped drain 203 by floating boom opening 206；
Step S06, as shown in Figure 10, continues to click on one layer of hard mask and photoresist in semiconductor substrate surface, passes through light
The second channel region 209 defined with etching technics in the lightly doped drain exposed not covered by floating boom 207 is carved, its
In, the depth of the second channel region 209 is necessarily less than the depth of lightly doped district (lightly doped drain herein), for forming insertion
TFET channel regions；
Step S07, as shown in figure 11, in the second insulating barrier of superficial growth 210 of Semiconductor substrate 200, the second insulating barrier 210
Source region 202, lightly doped drain 203, the channel region 209 of floating boom 207 and second is lightly doped in covering；Wherein, the second insulating barrier can be with
It is the insulating materials of the high-ks such as silica, silicon nitride, silicon oxynitride, thickness is 1-40 nanometers；
Step S08, as shown in figure 12, the polysilicon that n-type doping is deposited on the second insulating barrier 210 are conductive as second
Layer, and the control gate 211 of device is defined by chemical wet etching, the polysilicon of exposure outside is then etched away, wherein, control gate
211 should be greater than floating boom 207 in orientation, are completely covered and surround floating boom 207, and form side in the both sides of control gate 211
Wall 212；Specifically, the 3rd insulating barrier is deposited on semiconductor substrate 200, and one layer of photoresist is deposited simultaneously on the 3rd insulating barrier
By photoetching process formation figure, the 3rd insulating barrier exposed is then etched away, and continue to etch away the second layer exposed
Remaining 3rd insulating barrier forms side wall 212 in the both sides of control gate 211 after insulating barrier, etching, as shown in figure 13, wherein, the 3rd
Insulating barrier can be silica or silicon nitride；
Step S09, as shown in figure 13, what control gate 211 and not controlled grid were covered is lightly doped source region 202, is lightly doped
Drain region 203 carries out the ion implanting of n-type doping, and the heavy doping of source region 202 and the formation of lightly doped drain 203 high concentration is being lightly doped
Source region 213 and heavy doping drain region 214；
Step S10, as shown in figure 14, deposits one layer of silicon nitride hard mask and photoresist having formed body structure surface, leads to
Photoetching and etching technics are crossed, the heavy doping drain region that not controlled grid 211 are covered is etched away, drain recesses 220 are formed；
Step S11, as shown in figure 15, by selective epitaxial process in drain recesses 220, grows SiGe, with laggard
The ion implanting of row n-type doping, forms low energy gap heavy doping drain region 214 '；
Step S12, as shown in figure 16, is leaked in heavy doping source region, heavy doping respectively with conductive material by metallization process
The extraction pole that area, control gate and Semiconductor substrate formation are connected with external electrode, i.e. source electrode 231, drain electrode 232, control gate 233
With underlayer electrode 234.
Although the present invention is disclosed as above with preferred embodiment, the right embodiment illustrated only for the purposes of explanation and
, the present invention is not limited to, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry change and retouching, the protection domain that the present invention is advocated should be to be defined described in claims.
Claims (10)
1. half floating-gate device of a kind of pair of bathtub construction, it is characterised in that it includes：
Semiconductor substrate with the first doping type；
The Chang Yang areas for device isolation formed in the Semiconductor substrate, Chang Yang forms active area between area；
Formed in the Semiconductor substrate active area there is second doping type source region, lightly doped drain is lightly doped；
It is described for forming flute profile raceway groove in first channel region for being lightly doped and being formed between source region and lightly doped drain
Source region, the depth of lightly doped drain is lightly doped described in being more than in the depth of first channel region；
The first insulating barrier of source region, lightly doped drain and the formation of flute profile raceway groove is lightly doped described in covering；
The floating boom opening formed above the lightly doped drain at the first insulating barrier of flute profile raceway groove；
Cover the floating boom of first insulating barrier and the first doping type of floating boom opening formation；
The diffusion region with the first doping type formed in the lightly doped drain below the floating boom opening；
The second channel region formed in the lightly doped drain not covered by the floating boom, the depth of second channel region
Less than the lightly doped drain depth；
The second insulating barrier that source region, lightly doped drain, floating boom and the second channel region surface are formed is lightly doped described in covering；
Cover the control gate and its side wall of both sides of second of doping type of the second insulating barrier formation；
The heavy doping source region formed in source region and lightly doped drain and heavy doping drain region, institute is lightly doped in the control gate both sides
Heavy doping drain region is stated for small gap material, second channel region is located between the diffusion region and heavy doping drain region；
And the heavy doping source region, heavy doping drain region, the extraction pole of control gate and Semiconductor substrate.
2. half floating-gate device according to claim 1, it is characterised in that：The small gap material is SiGe.
3. half floating-gate device according to claim 2, it is characterised in that：First insulating barrier and the second insulating barrier are two
Silica and/or high dielectric constant material, the floating boom are the polysilicon that the first doping type adulterates, and the control gate is the
Polysilicon, the metal or alloy of two kinds of doping type doping.
4. half floating-gate device according to claim 2, it is characterised in that：The floating boom by the floating boom opening with it is described
Lightly doped drain is connected and forms PN junction diode, and the PN junction diode, the second insulating barrier and control gate are constituted with control gate
As the gate control diode of grid, the anode of the gate control diode is connected with the floating boom, the moon of the gate control diode
Pole is connected with the lightly doped drain.
5. half floating-gate device according to any one of Claims 1-4, it is characterised in that：The first described doping type is N
Type, second of doping type is p-type；Or, the first described doping type is p-type, and second of doping type is N
Type.
6. the manufacture method of half floating-gate device of double bathtub constructions described in a kind of claim 1, it is characterised in that it includes following
Step：
Step S01, forms the Chang Yang areas for device isolation, Chang Yangqu in the Semiconductor substrate with the first doping type
Between form active area；
Step S02, forms the lightly doped district with second of doping type in the active area；
Step S03, by photoetching and etching technics the first channel region of formation in the lightly doped district, for forming trough gutter
Road, the depth of first channel region is more than the depth of the lightly doped district, and is formed and gently mix in the flute profile raceway groove both sides
Miscellaneous source region and lightly doped drain；
Step S04, in the insulating barrier of semiconductor substrate surface growth regulation one, first insulating barrier covers the lightly-doped source
Area, lightly doped drain and flute profile raceway groove, shape is etched above the lightly doped drain at the first insulating barrier of flute profile raceway groove
Into floating boom opening to expose lightly doped drain；
Step S05, deposits the first conductive layer with the first doping type, and pass through photoetching in the semiconductor substrate surface
Etching defines the floating boom of device, and the floating boom covers first insulating barrier and floating boom opening, and under the floating boom opening
The diffusion region with the first doping type is formed in the lightly doped drain of side；
Step S06, passes through the second flute profile area of photoetching and etching technics formation in the lightly doped drain not covered by the floating boom
Domain, the depth of second channel region is less than the lightly doped drain depth；
Step S07, in the insulating barrier of semiconductor substrate surface growth regulation two, second insulating barrier covers the lightly-doped source
Area, lightly doped drain, floating boom and the second channel region；
Step S08, deposits the second conductive layer on second insulating barrier, and defines by chemical wet etching the control of device
Grid, and form side wall in the control gate both sides；
Step S09, the be lightly doped source region, lightly doped drain covered to the control gate and not controlled grid carries out second of doping
The ion implanting of type, forms heavy doping source region and heavy doping drain region；
Step S10, the heavy doping drain region formation drain recesses that not controlled grid are covered are etched by photoetching and etching technics；
Step S11, grows small gap material, and carry out the ion implanting of second of doping type, shape in the drain recesses
Into the low energy gap heavy doping drain region with second of doping type；
Step S12, forms the extraction pole of the heavy doping source region, heavy doping drain region, control gate and Semiconductor substrate.
7. half floating-gate device manufacture method according to claim 6, it is characterised in that：The small gap material is SiGe.
8. half floating-gate device manufacture method according to claim 7, it is characterised in that：First insulating barrier and second exhausted
Edge layer is silica and/or high dielectric constant material.
9. half floating-gate device manufacture method according to claim 7, it is characterised in that：The floating boom is the first doping class
The polysilicon of type doping, the control gate is polysilicon, the metal or alloy of second of doping type doping.
10. the half floating-gate device manufacture method according to any one of claim 6 to 9, it is characterised in that：It is described the first mix
Miscellany type is N-type, and second of doping type is p-type；Or, the first described doping type is p-type, is mixed for described second
Miscellany type is N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510148290.9A CN104701316B (en) | 2015-03-31 | 2015-03-31 | Half floating-gate device and its manufacture method of a kind of pair of bathtub construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510148290.9A CN104701316B (en) | 2015-03-31 | 2015-03-31 | Half floating-gate device and its manufacture method of a kind of pair of bathtub construction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104701316A CN104701316A (en) | 2015-06-10 |
| CN104701316B true CN104701316B (en) | 2017-09-29 |
Family
ID=53348266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510148290.9A Active CN104701316B (en) | 2015-03-31 | 2015-03-31 | Half floating-gate device and its manufacture method of a kind of pair of bathtub construction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104701316B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328718A (en) * | 2016-11-04 | 2017-01-11 | 四川洪芯微科技有限公司 | Mesa diode |
| CN108899277A (en) * | 2018-06-27 | 2018-11-27 | 中国电子科技集团公司第十三研究所 | The preparation method and Schottky diode of epitaxial wafer |
| CN112399106B (en) * | 2019-08-12 | 2023-04-18 | 天津大学青岛海洋技术研究院 | 4T pixel structure based on semi-floating gate |
| CN111477627B (en) * | 2020-04-27 | 2022-10-11 | 复旦大学 | Semi-floating gate memory based on double-floating gate material and preparation method thereof |
| CN111564443B (en) * | 2020-05-13 | 2023-05-19 | 复旦大学 | High-integration-density semi-floating gate memory and preparation method thereof |
| CN111933651B (en) * | 2020-08-13 | 2024-01-30 | 锐芯微电子股份有限公司 | Pixel structure of image sensor and forming method thereof |
| CN113948394A (en) * | 2021-09-18 | 2022-01-18 | 上海华力集成电路制造有限公司 | Manufacturing method of semi-floating gate device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103247626A (en) * | 2013-05-02 | 2013-08-14 | 复旦大学 | Semi-floating gate device and manufacturing method thereof |
| CN103632942A (en) * | 2012-08-24 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | SONOS device and LDMOS device integration method in CMOS process |
| CN203910798U (en) * | 2014-04-01 | 2014-10-29 | 苏州东微半导体有限公司 | U-shaped channel half-floating gate memory |
-
2015
- 2015-03-31 CN CN201510148290.9A patent/CN104701316B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632942A (en) * | 2012-08-24 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | SONOS device and LDMOS device integration method in CMOS process |
| CN103247626A (en) * | 2013-05-02 | 2013-08-14 | 复旦大学 | Semi-floating gate device and manufacturing method thereof |
| CN203910798U (en) * | 2014-04-01 | 2014-10-29 | 苏州东微半导体有限公司 | U-shaped channel half-floating gate memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104701316A (en) | 2015-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104701316B (en) | Half floating-gate device and its manufacture method of a kind of pair of bathtub construction | |
| US9748406B2 (en) | Semi-floating-gate device and its manufacturing method | |
| US8680588B2 (en) | Field effect transistor with buried gate pattern | |
| CN104882447B (en) | A kind of half floating-gate device and manufacturing method of drain region insertion inversion layer | |
| CN103887313B (en) | A kind of half floating-gate device and preparation method thereof | |
| CN104103640B (en) | Semiconductor device with U-shaped channel and manufacturing method thereof | |
| CN104103678A (en) | U-shaped trench type semiconductor device and manufacture method thereof | |
| CN106601750B (en) | Semi-floating gate memory device with U-shaped groove and preparation method | |
| CN103915439A (en) | Semiconductor device and manufacturing method thereof | |
| KR100871983B1 (en) | Semiconductor memory device and method for fabricating the same | |
| CN107958907B (en) | Semi-floating gate memory device with U-shaped groove and manufacturing method thereof | |
| CN104124248B (en) | NOR-type flash memory unit for lifting common source region and preparation method thereof | |
| JP3019154B2 (en) | Nonvolatile semiconductor memory device and semiconductor integrated circuit device | |
| CN104701263B (en) | A kind of manufacture method of half floating-gate device | |
| CN104638018B (en) | A kind of half floating-gate device and preparation method thereof | |
| US11894447B2 (en) | Method for manufacturing a semiconductor device with reduced variation of the impurity concentration near the surface of the semiconductor film | |
| JP2011134981A (en) | Non-volatile semiconductor storage device and method of manufacturing the same | |
| CN114335182A (en) | Embedded flash memory, semiconductor device structure and preparation method thereof | |
| CN103594519A (en) | Tunneling field effect floating gate transistor and manufacturing method thereof | |
| TW201519447A (en) | Recessed channel access transistor device and fabrication method thereof | |
| TWI696273B (en) | Flash memory with assistant gate and method of fabricating the same | |
| CN104425500B (en) | SONOS non-volatility memorizers and its manufacturing method | |
| CN106783572B (en) | The forming method of semiconductor structure | |
| CN110957325B (en) | Semiconductor memory and method of manufacturing the same | |
| CN110164768B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |