CN103632942A - SONOS device and LDMOS device integration method in CMOS process - Google Patents

SONOS device and LDMOS device integration method in CMOS process Download PDF

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CN103632942A
CN103632942A CN201210306805.XA CN201210306805A CN103632942A CN 103632942 A CN103632942 A CN 103632942A CN 201210306805 A CN201210306805 A CN 201210306805A CN 103632942 A CN103632942 A CN 103632942A
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sonos
layer
type well
ldmos device
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CN103632942B (en
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陈广龙
谭颖
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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Abstract

The invention discloses an SONOS device and LDMOS device integration method in a CMOS process. The method comprises the steps of forming a shallow trench isolation structure on a silicon substrate; forming a well region; carrying out threshold voltage adjustment injection; forming a first pre-oxidation layer; removing the first pre-oxidation layer of an SONOS device forming region; depositing an ONO layer; etching the ONO layer and forming a grid dielectric layer of an SONOS device and an LDMOS device; forming a grid oxidation layer of a CMOS logic device; carrying out polysilicon deposition; etching polysilicon and forming grid polysilicon of the SONOS device, the LDMOS device and the CMOS logic device; carrying out lightly doped source drain injection; forming a side wall; and carrying out source drain injection. According to the invention, the layer number of a photolithography mask is reduced, and the manufacturing cost of a chip is reduced.

Description

The method of integrated SONOS device and LDMOS device in CMOS technique
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of method of integrated SONOS device and LDMOS device in CMOS technique.
Background technology
Non-volatile line storage (NVM) technology is sent out sexual development so far, mainly contain floating boom (floating gate) technology, dividing potential drop grid (split gate) technology and SONOS(Silicon-Oxide-Nitride-Oxide-Silicon, silicon oxide nitride oxide silicon) technology.The advantages such as SONOS technology is widely used, and has operating voltage low, and speed is fast, and capacity is large.High speed development along with development of Mobile Internet technology, especially the semi-conductor market that the mobile terminal of take is staple market application emerges fast, wherein the emerging semiconductor of representative is to take the touch-screen control microprocessor that has been application integration, CODE memory device, and high tension apparatus is as LDMOS device etc.This just needs high tension apparatus and embedded memory device to be integrated in identical platform.Memory and high tension apparatus are embedded into standard CMOS logic process and need to newly increase 10 layers of above reticle, Design and manufacture cost is all very high.
As shown in Figure 1, the structural representation of existing N-type SONOS device; Existing N-type SONOS device: comprise P type well region 101, on described P type well region 101, be formed with successively the first silicon oxide layer 103, the second silicon nitride layer 104 and the 3rd silica 105, by described the first silicon oxide layer 103, the second silicon nitride layer 104 and the 3rd silica 105, form ONO layer, the tunnel oxide that described the first silicon oxide layer 103 is device, described the second silicon nitride layer 104 is data storage medium layer, and described the 3rd silica 105 is for controlling oxide layer.Above described ONO layer, be formed with grid polycrystalline silicon 106.In the side of described grid polycrystalline silicon 106, be formed with side wall 107, described ONO layer also extends to the below of described side wall 107.The described P type well region 101 that described grid polycrystalline silicon 106 covers is channel region, is formed with threshold voltage and adjusts injection region 102 in described channel region, and this threshold voltage is adjusted 102 Wei Yi N-districts, injection region, for adjusting the threshold voltage of device.Described P type well region 101 in described grid polycrystalline silicon 106 both sides is formed with symmetrically arranged lightly-doped source and leaks (LDD) district 108 and source-drain area 109, the edge autoregistration of described lightly-doped source drain region 108 and described grid polycrystalline silicon 106, the edge autoregistration of described source-drain area 109 and described side wall 107.When device carries out write operation, at described grid polycrystalline silicon 106 upper offset positive voltage VPOS, at described source-drain area 109 upper offset negative voltage VNEG, also negative voltage VNEG setovers on described P type well region 101, so just formed from described grid polycrystalline silicon 106 to the tunnelling voltage difference (VPOS-VNEG) described channel region, thereby the FN that electronics occurs wears then, the electronics of described channel region is entered into described the second silicon nitride layer 104 and is caught by the trap of described the second silicon nitride layer 104 through described the first silicon oxide layer 103 by F-N tunnelling mode.For existing P type SONOS device, the doping in each region is contrary with existing N-type SONOS device, and if channel region is N-type, source-drain area is P type.
Extra 3～4 layer photoetching layers that increase of CMOS technique needs that existing SONOS device are embedded into standard, as comprise: tunnel oxide definition lithography layer, lithography layer is injected in the adjustment of storage tube raceway groove, storage tube ono dielectric film definition lithography layer, and storage tube LDD injects lithography layer etc.
As shown in Figure 2 A, be the structural representation of existing asymmetric N-type LDMOS device; Existing N-type LDMOS device comprises: silicon substrate 201, in described silicon substrate 201, be formed with fleet plough groove isolation structure, and by the shallow trench field oxygen 203 being filled in shallow trench, isolate active area.In described silicon substrate 201, be formed with N-type well region (NWELL) 202; In described N-type well region 202, be formed with P type well region (PWELL) 204, on the surface of described silicon substrate 201, be formed with successively gate dielectric layer 205 as gate oxide and grid polycrystalline silicon 206, the described P type well region 204 being covered by described grid polycrystalline silicon 206 forms channel region.207 Wei Yi N+ districts, source region, are formed with in described P type well region 204; 208 Wei Yi N+ districts, drain region, be formed at described N-type well region 202, between described drain region 208 and described channel region, isolation has a shallow trench field oxygen 203, this shallow trench field oxygen 203 and the described channel region segment distance of being also separated by, and described grid polycrystalline silicon 206 extends to the top of this shallow trench field oxygen 203; By described channel region, to the described N-type well region 202 described drain region 208, formed the drift region (N-Drift) of device.At described P type well region 204, be formed with back-gate electrode draw-out area 209, these 309 Wei Yi N+ districts, back-gate electrode draw-out area.Above described source region 207, described drain region 208, described grid polycrystalline silicon 206 and described back-gate electrode draw-out area 209, be formed with respectively Metal Contact 210 and draw respectively source electrode, drain electrode, grid and back-gate electrode.
As shown in Figure 2 B, be the structural representation of existing asymmetric P type LDMOS device; Existing P type LDMOS device is formed in the dark N-type well region (DNWELL) 301 on silicon substrate, in described silicon substrate, is formed with fleet plough groove isolation structure, by the shallow trench field oxygen 303 being filled in shallow trench, isolates active area.In described dark N-type well region 301, be formed with P type well region 302; In described P type well region 302, be formed with N-type well region 304, on the surface of described silicon substrate, be formed with successively gate dielectric layer 305 as gate oxide and grid polycrystalline silicon 306, the described N-type well region 304 being covered by described grid polycrystalline silicon 306 forms channel region.307 Wei Yi P+ districts, source region, are formed with in described N-type well region 304; 308 Wei Yi P+ districts, drain region, be formed at described P type well region 302, between described drain region 308 and described channel region, isolation has a shallow trench field oxygen 303, this shallow trench field oxygen 303 and the described channel region segment distance of being also separated by, and described grid polycrystalline silicon 306 extends to the top of this shallow trench field oxygen 303; By described channel region, to the described P type well region 302 described drain region 308, formed the drift region (P-Drift) of device.At the NP of institute type well region 304, be formed with back-gate electrode draw-out area 309, these 309 Wei Yi N+ districts, back-gate electrode draw-out area.Above described source region 307, described drain region 308, described grid polycrystalline silicon 306 and described back-gate electrode draw-out area 309, be formed with respectively Metal Contact 310 and draw respectively source electrode, drain electrode, grid and back-gate electrode.
The feature of LDMOS device is formed with thicker gate dielectric layer for bearing high pressure as added high pressure on grid below grid polycrystalline silicon, and gate dielectric layer need to be by lithographic definition and etching to form.In addition, LDMOS device also need to form drift region for bearing the high pressure of the source of device between leaking, and drift region comprises P type drift region (P-Drift) and N-type drift region (N-Drift) two kinds, also needs to form by two layer photoetchings.In addition, LDMOS device also need two to three layer photoetching techniques to form high-pressure trap areas (HVWELL) to realize the high pressure of device withstand voltage, as the N-type well region (NWELL) of high pressure, P type well region (PWELL) and deeply N-type well region (DNWELL).Like this, in prior art, needing to increase by 6～7 layer photoetching techniques realizes LDMOS device is embedded in the CMOS technique of standard.
Therefore in prior art, if the LDMOS device of SONOS device and high pressure is embedded in standard CMOS process, need extra 9～11 layer photoetching versions that increase compared with standard CMOS process, this makes technique and manufacturing cost all higher.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method of integrated SONOS device and LDMOS device in CMOS technique, can greatly reduce the number of plies of reticle, greatly reduces the manufacturing cost of chip.
For solving the problems of the technologies described above, in CMOS technique provided by the invention, the method for integrated SONOS device and LDMOS device, for integrated SONOS device, LDMOS device and CMOS logical device on same silicon substrate, comprises the steps:
Step 1, on described silicon substrate, form fleet plough groove isolation structure, by described fleet plough groove isolation structure, isolate active area; Form well region; Carry out threshold voltage adjustment injection.
Step 2, the described surface of silicon after step 1 form the first pre-oxygen layer.
Step 3, employing chemical wet etching technique are carried out etching to the described first pre-oxygen layer, the described first pre-oxygen layer of described SONOS nmosfet formation region is removed and exposed described surface of silicon, the described first pre-oxygen layer outside described SONOS nmosfet formation region is retained.
Step 4, in described silicon substrate front deposit the first silicon oxide layer, the second silicon nitride layer and the 3rd silicon oxide layer successively, by described the first silicon oxide layer, described the second silicon nitride layer and described the 3rd silicon oxide layer, form an ONO layer, described ONO layer is covered in the described surface of silicon of described SONOS nmosfet formation region and the described first pre-oxygen layer surface outside described SONOS nmosfet formation region.
Step 5, employing chemical wet etching technique are carried out etching to described ONO layer, form the gate dielectric layer of described SONOS device and described LDMOS device simultaneously, the described ONO layer that the gate dielectric layer of described SONOS device is positioned at described SONOS nmosfet formation region after by etching forms, and the described first pre-oxygen layer and described ONO stacked adding that the gate dielectric layer of described LDMOS device is positioned at described LDMOS nmosfet formation region after by etching form.
Step 6, form the gate oxide of described CMOS logical device.
Step 7, carry out polysilicon deposit, adopt chemical wet etching technique to carry out to described polysilicon the grid polycrystalline silicon that etching forms described SONOS device, described LDMOS device and described CMOS logical device simultaneously.
Step 8, carry out lightly-doped source and leak and in the described silicon substrate be infused in grid polycrystalline silicon both sides described in each, to form lightly-doped source and leak injection region; Described in each, the side of grid polycrystalline silicon forms side wall; Carry out source and leak source region and the drain region of injecting formation described SONOS device, described LDMOS device and described CMOS logical device.
Further improving is that the thickness of the described first pre-oxygen layer is 100 dust～150 dusts; The thickness of described the first silicon oxide layer is 18 dust～24 dusts; The thickness of described the second silicon nitride layer is 80 dust～120 dusts; The thickness of described the 3rd silicon oxide layer is 40 dust～80 dusts.
Further improving is that the thickness of the gate dielectric layer of described LDMOS device is 200 dust～300 dusts.
Further improving is that described LDMOS device comprises channel region and drift region; Described channel region and described drift region are adjacent, and the grid polycrystalline silicon of described LDMOS device is covered in top, described channel region for controlling the formation of raceway groove; For N-type LDMOS device, channel region is comprised of P type well region, and drift region is comprised of N-type well region; For P type LDMOS device, channel region is comprised of N-type well region, and drift region is comprised of P type well region; Described P type well region and described N-type well region form in step 1.
Further improve and be, for symmetric form LDMOS device, described drift region comprises two, the both sides that are arranged on described channel region of two drift region symmetries, described in each, in drift region, be formed with respectively leakage injection region, ，Liang Ge source, leakage injection region, a source and be symmetrical structure and respectively as source region or the drain region of described symmetric form LDMOS device.For asymmetric LDMOS device, described drift region comprises one, described drift region is arranged on described channel region near drain terminal one side, described drain region is formed in described drift region, described source region is formed in described channel region, and the grid polycrystalline silicon edge autoregistration of described source region and top, described channel region.
Further improve and be, the grid polycrystalline silicon of described LDMOS device is withstand voltage is 12V～16V.
Further improving is that the Punchthrough voltage of described LDMOS device is 12V～16V.
Further improving is that described SONOS device includes channel region; For N-type SONOS device, described channel region is comprised of P type well region; For P type SONOS device, described channel region is comprised of N-type well region; Described P type well region and described N-type well region form in step 1.
Further improvement is, described CMOS logical device comprises PMOS logical device and NMOS logical device, and described PMOS logical device and described NMOS logical device all include channel region; For NMOS logical device, described channel region is comprised of P type well region; For PMOS logical device, described channel region is comprised of N-type well region; Described P type well region and described N-type well region form in step 1.
The gate dielectric layer of the present invention by LDMOS device is set to the structure that the first pre-oxygen layer and ONO layer are formed by stacking, can realize the gate dielectric layer that adopts same reticle while chemical wet etching to form SONOS device and LDMOS device, add that ONO layer need to adopt a reticle to define SONOS device position while forming, and needs 2 reticle just can prepare the gate dielectric layer of SONOS device and LDMOS device altogether; And the formation of LDMOS device and the needed well region of SONOS device and threshold voltage adjustment injection region can be carried out with well region and one of the injection region of threshold voltage adjustment of CMOS logical device, the grid polycrystalline silicon of LDMOS device and SONOS device and the formation of source-drain area also can be carried out with grid polycrystalline silicon and one of the source-drain area of CMOS logical device, therefore can greatly reduce, form the number of plies that forms separately the required reticle of LDMOS device and the needed well region of SONOS device, threshold voltage adjustment injection region, grid polycrystalline silicon and source-drain area; Above-mentioned advantage makes the present invention only need on the basis of standard CMOS process, increase by 3～4 layer photoetching versions just to realize SONOS device and LDMOS device are embedded in CMOS technique, can greatly reduce the number of plies of reticle, thereby also can greatly reduce the manufacturing cost of chip.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing N-type SONOS device;
Fig. 2 A is the structural representation of existing asymmetric N-type LDMOS device;
Fig. 2 B is the structural representation of existing asymmetric P type LDMOS device;
Fig. 3 is the flow chart of embodiment of the present invention method;
Fig. 4 A-Fig. 4 I is the device architecture schematic diagram in each step of embodiment of the present invention method.
Embodiment
If Fig. 3 is the flow chart of embodiment of the present invention method; As shown in Fig. 4 A to Fig. 4 I, it is the device architecture schematic diagram in each step of embodiment of the present invention method.In embodiment of the present invention CMOS technique, the method for integrated SONOS device and LDMOS device, for integrated SONOS device, LDMOS device and CMOS logical device on same silicon substrate, comprises the steps:
Step 1, as shown in Figure 4 A forms fleet plough groove isolation structure 3 on described silicon substrate, and the shallow trench field oxygen being filled in shallow trench by described fleet plough groove isolation structure 3 isolates active area; Form well region; Carry out threshold voltage adjustment injection.Described well region comprises dark N-type trap 1, P type well region 2, N-type well region 4.
Described LDMOS device comprises channel region and drift region; Described channel region and described drift region are adjacent, in described channel region, through described threshold voltage adjustment, inject and are formed with threshold voltage adjustment injection region.For N-type LDMOS device, channel region is comprised of P type well region 2, and drift region is comprised of N-type well region 4; For P type LDMOS device, channel region is comprised of N-type well region 4, and drift region is comprised of P type well region 2.For symmetric form LDMOS device, described drift region comprises two, the both sides that are arranged on described channel region of two drift region symmetries; For asymmetric LDMOS device, described drift region comprises one, and described drift region is arranged on described channel region near drain terminal one side.In Fig. 4 A to Fig. 4 I, illustrated the cross-section structure in the formation region of an asymmetric P type LDMOS device.The cross-section structure of asymmetric N-type LDMOS device and the P type of symmetric form and N-type LDMOS device also can make reference with the cross-section structure in the formation region of asymmetric P type LDMOS device, and the doping type of the channel region of asymmetric N-type LDMOS device and drift region and follow-up leakage doped region, source is done to phase inverse transformation; The cross-section structure of the LDMOS device of symmetric form only need on the LDMOS of symmetric form device basis, in source region, one side also increases a symmetrical drift region.
Described SONOS device includes channel region, in described channel region, through described threshold voltage adjustment, injects and is formed with threshold voltage adjustment injection region.For N-type SONOS device, described channel region is comprised of P type well region 2; For P type SONOS device, described channel region is comprised of N-type well region 4.In Fig. 4 A to Fig. 4 I, illustrated the cross-section structure in the formation region of a P type SONOS device; It is reference that the cross-section structure in the formation region of N-type SONOS device also can be take the cross-section structure in formation region of P type SONOS device, and the doping type of the channel region of N-type SONOS device and follow-up leakage doped region, source is done to phase inverse transformation.
Described CMOS logical device comprises PMOS logical device and NMOS logical device, and described PMOS logical device and described NMOS logical device all include channel region, in described channel region, through described threshold voltage adjustment, injects and is formed with threshold voltage adjustment injection region.For NMOS logical device, described channel region is comprised of P type well region 2; For PMOS logical device, described channel region is comprised of N-type well region 4.In Fig. 4 A to Fig. 4 I, illustrated the cross-section structure in the formation region of a NMOS logical device; It is reference that the cross-section structure in the formation region of PMOS logical device also can be take the cross-section structure in formation region of NMOS logical device, and the doping type of the channel region of PMOS logical device and follow-up leakage doped region, source is done to phase inverse transformation.
Can find out that step 1 forms together with described LDMOS device, described SONOS device can being adopted separately respectively to a reticle with needed dark N-type trap 1, P type well region 2, N-type well region 4 in the CMOS of institute logical device.Unnecessary in order to form dark N-type trap 1, P type well region 2, the N-type well region 4 of described LDMOS device, and the P type well region 2 of described SONOS device, N-type well region 4 and additionally increase polylith reticle.
Form described well region and carry out threshold voltage adjustment while injecting, need first in described surface of silicon, to form one deck screen oxide 5 and protect described surface of silicon.6 define the region that will carry out Implantation with photoresist afterwards.
After described well region injects and carries out threshold voltage adjustment injection, as shown in Figure 4 B, remove described photoresist 6 and described screen oxide 5.
Step 2, as shown in Figure 4 C, the described surface of silicon after step 1 forms the first pre-oxygen layer 7.The thickness of the described first pre-oxygen layer 7 is 100 dust～150 dusts.
Step 3, as shown in Figure 4 D, adopt chemical wet etching technique to carry out etching to the described first pre-oxygen layer 7, the described first pre-oxygen layer 7 of described SONOS nmosfet formation region is removed and exposed described surface of silicon, the described first pre-oxygen layer 7 outside described SONOS nmosfet formation region is retained.
Step 4, as shown in Figure 4 E, the first silicon oxide layer 8, the second silicon nitride layer 9 and the 3rd silicon oxide layer 10 in described silicon substrate front successively deposit, the thickness of described the first silicon oxide layer 8 is 18 dust～24 dusts; The thickness of described the second silicon nitride layer 9 is 80 dust～120 dusts; The thickness of described the 3rd silicon oxide layer 10 is 40 dust～80 dusts.By described the first silicon oxide layer 8, described the second silicon nitride layer 9 and described the 3rd silicon oxide layer 10, form an ONO layer.Described ONO layer is covered in the described surface of silicon of described SONOS nmosfet formation region and the described first pre-oxygen layer 7 surface outside described SONOS nmosfet formation region.
Step 5, as shown in Fig. 4 F, adopt chemical wet etching technique to carry out etching to described ONO layer, form the gate dielectric layer of described SONOS device and described LDMOS device simultaneously.The described ONO layer that the gate dielectric layer of described SONOS device is positioned at described SONOS nmosfet formation region after by etching forms, wherein, the tunnel oxide that described the first silicon oxide layer 8 is device, described the second silicon nitride layer 9 is data storage medium layer, described the 3rd silica 10 is for controlling oxide layer.The described first pre-oxygen layer 7 and described ONO stacked adding that the gate dielectric layer of described LDMOS device is positioned at described LDMOS nmosfet formation region after by etching, form, and the thickness of the gate dielectric layer of described LDMOS device is 200 dust～300 dusts.After the gate dielectric layer of described SONOS device and described LDMOS device forms, identical photoetching offset plate figure while adopting ONO layer described in etching, adopt etching technics that the described first pre-oxygen layer outside the gate dielectric layer of described SONOS device and described LDMOS device is all removed, this etching technics can be wet etching; Afterwards photoresist is removed.
Step 6, as shown in Figure 4 G, forms the gate oxide of described CMOS logical device.
Step 7, as shown in Figure 4 G, carry out polysilicon deposit, adopt chemical wet etching technique to carry out to described polysilicon the grid polycrystalline silicon 11b that etching forms the grid polycrystalline silicon 11c of described SONOS device, the grid polycrystalline silicon 11a of described LDMOS device and described CMOS logical device simultaneously.
Step 8, as shown in Figure 4 G, carries out lightly-doped source and leaks and in the described silicon substrate that is infused in grid polycrystalline silicon 11a, 11b and 11c both sides described in each, form lightly-doped source and leak injection region.Described in each, lightly-doped source leaks edge and the corresponding described grid polycrystalline silicon autoregistration of injection region.
Described in each, the side of grid polycrystalline silicon 11a, 11b and 11c forms side wall.
Carry out source and leak source region and the drain region of injecting formation described SONOS device, described LDMOS device and described CMOS logical device, and the back-gate electrode draw-out area (Bulk) that simultaneously forms described LDMOS device.
The source region of described SONOS device and drain region be for being symmetrical arranged, and all with the side wall edge autoregistration of corresponding grid polycrystalline silicon.The source region of described P type SONOS device and 12cYou P+ district, drain region form; The source region of described N-type SONOS device and YouN+ district, drain region form.
The source region of described CMOS logical device and drain region be for being symmetrical arranged, and all with the side wall edge autoregistration of corresponding grid polycrystalline silicon.The source region of described NMOS logical device and 12bYou N+ district, drain region form; The source region of described PMOS logical device and YouP+ district, drain region form.
The source region 12a of described asymmetric P type LDMOS device is formed in channel region, and the side wall edge autoregistration of described source region 12a and corresponding grid polycrystalline silicon; The drain region of described asymmetric P type LDMOS device is formed in corresponding drift region and (does not illustrate); The Dou You P+ district, 12aHe drain region, source region of described asymmetric P type LDMOS device forms.
The source region of described asymmetrical N-type LDMOS device and Dou You N+ district, drain region form.
Source region and the drain region of the P type LDMOS device of described symmetry are all formed in corresponding drift region, for being symmetrical arranged Qie Douyou P+ district, form.
The source region of the N-type LDMOS device of described symmetry and drain region are all formed in corresponding drift region, for being symmetrical arranged Qie Douyou N+ district, form.
The back-gate electrode draw-out area of described LDMOS device also comprises two kinds, HeN+ district, P+ district, and the doping type of back-gate electrode draw-out area is identical with the doping type of the channel region that will draw.
The identical lightly-doped source leakage injection region of doping type of SONOS device described above, described LDMOS device and described CMOS logical device is that the lightly-doped source leakage injection region of N-type or P type can adopt respectively a reticle to inject.The source region of described SONOS device, described LDMOS device and described CMOS logical device and the back-gate electrode draw-out area of drain region and described LDMOS device comprise two kinds, HeN+ district, LiaoP+ district, can adopt respectively a reticle to inject and form HuoN+ district, P+ district, thereby form the source region of SONOS device described in each, described LDMOS device and described CMOS logical device and drain region and the back-gate electrode draw-out area of LDMOS device described in each.So the inventive method is unnecessary, in order to form the lightly-doped source of described LDMOS device and described SONOS device, leaks injection region and source-drain area and additionally increase polylith reticle.
It is 12V～16V that the setting of the thickness of the gate dielectric layer of described LDMOS device makes the grid polycrystalline silicon of described LDMOS device withstand voltage.Described in each, well region corresponding to the channel region of LDMOS device and drift region is arranged so that the Punchthrough voltage of LDMOS device is 12V～16V described in each.Make described LDMOS device that the present invention forms meet the high voltage endurance of 12V～16V.
As shown in Fig. 4 H, form and the source region of SONOS device, described LDMOS device and described CMOS logical device described in each and drain region and Metal Contact 13 that described in each, back-gate electrode draw-out area of LDMOS device contacts and is connected.
As shown in Fig. 4 I, form metal level 14, and chemical wet etching forms the source electrode of SONOS device described in each, described LDMOS device and described CMOS logical device and drain electrode and the back-gate electrode of LDMOS device described in each.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (9)

1. a method for integrated SONOS device and LDMOS device in CMOS technique, for integrated SONOS device, LDMOS device and CMOS logical device on same silicon substrate, is characterized in that, comprises the steps:
Step 1, on described silicon substrate, form fleet plough groove isolation structure, by described fleet plough groove isolation structure, isolate active area; Form well region; Carry out threshold voltage adjustment injection;
Step 2, the described surface of silicon after step 1 form the first pre-oxygen layer;
Step 3, employing chemical wet etching technique are carried out etching to the described first pre-oxygen layer, the described first pre-oxygen layer of described SONOS nmosfet formation region is removed and exposed described surface of silicon, the described first pre-oxygen layer outside described SONOS nmosfet formation region is retained;
Step 4, in described silicon substrate front deposit the first silicon oxide layer, the second silicon nitride layer and the 3rd silicon oxide layer successively, by described the first silicon oxide layer, described the second silicon nitride layer and described the 3rd silicon oxide layer, form an ONO layer, described ONO layer is covered in the described surface of silicon of described SONOS nmosfet formation region and the described first pre-oxygen layer surface outside described SONOS nmosfet formation region;
Step 5, employing chemical wet etching technique are carried out etching to described ONO layer, form the gate dielectric layer of described SONOS device and described LDMOS device simultaneously, the described ONO layer that the gate dielectric layer of described SONOS device is positioned at described SONOS nmosfet formation region after by etching forms, and the described first pre-oxygen layer and described ONO stacked adding that the gate dielectric layer of described LDMOS device is positioned at described LDMOS nmosfet formation region after by etching form; Adopt etching technics that the described first pre-oxygen layer outside the gate dielectric layer of described SONOS device and described LDMOS device is all removed;
Step 6, form the gate oxide of described CMOS logical device;
Step 7, carry out polysilicon deposit, adopt chemical wet etching technique to carry out to described polysilicon the grid polycrystalline silicon that etching forms described SONOS device, described LDMOS device and described CMOS logical device simultaneously;
Step 8, carry out lightly-doped source and leak and in the described silicon substrate be infused in grid polycrystalline silicon both sides described in each, to form lightly-doped source and leak injection region; Described in each, the side of grid polycrystalline silicon forms side wall; Carry out source and leak source region and the drain region of injecting formation described SONOS device, described LDMOS device and described CMOS logical device.
2. the method for claim 1, is characterized in that: the thickness of the described first pre-oxygen layer is 100 dust～150 dusts; The thickness of described the first silicon oxide layer is 18 dust～24 dusts; The thickness of described the second silicon nitride layer is 80 dust～120 dusts; The thickness of described the 3rd silicon oxide layer is 40 dust～80 dusts.
3. the method for claim 1, is characterized in that: the thickness of the gate dielectric layer of described LDMOS device is 200 dust～300 dusts.
4. the method for claim 1, is characterized in that: described LDMOS device comprises channel region and drift region; Described channel region and described drift region are adjacent, and the grid polycrystalline silicon of described LDMOS device is covered in top, described channel region for controlling the formation of raceway groove; For N-type LDMOS device, channel region is comprised of P type well region, and drift region is comprised of N-type well region; For P type LDMOS device, channel region is comprised of N-type well region, and drift region is comprised of P type well region; Described P type well region and described N-type well region form in step 1.
5. method as claimed in claim 4, it is characterized in that: for symmetric form LDMOS device, described drift region comprises two, the both sides that are arranged on described channel region of two drift region symmetries, described in each, in drift region, be formed with respectively leakage injection region, ，Liang Ge source, leakage injection region, a source and be symmetrical structure and respectively as source region or the drain region of described symmetric form LDMOS device;
For asymmetric LDMOS device, described drift region comprises one, described drift region is arranged on described channel region near drain terminal one side, described drain region is formed in described drift region, described source region is formed in described channel region, and the grid polycrystalline silicon edge autoregistration of described source region and top, described channel region.
6. method as claimed in claim 3, is characterized in that: the withstand voltage 12V～16V of being of grid polycrystalline silicon of described LDMOS device.
7. the method as described in claim 4 or 5, is characterized in that: the Punchthrough voltage of described LDMOS device is 12V～16V.
8. the method for claim 1, is characterized in that: described SONOS device includes channel region; For N-type SONOS device, described channel region is comprised of P type well region; For P type SONOS device, described channel region is comprised of N-type well region; Described P type well region and described N-type well region form in step 1.
9. the method for claim 1, is characterized in that: described CMOS logical device comprises PMOS logical device and NMOS logical device, and described PMOS logical device and described NMOS logical device all include channel region; For NMOS logical device, described channel region is comprised of P type well region; For PMOS logical device, described channel region is comprised of N-type well region; Described P type well region and described N-type well region form in step 1.
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