CN111883484B - Manufacturing method of switching LDMOS device - Google Patents

Manufacturing method of switching LDMOS device Download PDF

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Publication number
CN111883484B
CN111883484B CN202010817030.7A CN202010817030A CN111883484B CN 111883484 B CN111883484 B CN 111883484B CN 202010817030 A CN202010817030 A CN 202010817030A CN 111883484 B CN111883484 B CN 111883484B
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switching
region
forming
ldmos
ldmos device
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CN111883484A (en
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张晗
杨新杰
金锋
乐薇
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses a manufacturing method of a switching LDMOS device, and relates to the field of semiconductor manufacturing. The method includes forming an active region on a substrate; forming a first well region of the CMOS device in the CMOS region; forming a gate oxide layer on the surface of the substrate; forming a grid electrode of the CMOS device and a grid electrode of the switching LDMOS device; forming a second well region of the switching LDMOS device in the switching LDMOS region, wherein the first well region and the second well region are different; forming a high-voltage doped region of the switching LDMOS device; forming a grid side wall of the device; forming a source region and a drain region of the CMOS device and the switch LDMOS device; the problem that the performance of a switching LDMOS device is limited by a CMOS device is solved by integrally manufacturing the CMOS device and the switching LDMOS device at present; the performance of the switch LDMOS device is improved, and the effect of meeting new application scenes is achieved.

Description

Manufacturing method of switching LDMOS device
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a switching LDMOS device.
Background
The conventional 5-7V switching LDMOS device adopts a 5V CMOS structure, as shown in fig. 1, taking NMOS as an example, the conventional switching LDMOS device includes a P-well 11, a p+ region 12, an n+ region 13, and an N-type LDD region 14 disposed in the P-well 11, a gate structure 15 disposed on a surface of a substrate, and a shallow trench isolation 16 disposed in the substrate.
Typically, the breakdown voltage of the 5V NMOS is 11.5V, the breakdown voltage of the 5V PMOS is 10.5V, the switching LDMOS is fabricated during the CMOS fabrication, the CMOS and the LDMOS share a well region, such as an N-type device shares a P-well, and a P-type device shares an N-well. When a 5-7V switching LDMOS is added in the manufacturing flow of the 5V CMOS, the common use of the well region of the CMOS and the well region of the switching LDMOS only requires 10V for the breakdown voltage of the conventional 5V CMOS, the ion concentration of the well region is very thick, and the Junction breakdown voltage (Junction BV) of the switching LDMOS device is limited; the surface concentration of the well region is light, and a long channel length Lch is required to ensure a Punch-through Breakdown Voltage (BV), so that the cell size of the switching LDMOS is limited.
Due to the limitation, the breakdown voltage of the switching LDMOS device cannot be continuously increased, for example, the breakdown voltage is more than or equal to 12V, a new application scene is difficult to meet, the on-resistance cannot be continuously reduced in a large proportion, and the chip area is difficult to reduce.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a manufacturing method of a switching LDMOS device. The technical scheme comprises the following steps:
in one aspect, an embodiment of the present application provides a method for manufacturing a switching LDMOS device, where the method includes:
forming an active region on a substrate, wherein the active region is used for forming a CMOS device and a switching LDMOS device;
forming a first well region of the CMOS device in the CMOS region;
forming a gate oxide layer on the surface of the substrate;
forming a grid electrode of the CMOS device and a grid electrode of the switching LDMOS device;
forming a second well region of the switching LDMOS device in the switching LDMOS region, wherein the first well region and the second well region are different;
forming a high-voltage doped region of the switching LDMOS device;
forming a grid side wall of the CMOS device and a grid side wall of the switch LDMOS device;
and forming source regions and drain regions of the CMOS device and the switching LDMOS device.
Optionally, forming the gate of the CMOS device and the gate of the switching LDMOS device includes:
forming a polysilicon layer on a substrate;
and forming a grid electrode of the CMOS device in the CMOS region and forming a grid electrode of the switch LDMOS device in the switch LDMOS region through a photoetching process and an etching process.
Optionally, the conductivity type of the high voltage doped region is opposite to the conductivity type of the second well region.
Optionally, before forming the gate sidewall of the CMOS device and the gate sidewall of the switching LDMOS device, the method further includes:
and forming a lightly doped drain region of the CMOS device in the CMOS region.
Optionally, forming a source region and a drain region of the switching LDMOS device includes:
and forming a drain region of the switching LDMOS device in the high-voltage doped region by an ion implantation process, and forming a source region of the switching LDMOS device in the second well region.
Optionally, forming a second well region of the switching LDMOS device in the switching LDMOS region includes:
and forming a second well region below the gate electrode of the switching LDMOS device through an ion implantation process.
Optionally, forming the high-voltage doped region of the switching LDMOS device includes:
defining a high-voltage doped region pattern of the switching LDMOS device through a photoetching process;
etching according to the high-voltage doped region pattern to expose the surface of the substrate corresponding to the high-voltage doped region pattern;
and forming a high-voltage doped region of the switching LDMOS device in the substrate corresponding to the high-voltage doped region pattern through an ion implantation process.
Optionally, one side of the high-voltage doped region of the switching LDMOS device is connected with the shallow trench isolation in the second well region.
Optionally, the CMOS device includes at least one of a PMOS device and an NMOS device;
the switching LDMOS device includes at least one of a switching PLDMOS device and a switching NLDMOS device.
Optionally, the switching LDMOS device is a 5-7V switching LDMOS device.
The technical scheme of the application at least comprises the following advantages:
according to the manufacturing method of the switching LDMOS device, when the CMOS device and the switching LDMOS device are formed on the same substrate, the well region of the CMOS device and the well region of the switching LDMOS device are formed respectively, namely, the well region of the CMOS device and the well region of the switching LDMOS device are not shared, so that the well region of the switching LDMOS device can adopt lower concentration to form junction depth during injection, the requirement of the switching LDMOS device on higher breakdown voltage is met, and the problem that the performance of the switching LDMOS device is limited by the CMOS device due to the fact that the CMOS device and the switching LDMOS device are manufactured in an integrated mode at present is solved; the performance of the switch LDMOS device is improved, and the effect of meeting new application scenes is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional switching LDMOS structure;
fig. 2 is a flowchart of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a switching LDMOS device according to an embodiment of the present application;
fig. 4 is a flowchart of a method for manufacturing a switching LDMOS device according to another embodiment of the present application;
fig. 5 is a schematic diagram of an implementation of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 6 is a schematic diagram illustrating a method for manufacturing a switching LDMOS device according to an embodiment of the application
Fig. 7 is a schematic diagram of an implementation of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 8 is a schematic diagram of an implementation of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 9 is a schematic diagram of an implementation of a method for manufacturing a switching LDMOS device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 2, a flowchart of a method for manufacturing a switching LDMOS device according to an embodiment of the application is shown, and the method at least includes the following steps:
an active region is formed on a substrate, the active region being used to form a CMOS device and a switching LDMOS device, step 201.
Optionally, shallow trench isolation is formed on the substrate, and an active region is defined by the shallow trench isolation, wherein the active region is used for forming a semiconductor device at least comprising a CMOS device and a switching LDMOS device.
In step 202, a first well region of a CMOS device is formed in a CMOS region.
And forming a first well region of the CMOS device in the CMOS region through an ion implantation process. The switching LDMOS region is protected while forming a first well region of the CMOS region.
In step 203, a gate oxide layer is formed on the surface of the substrate.
Optionally, a gate oxide layer is formed on the surface of the substrate by a thermal oxidation process.
Optionally, the gate oxide of the CMOS device and the gate oxide of the switching LDMOS device are formed simultaneously.
At step 204, a gate of the CMOS device and a gate of the switching LDMOS device are formed.
Optionally, the gate of the CMOS device and the gate of the switching LDMOS device are formed in the same process step.
In step 205, a second well region of the switching LDMOS device is formed in the switching LDMOS region, and the first well region and the second well region are different.
And forming a second well region of the switching LDMOS device in the switching LDMOS region through an ion implantation process. The CMOS region is protected while forming the second well region of the switching LDMOS device.
Optionally, the concentration of the implanted ions used to form the first well region is different from the concentration of the implanted ions used to form the second well region, and the mask used to form the first well region is different from the mask used to form the second well region.
At step 206, a high voltage doped region of the switching LDMOS device is formed.
And forming a high voltage doped region (HVLDD) of the switching LDMOS device at a predetermined position in the switching LDMOS region.
In the subsequent process steps, a drain region of the switching LDMOS device is formed in the high-voltage doped region.
And step 207, forming a grid side wall of the CMOS device and a grid side wall of the switch LDMOS device.
Optionally, the gate sidewall of the CMOS device and the gate sidewall of the switching LDMOS device are formed simultaneously.
At step 208, source and drain regions of the CMOS device and the switching LDMOS device are formed.
And forming a source region and a drain region through ion implantation.
Optionally, the source region of the CMOS device is formed simultaneously with the source region of the switching LDMOS device, and the drain region of the CMOS device is formed simultaneously with the drain region of the switching LDMOS device.
Fig. 3 schematically illustrates a structure of a switching LDMOS device manufactured by using the manufacturing method of the switching LDMOS device provided by the embodiment of the application, in which a second well region 36 of the switching LDMOS device is formed in a substrate 31, the second well region 36 is not shared with a CMOS device, and a shallow trench isolation 38 is also formed on the substrate 31; a high-voltage doped region 35 and a source region 32 are provided in the second well region 36, and a drain region 34 is formed in the high-voltage doped region 35. The source region 32 of the switching LDMOS device is formed of a first type heavily doped region and a second type heavily doped region having opposite conductivity types, the first type heavily doped region having the same conductivity type as the drain region 34.
Wherein the switching LDMOS device comprises a first gate 33 and a second gate 37; the second gate 37 is located above the shallow trench isolation, the second gate 37 acting as a mask for the self-aligned implantation of the high-voltage doped region 35, the second gate 37 being electrically inactive.
In summary, in the method for manufacturing the switching LDMOS device provided by the embodiment of the application, when the CMOS device and the switching LDMOS device are formed on the same substrate, the well region of the CMOS device and the well region of the switching LDMOS device are formed respectively, i.e., the well region of the CMOS device and the well region of the switching LDMOS device are not shared, so that the well region of the switching LDMOS device can adopt a lower concentration to form a junction depth during injection, thereby meeting the requirement of the switching LDMOS device on a higher breakdown voltage, and solving the problem that the performance of the switching LDMOS device is limited by the CMOS device when the CMOS device and the switching LDMOS device are manufactured in an integrated manner at present; the performance of the switch LDMOS device is improved, and the effect of meeting new application scenes is achieved.
Referring to fig. 4, a flowchart of a method for manufacturing a switching LDMOS device according to another embodiment of the application is shown, the method at least includes the following steps:
an active region is formed on a substrate, the active region being used to form a CMOS device and a switching LDMOS device, step 401.
This step is described in step 201 above, and will not be described here again.
In step 402, a first well region of a CMOS device is formed in a CMOS region.
This step is described in step 202 above, and will not be described again here.
In step 403, a gate oxide layer is formed on the surface of the substrate.
This step is described in step 203 above, and will not be described here again.
At step 404, a polysilicon layer is formed on the substrate.
And depositing a polysilicon layer on the surface of the substrate, wherein the polysilicon layer is formed in the CMOS area and the switch LDMOS area.
As shown in fig. 5, in the switching LDMOS region, shallow trench isolation 38 is formed on the substrate 31, and a polysilicon layer 51 is formed on the surface of the substrate 31.
In step 405, a gate of the CMOS device is formed in the CMOS area and a gate of the switching LDMOS device is formed in the switching LDMOS area by a photolithography process and an etching process.
Optionally, photoresist is coated on the surface of the polysilicon layer, and after exposure and development by a mask, the gate position of the CMOS device and the gate position of the switch LDMOS device are determined, wherein the gate of the CMOS device is in the CMOS region, and the gate of the switch LDMOS device is in the switch LDMOS region.
And etching the polysilicon layer through an etching process, forming a grid electrode of the CMOS device in the CMOS region, and forming a grid electrode of the switch LDMOS device in the switch LDMOS region.
As shown in fig. 6, in the LDMOS region, a polysilicon gate 52 is formed on the surface of the substrate 31.
In step 406, a second well region is formed under the gate of the switching LDMOS device by an ion implantation process.
The first well region and the second well region are different.
The first well region and the second well region are different in formation region, and the first well region and the second well region are different in implantation concentration adopted during ion implantation.
Optionally, the photoresist is used to protect the area where the second well region is not required to be formed before the second well region of the switching LDMOS device is formed.
As shown in fig. 7, when the second well region 36 is formed by performing an ion implantation process, the photoresist 53 on the surface of the substrate is left, and ion implantation is performed by self-alignment through the polysilicon gate electrode 52.
In the second well region forming process, a pocket region (HALO) is formed on top of the second well region, the pocket region is located at two sides of the polysilicon gate and is located between the shallow trench isolation and the polysilicon gate.
Because the well region of the switching LDMOS device and the well region of the CMOS device are not shared, the ion implantation is self-aligned with glue and is performed through the polysilicon gate, and the junction depth can be formed by adopting a concentration lower than the implantation concentration of the well region of the CMOS device, so that the requirement of the switching LDMOS device on breakdown voltage is met.
Because the second well region is injected to form a channel by self-aligned injection, the surface concentration of the second well region can be improved, the channel length Lch can be shortened to reduce the cell size of the switching LDMOS device, and further, the lower on-resistance can be obtained.
In step 407, a high voltage doped region pattern of the switching LDMOS device is defined by a photolithography process.
Optionally, photoresist is coated on the surface of the substrate, and a high-voltage doped region pattern of the switching LDMOS device is formed on the photoresist layer through a photoetching process.
And step 408, etching according to the high-voltage doped region pattern to expose the surface of the substrate corresponding to the high-voltage doped region pattern.
And etching the material below the photoresist layer according to the high-voltage doped region pattern until the surface of the substrate corresponding to the high-voltage doped region pattern is exposed.
And when the polysilicon gate exists below the high-voltage doped region pattern, etching the polysilicon gate to expose the surface of the substrate.
As shown in fig. 8, since the substrate on which the high-voltage doped region is to be formed is covered with the polysilicon gate, the polysilicon gate is etched according to the high-voltage doped region pattern in the photoresist layer 54 at the time of etching, and the etched polysilicon gate is divided into a first gate 33 and a second gate 37, the first gate 33 has electrical properties, the second gate 37 is located above the shallow trench isolation in the second well region 36, the second gate 37 has no electrical properties, and the second gate defines the position of the high-voltage doped region.
And 409, forming a high-voltage doped region of the switching LDMOS device in the substrate corresponding to the high-voltage doped region pattern through an ion implantation process.
The high voltage doped region has a conductivity type opposite to that of the second well region.
One side of the high-voltage doped region of the switching LDMOS device is connected with the shallow trench isolation in the second well region.
As shown in fig. 9, an ion implantation process is performed to form a high-voltage doped region 35, the high-voltage doped region 35 being defined between the first gate 33 and the second gate 37, one side of the high-voltage doped region 35 being connected to shallow trench isolation in the second well region 36.
In step 410, lightly doped drain regions of the CMOS device are formed in the CMOS region.
Optionally, a lightly doped drain region of the CMOS device is formed in the CMOS region by an ion implantation process.
In step 411, a gate sidewall of the CMOS device and a gate sidewall of the switching LDMOS device are formed.
Optionally, a sidewall material is deposited on the surface of the substrate, and back etching is performed until the top of the polysilicon gate is exposed.
Optionally, gate side walls are formed on both sides of the gate of the CMOS device, on both sides of the first gate of the switching LDMOS device, and on both sides of the second gate of the switching LDMOS device.
And 412, forming source regions and drain regions of the CMOS device and the switching LDMOS device.
And forming a drain region of the switching LDMOS device in the high-voltage doped region by an ion implantation process, and forming a source region of the switching LDMOS device in the second well region.
And forming a source region and a drain region of the CMOS device in the CMOS region through an ion implantation process.
Optionally, forming a first type heavily doped region in the first well region of the CMOS region and the second well region of the switch LDMOS region by an ion implantation process, and forming a second type heavily doped region in the first well region of the CMOS region and the second well region of the switch LDMOS region by an ion implantation process; the first type heavily doped region has a conductivity type opposite to the conductivity type of the second type heavily doped region.
In the CMOS area, the first heavily doped region is used as a source region of the CMOS device, and the second heavily doped region is used as a drain region of the CMOS device.
And in the switching LDMOS region, a second type heavily doped region in the high-voltage doped region is used as a drain region of the switching LDMOS device, and a first type heavily doped region and a second type heavily doped region which are positioned outside the high-voltage doped region in the second well region form a source region of the switching LDMOS device.
A schematic structure of the formed switching LDMOS device is shown in FIG. 3.
In an alternative embodiment based on the embodiment shown in fig. 2 or 4, the CMOS device comprises at least one of a PMOS device and an NMOS device; the switching LDMOS device includes at least one of a switching PLDMOS device and a switching NLDMOS device.
In one example, the CMOS devices fabricated on the substrate include both PMOS devices and NMOS devices, and the switching LDMOS devices include switching PLDMOS devices and switching NLDMOS devices, where ion implantation may be performed on the P-type devices followed by ion implantation on the N-type devices, or on the N-type devices followed by ion implantation on the P-type devices.
In one example, the method for manufacturing the switching LDMOS device provided by the embodiment of the application is suitable for the switching LDMOS device with the working voltage of a drain terminal of 5-7V.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.

Claims (10)

1. A method of fabricating a switching LDMOS device, the method comprising:
forming an active region on a substrate, wherein the active region is used for forming a CMOS device and a switching LDMOS device;
forming a first well region of the CMOS device in the CMOS region;
forming a gate oxide layer on the surface of the substrate;
forming a grid electrode of the CMOS device and a grid electrode of the switching LDMOS device;
forming a second well region of the switching LDMOS device in the switching LDMOS region, wherein the concentration of implanted ions for forming the first well region is different from the concentration of implanted ions for forming the second well region;
forming a high-voltage doped region of the switching LDMOS device;
forming a grid side wall of the CMOS device and a grid side wall of the switch LDMOS device;
and forming source regions and drain regions of the CMOS device and the switching LDMOS device.
2. The method of claim 1, wherein forming the gate of the CMOS device and the gate of the switching LDMOS device comprises:
forming a polysilicon layer on the substrate;
and forming a grid electrode of the CMOS device in the CMOS region and forming a grid electrode of the switching LDMOS device in the switching LDMOS region through a photoetching process and an etching process.
3. The method of claim 1, wherein the high voltage doped region has a conductivity type opposite to a conductivity type of the second well region.
4. The method of claim 1, wherein prior to forming the gate sidewall of the CMOS device and the gate sidewall of the switching LDMOS device, the method further comprises:
and forming a lightly doped drain region of the CMOS device in the CMOS region.
5. The method of claim 1, wherein forming source and drain regions of the switching LDMOS device comprises:
and forming a drain region of the switching LDMOS device in the high-voltage doped region by an ion implantation process, and forming a source region of the switching LDMOS device in the second well region.
6. The method of claim 1, wherein forming the second well region of the switching LDMOS device in the switching LDMOS region comprises:
and forming the second well region below the grid electrode of the switching LDMOS device through an ion implantation process.
7. The method of claim 1, wherein forming the high voltage doped region of the switching LDMOS device comprises:
defining a high-voltage doped region pattern of the switching LDMOS device through a photoetching process;
etching according to the high-voltage doped region pattern to expose the surface of the substrate corresponding to the high-voltage doped region pattern;
and forming a high-voltage doped region of the switching LDMOS device in the substrate corresponding to the high-voltage doped region pattern through an ion implantation process.
8. The method of claim 7, wherein a side of the high voltage doped region of the switching LDMOS device is contiguous with a shallow trench isolation within the second well region.
9. The method of claim 1, wherein the CMOS device comprises at least one of a PMOS device and an NMOS device;
the switching LDMOS device comprises at least one of a switching PLDMOS device and a switching NLDMOS device.
10. The method of any of claims 1-9, wherein the switching LDMOS device is a 5-7V switching LDMOS device.
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