CN111883484A - Manufacturing method of switch LDMOS device - Google Patents

Manufacturing method of switch LDMOS device Download PDF

Info

Publication number
CN111883484A
CN111883484A CN202010817030.7A CN202010817030A CN111883484A CN 111883484 A CN111883484 A CN 111883484A CN 202010817030 A CN202010817030 A CN 202010817030A CN 111883484 A CN111883484 A CN 111883484A
Authority
CN
China
Prior art keywords
region
forming
switch
ldmos device
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010817030.7A
Other languages
Chinese (zh)
Other versions
CN111883484B (en
Inventor
张晗
杨新杰
金锋
乐薇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202010817030.7A priority Critical patent/CN111883484B/en
Publication of CN111883484A publication Critical patent/CN111883484A/en
Application granted granted Critical
Publication of CN111883484B publication Critical patent/CN111883484B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses a manufacturing method of a switch LDMOS device, and relates to the field of semiconductor manufacturing. The method includes forming an active region on a substrate; forming a first well region of a CMOS device in the CMOS region; forming a gate oxide layer on the surface of the substrate; forming a grid electrode of the CMOS device and a grid electrode of the switch LDMOS device; forming a second well region of the switch LDMOS device in the switch LDMOS region, wherein the first well region is different from the second well region; forming a high-voltage doped region of the switch LDMOS device; forming a grid side wall of the device; forming a source region and a drain region of the CMOS device and the switch LDMOS device; the problem that the performance of the switch LDMOS device is limited by the CMOS device when the CMOS device and the switch LDMOS device are integrally manufactured at present is solved; the performance of the switch LDMOS device is improved, and the effect of meeting a new application scene is achieved.

Description

Manufacturing method of switch LDMOS device
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a switch LDMOS device.
Background
At present, a 5-7V switch LDMOS device adopts a conventional structure of a 5V CMOS, as shown in fig. 1, taking an NMOS as an example, the existing switch LDMOS device includes a P well 11, a P + region 12, an N + region 13, and an N-type LDD region 14 are disposed in the P well 11, a gate structure 15 is disposed on a surface of the substrate, and a shallow trench isolation 16 is also disposed in the substrate.
The breakdown voltage of a 5V NMOS is generally 11.5V, the breakdown voltage of a 5V PMOS is generally 10.5V, a switch LDMOS is manufactured when the CMOS is manufactured, the CMOS and the LDMOS share a well region, for example, an N-type device shares a P-well, and the P-type device shares an N-well. When the 5-7V switch LDMOS is added in the manufacturing process of the 5V CMOS, as the well region of the CMOS and the well region of the switch LDMOS are shared, the breakdown voltage of the conventional 5V CMOS only requires 10V, the ion concentration of the well region is very strong, and the Junction breakdown voltage (Junction BV) of the switch LDMOS device is limited; the surface concentration of the well region is relatively light, and a long channel length Lch is required to ensure punch-through breakdown voltage (punchthreow BV), so that the cell size reduction of the switch LDMOS is limited.
Due to the above limitation, the breakdown voltage of the switch LDMOS device cannot be continuously increased, for example, the breakdown voltage is greater than or equal to 12V, which is difficult to meet new application scenarios, the on-resistance cannot be continuously reduced in a large scale, and the chip area is difficult to reduce.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method for manufacturing a switching LDMOS device. The technical scheme comprises the following steps:
in one aspect, an embodiment of the present application provides a method for manufacturing a switching LDMOS device, where the method includes:
forming an active region on the substrate, wherein the active region is used for forming a CMOS device and a switch LDMOS device;
forming a first well region of a CMOS device in the CMOS region;
forming a gate oxide layer on the surface of the substrate;
forming a grid electrode of the CMOS device and a grid electrode of the switch LDMOS device;
forming a second well region of the switch LDMOS device in the switch LDMOS region, wherein the first well region is different from the second well region;
forming a high-voltage doped region of the switch LDMOS device;
forming a grid side wall of the CMOS device and a grid side wall of the switch LDMOS device;
and forming a source region and a drain region of the CMOS device and the LDMOS switch device.
Optionally, forming a gate of the CMOS device and a gate of the switching LDMOS device includes:
forming a polysilicon layer on a substrate;
and forming a grid electrode of the CMOS device in the CMOS area and forming a grid electrode of the switch LDMOS device in the switch LDMOS area through a photoetching process and an etching process.
Optionally, the conductivity type of the high-voltage doped region is opposite to the conductivity type of the second well region.
Optionally, before forming the gate sidewall of the CMOS device and the gate sidewall of the switch LDMOS device, the method further includes:
and forming a lightly doped drain region of the CMOS device in the CMOS area.
Optionally, forming a source region and a drain region of the switching LDMOS device includes:
and forming a drain region of the switch LDMOS device in the high-voltage doped region through an ion implantation process, and forming a source region of the switch LDMOS device in the second well region.
Optionally, forming a second well region of the switch LDMOS device in the switch LDMOS region includes:
and forming a second well region below the grid electrode of the switch LDMOS device through an ion implantation process.
Optionally, forming a high-voltage doped region of the switching LDMOS device includes:
defining a high-voltage doped region pattern of the switch LDMOS device through a photoetching process;
etching according to the high-voltage doped region pattern to expose the substrate surface corresponding to the high-voltage doped region pattern;
and forming a high-voltage doped region of the switch LDMOS device in the substrate corresponding to the high-voltage doped region pattern through an ion implantation process.
Optionally, one side of the high-voltage doped region of the switch LDMOS device is connected to the shallow trench isolation in the second well region.
Optionally, the CMOS device includes at least one of a PMOS device and an NMOS device;
the switching LDMOS device includes at least one of a switching PLDMOS device and a switching NLDMOS device.
Optionally, the switch LDMOS device is a 5-7V switch LDMOS device.
The technical scheme at least comprises the following advantages:
according to the manufacturing method of the switch LDMOS device, provided by the embodiment of the application, when the CMOS device and the switch LDMOS device are formed on the same substrate, the well region of the CMOS device and the well region of the switch LDMOS device are respectively formed, namely the well region of the CMOS device and the well region of the switch LDMOS device are not shared, so that the well region of the switch LDMOS device can adopt lower concentration to form junction depth during injection, the requirement of the switch LDMOS device on higher breakdown voltage is met, and the problem that the performance of the switch LDMOS device is limited by the CMOS device in the existing integrated manufacturing of the CMOS device and the switch LDMOS device is solved; the performance of the switch LDMOS device is improved, and the effect of meeting a new application scene is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional switching LDMOS;
fig. 2 is a flowchart of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a switching LDMOS device according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a method for manufacturing a switching LDMOS device according to another embodiment of the present application;
fig. 5 is a schematic implementation diagram of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 6 is an implementation schematic diagram of a method for manufacturing a switching LDMOS device according to an embodiment of the present application
Fig. 7 is a schematic implementation diagram of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 8 is a schematic implementation diagram of a method for manufacturing a switching LDMOS device according to an embodiment of the present application;
fig. 9 is an implementation schematic diagram of a method for manufacturing a switching LDMOS device according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flowchart of a method for manufacturing a switching LDMOS device according to an embodiment of the present application is shown, where the method at least includes the following steps:
step 201, forming an active region on a substrate, wherein the active region is used for forming a CMOS device and a switch LDMOS device.
Optionally, shallow trench isolation is formed on the substrate, and an active region is defined by using the shallow trench isolation, and the active region is used for forming a semiconductor device at least comprising a CMOS device and a switch LDMOS device.
In step 202, a first well region of a CMOS device is formed in a CMOS region.
A first well region of the CMOS device is formed in the CMOS region by an ion implantation process. The switching LDMOS region is protected while the first well region of the CMOS region is formed.
Step 203, forming a gate oxide layer on the surface of the substrate.
Optionally, a gate oxide layer is formed on the surface of the substrate by a thermal oxidation process.
Optionally, the gate oxide layer of the CMOS device and the gate oxide layer of the switching LDMOS device are formed simultaneously.
And step 204, forming a grid electrode of the CMOS device and a grid electrode of the switch LDMOS device.
Optionally, the gate of the CMOS device and the gate of the switching LDMOS device are formed in the same process step.
In step 205, a second well region of the switch LDMOS device is formed in the switch LDMOS region, and the first well region and the second well region are different.
And forming a second well region of the switch LDMOS device in the switch LDMOS region through an ion implantation process. The CMOS region is protected when the second well region of the switching LDMOS device is formed.
Optionally, the ion implantation concentration for forming the first well region is different from the ion implantation concentration for forming the second well region, and the photomask for forming the first well region is different from the photomask for forming the second well region.
And step 206, forming a high-voltage doped region of the switch LDMOS device.
At a predetermined position in the switching LDMOS region, a high voltage doped region (HVLDD) of the switching LDMOS device is formed.
In the subsequent process steps, a drain region of the switch LDMOS device is formed in the high-voltage doping region.
And step 207, forming a grid side wall of the CMOS device and a grid side wall of the switch LDMOS device.
Optionally, the gate side wall of the CMOS device and the gate side wall of the switch LDMOS device are formed at the same time.
And step 208, forming source regions and drain regions of the CMOS device and the switch LDMOS device.
And forming a source region and a drain region by ion implantation.
Optionally, a source region of the CMOS device and a source region of the switch LDMOS device are formed at the same time, and a drain region of the CMOS device and a drain region of the switch LDMOS region are formed at the same time.
Fig. 3 schematically illustrates a structure of a switching LDMOS device manufactured by the method for manufacturing a switching LDMOS device according to an embodiment of the present application, a second well region 36 of the switching LDMOS device is formed in a substrate 31, the second well region 36 is not shared by CMOS devices, and a shallow trench isolation 38 is further formed on the substrate 31; the second well region 36 has a high-voltage doped region 35 and a source region 32 formed therein, and a drain region 34 is formed in the high-voltage doped region 35. The source region 32 of the switch LDMOS device is composed of a first type heavily doped region and a second type heavily doped region, the conductivity types of the first type heavily doped region and the second type heavily doped region are opposite, and the conductivity type of the first type heavily doped region is the same as the conductivity type 34 of the drain region.
Wherein the switching LDMOS device includes a first gate 33 and a second gate 37; the second gate 37 is located above the shallow trench isolation, the second gate 37 serves as a mask for the self-aligned implantation of the high-voltage doped region 35, and the second gate 37 does not function electrically.
In summary, according to the manufacturing method of the switch LDMOS device provided by the embodiment of the present application, when the CMOS device and the switch LDMOS device are formed on the same substrate, the well region of the CMOS device and the well region of the switch LDMOS device are formed respectively, that is, the well region of the CMOS device and the well region of the switch LDMOS device are not shared, so that the well region of the switch LDMOS device can adopt a lower concentration to form junction depth during injection, thereby satisfying the requirement of the switch LDMOS device for a higher breakdown voltage, and solving the problem that the performance of the switch LDMOS device is limited by the CMOS device when the CMOS device and the switch LDMOS device are integrally manufactured at present; the performance of the switch LDMOS device is improved, and the effect of meeting a new application scene is achieved.
Referring to fig. 4, a flow chart of a method for manufacturing a switching LDMOS device according to another embodiment of the present application is shown, where the method at least includes the following steps:
step 401, forming an active region on a substrate, wherein the active region is used for forming a CMOS device and a switch LDMOS device.
This step is explained in step 201 above and will not be described here.
In step 402, a first well region of a CMOS device is formed in a CMOS region.
This step is explained in step 202 above and will not be described here.
Step 403, forming a gate oxide layer on the surface of the substrate.
This step is explained in step 203 above and will not be described here.
At step 404, a polysilicon layer is formed on the substrate.
And depositing a polycrystalline silicon layer on the surface of the substrate, wherein the polycrystalline silicon layer is formed in the CMOS area and the switch LDMOS area.
As shown in fig. 5, in the LDMOS region of the switch, shallow trench isolations 38 are formed on the substrate 31, and a polysilicon layer 51 is formed on the surface of the substrate 31.
Step 405, forming a gate of the CMOS device in the CMOS region and a gate of the switching LDMOS device in the switching LDMOS region by a photolithography process and an etching process.
Optionally, photoresist is coated on the surface of the polycrystalline silicon layer, the polycrystalline silicon layer is exposed through a mask plate, and after development, the position of the gate of the CMOS device and the position of the gate of the switch LDMOS device are determined, the gate of the CMOS device is in the CMOS region, and the gate of the switch LDMOS device is in the switch LDMOS region.
And etching the polysilicon layer by an etching process to form a grid electrode of the CMOS device in the CMOS area and a grid electrode of the switch LDMOS device in the switch LDMOS area.
As shown in fig. 6, in the LDMOS region, a polysilicon gate 52 is formed on the surface of the substrate 31.
In step 406, a second well region is formed under the gate of the switching LDMOS device by an ion implantation process.
The first well region and the second well region are different.
The first well region and the second well region are different in forming region, and the first well region and the second well region are different in injection concentration during ion injection.
Optionally, before forming the second well region of the switching LDMOS device, a photoresist is used to protect a region where the second well region is not required to be formed.
As shown in fig. 7, when the ion implantation process is performed to form the second well region 36, the photoresist 53 on the substrate surface is remained, and the ion implantation is performed through the polysilicon gate 52 in a self-aligned manner.
During the formation of the second well region, pocket regions (HALO) are formed at the top of the second well region, and the pocket regions are located on both sides of the polysilicon gate and between the shallow trench isolation and the polysilicon gate.
Because the well region of the switch LDMOS device and the well region of the CMOS device are not shared, the ion implantation is self-aligned with glue and is carried out by separating the polysilicon gate, and the junction depth can be formed by adopting the concentration lower than the well region implantation concentration of the CMOS device, thereby meeting the requirement of the switch LDMOS device on the breakdown voltage.
Because the channel is formed by self-aligned injection when the second well region is injected, the surface concentration of the second well region can be improved, the channel length Lch is shortened to reduce the cell size of the switch LDMOS device, and further lower on resistance is obtained.
Step 407, defining a high-voltage doped region pattern of the switch LDMOS device through a photolithography process.
Optionally, photoresist is coated on the surface of the substrate, and a high-voltage doped region pattern of the switch LDMOS device is formed on the photoresist layer through a photolithography process.
And step 408, etching is carried out according to the high-voltage doped region pattern, and the substrate surface corresponding to the high-voltage doped region pattern is exposed.
And etching the material below the photoresist layer according to the high-pressure doped region pattern until the substrate surface corresponding to the high-pressure doped region pattern is exposed.
And when the polysilicon gate exists below the high-voltage doped region pattern, etching the polysilicon gate to expose the surface of the substrate.
As shown in fig. 8, since the substrate on which the high voltage doped region is to be formed is covered by the polysilicon gate, during etching, the polysilicon gate is etched according to the high voltage doped region pattern in the photoresist layer 54, the etched polysilicon gate is divided into a first gate 33 and a second gate 37, the first gate 33 has electrical properties, the second gate 37 is located above the shallow trench isolation in the second well region 36, the second gate 37 has no electrical properties, and the second gate defines the position of the high voltage doped region.
And 409, forming a high-voltage doped region of the switch LDMOS device in the substrate corresponding to the high-voltage doped region pattern through an ion implantation process.
The high-voltage doped region has a conductivity type opposite to that of the second well region.
One side of the high-voltage doped region of the switch LDMOS device is connected with the shallow trench isolation in the second well region.
As shown in fig. 9, an ion implantation process is performed to form a high-voltage doped region 35, the high-voltage doped region 35 is defined between the first gate 33 and the second gate 37, and one side of the high-voltage doped region 35 is connected to the shallow trench isolation in the second well region 36.
In step 410, lightly doped drain regions of the CMOS devices are formed in the CMOS regions.
Optionally, a lightly doped drain region of the CMOS device is formed in the CMOS region by an ion implantation process.
Step 411, forming a gate side wall of the CMOS device and a gate side wall of the switch LDMOS device.
Optionally, a side wall material is deposited on the surface of the substrate, and etching is performed until the top of the polysilicon gate is exposed.
Optionally, two sides of the gate of the CMOS device, two sides of the first gate of the switch LDMOS device, and two sides of the second gate of the switch LDMOS device form gate side walls.
And step 412, forming source regions and drain regions of the CMOS device and the switch LDMOS device.
And forming a drain region of the switch LDMOS device in the high-voltage doped region through an ion implantation process, and forming a source region of the switch LDMOS device in the second well region.
And forming a source region and a drain region of the CMOS device in the CMOS region by an ion implantation process.
Optionally, a first heavily doped region is formed in the first well region of the CMOS region and the second well region of the switch LDMOS region by an ion implantation process, and a second heavily doped region is formed in the first well region of the CMOS region and the second well region of the switch LDMOS region by an ion implantation process; the conductivity type of the first type heavily doped region is opposite to that of the second type heavily doped region.
In the CMOS area, the first type heavily doped area is used as a source area of the CMOS device, and the second type heavily doped area is used as a drain area of the CMOS device.
In the switch LDMOS region, a second heavily doped region in the high-voltage doped region serves as a drain region of the switch LDMOS device in a second well region, and the first heavily doped region and the second heavily doped region outside the high-voltage doped region in the second well region form a source region of the switch LDMOS device.
The structure of the formed switching LDMOS device is schematically shown in fig. 3.
In an alternative embodiment based on the embodiment shown in fig. 2 or 4, the CMOS device comprises at least one of a PMOS device and an NMOS device; the switching LDMOS device includes at least one of a switching PLDMOS device and a switching NLDMOS device.
In one example, the CMOS device fabricated on the substrate includes both a PMOS device and an NMOS device, and the switching LDMOS device includes a switching PLDMOS device and a switching NLDMOS device, and when performing ion implantation, ion implantation of the P-type device may be performed first, and then ion implantation of the N-type device may be performed, or ion implantation of the N-type device may be performed first, and then ion implantation of the P-type device may be performed.
In one example, the manufacturing method of the switching LDMOS device provided by the embodiment of the application is suitable for a switching LDMOS device with a drain-side operating voltage of 5-7V.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (10)

1. A method of fabricating a switching LDMOS device, the method comprising:
forming an active region on a substrate, wherein the active region is used for forming a CMOS device and a switch LDMOS device;
forming a first well region of a CMOS device in the CMOS region;
forming a gate oxide layer on the surface of the substrate;
forming a gate of the CMOS device and a gate of the switch LDMOS device;
forming a second well region of the switch LDMOS device in the switch LDMOS region, wherein the first well region is different from the second well region;
forming a high-voltage doped region of the switch LDMOS device;
forming a grid side wall of the CMOS device and a grid side wall of the switch LDMOS device;
and forming source regions and drain regions of the CMOS device and the switch LDMOS device.
2. The method of claim 1, wherein forming the gate of the CMOS device and the gate of the switch LDMOS device comprises:
forming a polysilicon layer on the substrate;
and forming a grid electrode of the CMOS device in the CMOS area and forming a grid electrode of the switch LDMOS device in the switch LDMOS area through a photoetching process and an etching process.
3. The method of claim 1, wherein the HVD region has a conductivity type opposite to a conductivity type of the second well region.
4. The method of claim 1, wherein before forming the gate sidewall spacers of the CMOS device and the switch LDMOS device, the method further comprises:
and forming a lightly doped drain region of the CMOS device in the CMOS region.
5. The method of claim 1, wherein forming the source and drain regions of the switching LDMOS device comprises:
and forming a drain region of the switch LDMOS device in the high-voltage doped region through an ion implantation process, and forming a source region of the switch LDMOS device in the second well region.
6. The method of claim 1, wherein forming the second well region of the switch LDMOS device in the switch LDMOS region comprises:
and forming the second well region below the grid electrode of the switch LDMOS device through an ion implantation process.
7. The method of claim 1, wherein forming the high-voltage doped region of the switching LDMOS device comprises:
defining a high-voltage doped region pattern of the switch LDMOS device through a photoetching process;
etching according to the high-voltage doped region pattern to expose the substrate surface corresponding to the high-voltage doped region pattern;
and forming a high-voltage doped region of the switch LDMOS device in the substrate corresponding to the high-voltage doped region pattern through an ion implantation process.
8. The method of claim 7, wherein one side of the heavily doped region of the switch LDMOS device is connected to the shallow trench isolation in the second well region.
9. The method of claim 1, wherein the CMOS device comprises at least one of a PMOS device and an NMOS device;
the switch LDMOS device comprises at least one of a switch PLDMOS device and a switch NLDMOS device.
10. The method of any of claims 1 to 9, wherein the switching LDMOS device is a 5-7V switching LDMOS device.
CN202010817030.7A 2020-08-14 2020-08-14 Manufacturing method of switching LDMOS device Active CN111883484B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010817030.7A CN111883484B (en) 2020-08-14 2020-08-14 Manufacturing method of switching LDMOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010817030.7A CN111883484B (en) 2020-08-14 2020-08-14 Manufacturing method of switching LDMOS device

Publications (2)

Publication Number Publication Date
CN111883484A true CN111883484A (en) 2020-11-03
CN111883484B CN111883484B (en) 2023-10-20

Family

ID=73203745

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010817030.7A Active CN111883484B (en) 2020-08-14 2020-08-14 Manufacturing method of switching LDMOS device

Country Status (1)

Country Link
CN (1) CN111883484B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113921591A (en) * 2021-09-24 2022-01-11 上海华虹宏力半导体制造有限公司 LDMOS device and forming method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108520A1 (en) * 2005-11-07 2007-05-17 Macronix International Co., Ltd. Laterally double-diffused metal oxide semiconductor transistor and method for fabricating the same
CN101378075A (en) * 2007-08-31 2009-03-04 谭健 LDMOS, and semicondutor device integrating with LDMOS and CMOS
CN101819937A (en) * 2009-05-29 2010-09-01 杭州矽力杰半导体技术有限公司 Method for manufacturing lateral double-diffused metal oxide semiconductor transistor
CN102097389A (en) * 2011-01-12 2011-06-15 深圳市联德合微电子有限公司 LDMOS (laterally diffused metal oxide semiconductor), semiconductor device integrated with same and manufacturing method thereof
CN103208519A (en) * 2012-01-12 2013-07-17 上海华虹Nec电子有限公司 N-type laterally diffused metal oxide semiconductor (NLMOS) structure compatible with 5-V complementary metal oxide semiconductor (CMOS) process and manufacturing method thereof
CN103632942A (en) * 2012-08-24 2014-03-12 上海华虹宏力半导体制造有限公司 SONOS device and LDMOS device integration method in CMOS process
CN104900591A (en) * 2014-03-06 2015-09-09 美格纳半导体有限公司 Low-cost semiconductor device manufacturing method
CN110767551A (en) * 2019-10-17 2020-02-07 上海华力集成电路制造有限公司 LDMOS device, manufacturing method thereof and method for adjusting electrical parameters of LDMOS device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108520A1 (en) * 2005-11-07 2007-05-17 Macronix International Co., Ltd. Laterally double-diffused metal oxide semiconductor transistor and method for fabricating the same
CN101378075A (en) * 2007-08-31 2009-03-04 谭健 LDMOS, and semicondutor device integrating with LDMOS and CMOS
CN101819937A (en) * 2009-05-29 2010-09-01 杭州矽力杰半导体技术有限公司 Method for manufacturing lateral double-diffused metal oxide semiconductor transistor
CN102097389A (en) * 2011-01-12 2011-06-15 深圳市联德合微电子有限公司 LDMOS (laterally diffused metal oxide semiconductor), semiconductor device integrated with same and manufacturing method thereof
CN103208519A (en) * 2012-01-12 2013-07-17 上海华虹Nec电子有限公司 N-type laterally diffused metal oxide semiconductor (NLMOS) structure compatible with 5-V complementary metal oxide semiconductor (CMOS) process and manufacturing method thereof
CN103632942A (en) * 2012-08-24 2014-03-12 上海华虹宏力半导体制造有限公司 SONOS device and LDMOS device integration method in CMOS process
CN104900591A (en) * 2014-03-06 2015-09-09 美格纳半导体有限公司 Low-cost semiconductor device manufacturing method
CN110767551A (en) * 2019-10-17 2020-02-07 上海华力集成电路制造有限公司 LDMOS device, manufacturing method thereof and method for adjusting electrical parameters of LDMOS device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113921591A (en) * 2021-09-24 2022-01-11 上海华虹宏力半导体制造有限公司 LDMOS device and forming method thereof

Also Published As

Publication number Publication date
CN111883484B (en) 2023-10-20

Similar Documents

Publication Publication Date Title
US7981783B2 (en) Semiconductor device and method for fabricating the same
US7345341B2 (en) High voltage semiconductor devices and methods for fabricating the same
EP2613357B1 (en) Field-effect transistor and manufacturing method thereof
US7745294B2 (en) Methods of manufacturing trench isolated drain extended MOS (demos) transistors and integrated circuits therefrom
CN111697081B (en) LDMOS device and manufacturing method thereof
US6924529B2 (en) MOS transistor having a recessed gate electrode and fabrication method thereof
KR101531882B1 (en) Semiconductor device and method for manufacturing the same
KR20020072494A (en) Field effect transistor and semiconductor device manufaturing method
CN111106111A (en) Semiconductor device, method of manufacturing the same, and electronic apparatus including the same
US10593781B2 (en) Semiconductor device and fabrication method thereof
CN104377244A (en) Device structure lowering LDMOS on resistance
US9768054B2 (en) High voltage device with low Rdson
CN114361244B (en) LDMOSFET device, manufacturing method and chip
JPS6055665A (en) Manufacture of semiconductor device
US20020025641A1 (en) Method for fabricating a MOSFET and a MOSFET
US8138559B2 (en) Recessed drift region for HVMOS breakdown improvement
CN111883484B (en) Manufacturing method of switching LDMOS device
CN104576732B (en) A kind of parasitic FinFET transverse double-diffusion semiconductor device
US8198659B2 (en) Semiconductor device and method for fabricating the same
KR20090064658A (en) Semiconductor device and method of fabricating the same
CN111446298A (en) Medium-high voltage CMOS device and manufacturing method thereof
CN108962988B (en) High voltage metal oxide semiconductor element and manufacturing method thereof
CN111128700A (en) Preparation method of semiconductor device and semiconductor device
CN216671642U (en) Integrated circuit with a plurality of transistors
CN114639737B (en) LDMOS device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant