CN111446298A - Medium-high voltage CMOS device and manufacturing method thereof - Google Patents
Medium-high voltage CMOS device and manufacturing method thereof Download PDFInfo
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- CN111446298A CN111446298A CN202010277804.1A CN202010277804A CN111446298A CN 111446298 A CN111446298 A CN 111446298A CN 202010277804 A CN202010277804 A CN 202010277804A CN 111446298 A CN111446298 A CN 111446298A
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- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000002513 implantation Methods 0.000 claims description 146
- 239000012535 impurity Substances 0.000 claims description 93
- 125000004429 atom Chemical group 0.000 claims description 91
- 238000002347 injection Methods 0.000 claims description 75
- 239000007924 injection Substances 0.000 claims description 75
- 125000005843 halogen group Chemical group 0.000 claims description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 30
- 239000007943 implant Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 10
- 125000004437 phosphorous atom Chemical group 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 125000001475 halogen functional group Chemical group 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000003111 delayed effect Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
The application relates to the technical field of semiconductor manufacturing, in particular to a medium-high voltage CMOS device and a manufacturing method thereof, wherein the device comprises a first conduction type well region formed in a substrate layer, a gate structure arranged on the substrate layer at the position of the first conduction type well region, a source region structure arranged in the first conduction type well region on one side of the gate structure, a source region structure comprising a pre-doped structure and a second conduction type heavily doped source electrode formed in the pre-doped structure, the pre-doped structure comprising a low-voltage L DD structure and a halo structure, a drain region structure arranged in the first conduction type well region on the other side of the gate structure, and a drain region structure comprising a medium-high voltage L DD structure and a second conduction type heavily doped drain electrode formed in the medium-high voltage L DD structure.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a medium-high voltage CMOS device and a manufacturing method thereof.
Background
The on-resistance and the breakdown voltage are two important parameters of the medium-high voltage CMOS device, the breakdown voltage of the device is related to the reliability of the medium-high voltage CMOS, and the on-resistance of the device is related to the performance of the medium-high voltage CMOS.
Generally, a lightly Doped Drain structure (L bright Doped Drain, L DD) is formed in a Drain region and a source region of a device by implantation before source and Drain heavy doping implantation so as to improve the electric field distribution of the device, improve the breakdown voltage of the device and further improve the reliability of the device, but the on-resistance and the breakdown voltage of the device have a contradiction relation, and for a medium-high voltage CMOS device, the channel length of the medium-high voltage CMOS needs to be shortened while the lightly Doped Drain structure is formed, so that the on-resistance of the device needs to be reduced, and meanwhile, the sufficient breakdown voltage needs to be ensured.
However, as the device channel is continuously shortened, the short channel effect strain caused by the lightly doped drain structure is not negligible. Therefore, how to delay the short channel effect of the device under the condition of further shortening the polysilicon length of the medium-high voltage CMOS device becomes a technical problem to be solved in the field.
Disclosure of Invention
The application provides a medium-high voltage CMOS device and a manufacturing method thereof, which can solve the problem of short channel effect caused by a lightly doped drain structure along with continuous shortening of a device channel in the related technology.
As a first aspect of the present application, there is provided a medium-high voltage CMOS device including at least:
a first conductivity type well region formed in a base layer;
the grid structure is arranged on the substrate layer at the position of the first conductivity type well region;
the source region structure is arranged in the first conduction type well region on one side of the grid structure and comprises a pre-doped structure and a second conduction type heavily-doped source electrode formed in the pre-doped structure, wherein the pre-doped structure comprises a low-voltage L DD structure and a halo structure;
the drain region structure is arranged in the first conductivity type well region on the other side of the gate structure and comprises a medium-high voltage L DD structure and a second conductivity type heavily doped drain electrode formed in the medium-high voltage L DD structure.
Optionally, the impurity atoms in the low pressure L DD structure are arsenic atoms.
Optionally, the implantation energy of the impurity atoms of the low-pressure L DD structure is 2KeV to 5KeV, and the implantation dose is 2KeV13～214/cm2。
Optionally, the impurity atoms in the halo structure are boron atoms.
The implantation energy of the impurity atoms in the optional halo structure is 10 KeV-25 KeV, and the implantation dose is 5KeV12～513/cm2。
The impurity atoms in the medium-high pressure L DD structure are phosphorus atoms.
The implantation energy of the impurity atoms in the medium-high pressure L DD structure is 40 KeV-80 KeV, and the implantation dose is 512～513/cm2。
The implantation energy of the impurity atoms in the medium-high pressure L DD structure is 60 KeV-300 KeV, and the implantation dose is 512～513/cm2。
As a second aspect of the present application, there is provided a method for manufacturing a medium-high voltage CMOS device, the method comprising:
providing a substrate layer, and performing selective implantation on the substrate layer to form a first conductive type well region;
manufacturing a laminated structure of a gate insulating dielectric layer and a gate polycrystalline silicon layer on the substrate layer at the position of the first conductive type well region;
defining the boundary of a gate structure, and etching and removing a gate polycrystalline silicon layer in an area outside the gate structure; because part of the gate insulating dielectric layer can be etched during the etching of the gate polycrystalline silicon layer, a shielding oxide layer is formed on the rest gate insulating dielectric layer outside the gate structure;
coating a first photoresist layer on the surface of the device, opening the first photoresist layer through a photoetching process, and forming a source region injection window on the first photoresist layer;
carrying out pre-doping injection into the source region injection window to form a pre-doping structure in the first conduction type well region, wherein the pre-doping injection comprises low-pressure L DD injection and halo injection;
removing the residual first photoresist layer;
coating a second photoresist layer on the surface of the device, and opening the second photoresist layer at the position of a drain region of the device through a photoetching process to form a drain region injection window;
performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region;
manufacturing a side wall dielectric layer on the periphery of the grid structure, and injecting to form a second conductive type heavily doped source electrode and a second conductive type heavily doped drain electrode;
and removing the shielding oxide layer and the residual second photoresist layer.
As a third aspect of the present application, there is provided a method for manufacturing a medium-high voltage CMOS device, the method comprising:
providing a substrate layer, and performing selective implantation on the substrate layer to form a first conductive type well region;
manufacturing a laminated structure of a gate insulating dielectric layer and a gate polycrystalline silicon layer on the substrate layer at the position of the first conductive type well region;
defining a boundary between the source region and the grid structure, and etching and removing the grid polycrystalline silicon layer at the position of the source region to form a source region injection window at the position of the source region, wherein part of the grid insulating medium layer can be etched during etching of the grid polycrystalline silicon layer, and the rest grid insulating medium layer at the position of the source region forms a shielding oxide layer;
carrying out pre-doping injection into the source region injection window to form a pre-doping structure in the first conduction type well region, wherein the pre-doping injection comprises low-pressure L DD injection and halo injection;
coating a second photoresist layer on the surface of the device, and opening the second photoresist layer at the position of the drain region of the device through a photoetching process;
defining a boundary between the drain region and the gate structure, and etching to remove the gate polysilicon layer at the drain region position, so that a drain region injection window is formed at the drain region position, and because part of the gate insulating dielectric layer is etched during etching of the gate polysilicon layer, a shielding oxide layer is formed on the rest gate insulating dielectric layer at the drain region position;
performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region;
performing second conductive type heavily doped drain injection on the drain injection window, and forming a second conductive type heavily doped drain in the medium-high voltage L DD structure;
and removing the shielding oxide layer and the residual second photoresist layer.
Optionally, performing pre-doping implantation on the source region implantation window includes:
arsenic atoms are used as impurity atoms, the implantation energy of the impurity atoms is 2 KeV-5 KeV, and the implantation dosage of the impurity atoms is 2KeV13～214/cm2Performing low-pressure L DD injection on the source region injection window to form a low-pressure L DD structure;
boron atoms are used as impurity atoms, the implantation energy of the impurity atoms is 10 KeV-25 KeV, and the implantation dosage of the impurity atoms is 5KeV12～513/cm2And carrying out halo implantation on the source region implantation window to form a halo structure.
Optionally, the drain region of the device and a part of the gate structure close to the drain region are exposed through the drain region injection window.
Optionally, the performing a middle-high voltage L DD implantation into the drain region implantation window includes:
phosphorus atoms are used as impurity atoms, the implantation energy of the impurity atoms is 40 KeV-80 KeV, and the implantation dosage of the impurity atoms is 512～513/cm2And performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region.
Optionally, the drain region of the device is exposed through the drain region injection window.
Optionally, phosphorus atoms are used as impurity atoms,the implantation energy of impurity atoms is 60 KeV-300 KeV, and the implantation dosage of impurity atoms is 512～513/cm2And performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region.
The technical scheme at least comprises the following advantages that effective channel injection of a medium-high voltage device can be increased through halo injection, and a short channel effect of the device is delayed, the doping gradient between an N-type heavily doped region and a P-type well region can be improved through medium-high voltage L DD injection of a drain end, and the breakdown voltage of the device is guaranteed.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram of a related art medium and high voltage NMOS device structure;
fig. 2 is a structure of a medium-high voltage NMOS device provided by the present application;
fig. 3A is a schematic structural diagram of a medium-high voltage NMOS device manufacturing method provided in embodiment 1 of the present application after S11 is completed;
fig. 3B is a schematic structural diagram of the middle-high voltage NMOS device manufacturing method provided in embodiment 1 of the present application after S15 is completed;
fig. 3C is a schematic structural diagram of the middle-high voltage NMOS device manufacturing method provided in embodiment 1 of the present application after S19 is completed;
fig. 4A is a schematic structural diagram of a medium-high voltage NMOS device manufacturing method provided in embodiment 2 of the present application after S21 is completed;
fig. 4B is a schematic structural diagram of the middle-high voltage NMOS device manufacturing method provided in embodiment 2 of the present application after S25 is completed;
fig. 4C is a schematic structural diagram of the middle-high voltage NMOS device manufacturing method provided in embodiment 2 of the present application after S29 is completed;
fig. 5 is a schematic diagram of doping concentration of a medium-high voltage NMOS device provided in the present application;
FIG. 6 is an enlarged view of portion A of FIG. 5;
FIG. 7 is a graph illustrating the concentration of impurity atoms on reference lines L1 and L2 for a device of the present application and a device of the related art, respectively;
FIG. 8 is a breakdown voltage characteristic of the device provided herein in the off state;
fig. 9 is a comparison of metallurgical junctions of medium and high voltage CMOS devices provided in the present application and the related art.
In fig. 1, a 101a.p type base layer, a 102a.p type well region, a 103a gate insulating dielectric layer, a 104a gate polysilicon layer, a 105A, L DD injection structure, a 106a side wall dielectric layer, a 107a.n type heavily doped source electrode and a 108a.n type heavily doped drain electrode.
In FIGS. 3A to 3C, and in FIGS. 4A to 4C, 101a base layer 102a P-well 103A pre-doped structure 104A gate insulating dielectric 105a gate polysilicon 106a medium-high voltage L DD structure 107a spacer dielectric 108 an N-heavily doped source 109 an N-heavily doped drain 151 an implant masking oxide 152 a first photoresist layer 153A mask oxide 154A second photoresist layer 200 a source region implant window 300 a drain region implant window,
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a structure of a medium-high voltage NMOS device in the related art, and referring to fig. 1, the structure includes a P-type substrate layer 101A, a P-type well region 102A is formed in the P-type substrate layer 101A, a gate structure is provided on the substrate layer 101A at the position of the P-type well region 102A, the gate structure includes a stacked gate insulating dielectric layer 103A and a gate polysilicon layer 104A, and a sidewall dielectric layer 106A is formed on the periphery of the stacked structure of the gate insulating dielectric layer 103A and the gate polysilicon layer 104A.
L DD injection structures 105A are formed in the P-well region 102A on both sides of the gate structure, wherein a heavily N-doped source 107A is formed in the L DD injection structure 105A on one side, and a heavily N-doped drain 108A is formed in the L DD injection structure 105A on the other side.
In the related art shown in fig. 1, in order to improve the reliability and breakdown voltage of the device, a L DD injection structure 105A is implanted in a P-type well region 102A before forming an N-type heavily Doped source 107A and an N-type heavily Doped Drain 108A, but the L DD injection structure 105A is formed to further shorten the effective length of a device channel, thereby causing a short channel effect of the device.
In order to solve the disadvantages in the related art, the present application provides the following embodiments, which all take NMOS as an example, that is, for NMOS, the first conductivity type is P type, and the second conductivity type is N type; in addition to this embodiment, the present application also includes the equivalent of a PMOS based, i.e., for PMOS, the first conductivity type is N-type and the second conductivity type is P-type.
Example 1:
the embodiment provides a manufacturing method of a medium-high voltage CMOS device, which comprises the following steps:
s11: referring to fig. 3A, a base layer 101 is provided, and a selective implantation is performed on the base layer 101 to form a P-type well region 102;
wherein the base layer 101 is a P-type substrate or a P-type epitaxial layer.
Optionally, an implantation blocking oxide layer 151 is formed on the upper surface of the substrate layer 101 at the position of the P-type well region 102, then selective implantation is performed on a region where the P-type well region 102 needs to be formed, and finally the P-type well region 102 is formed, and after the P-type well region 102 is formed, the implantation blocking oxide layer 151 is removed, so that subsequent operations can be performed conveniently.
S12: on the substrate layer 101 at the position of the P-type well region 102, a stacked structure of a gate insulating dielectric layer 104 and a gate polysilicon layer 105 is fabricated.
S13: defining the boundary of a gate structure, and etching and removing the gate polysilicon layer 105 in the region outside the gate structure; because a part of the gate insulating dielectric layer 104 is etched away when the gate polysilicon layer 105 is etched, a shielding oxide layer 153 is formed on the remaining gate insulating dielectric layer 104 in the region outside the gate structure;
namely, when the gate polysilicon layer 105 is etched, part of the gate insulating dielectric layer 104 is also etched, a part of the gate insulating dielectric layer 104 which is not blocked by the gate polysilicon layer 105 is etched when the gate polysilicon layer 105 is etched, and the rest of the gate insulating dielectric layer 104 which is not etched forms the shielding oxide layer 153;
optionally, by a thermal oxidation process, a gate insulating dielectric layer 104 is formed on the upper surface of the substrate layer 101 (i.e., on the upper surface of the P-type epitaxial layer), and then a gate polysilicon layer 105 is deposited on the upper surface of the gate insulating dielectric layer 104. Because the etching selection ratio between the polysilicon layer and the gate insulating dielectric layer 104 is not infinite, a part of the gate insulating dielectric layer 104 is etched while the gate polysilicon layer 105 is etched, finally, a part of the gate insulating dielectric layer 104 is etched to form the shielding oxide layer 153 in the region outside the gate structure, and the rest of the gate polysilicon layer 105 and the gate insulating dielectric layer 104 covered by the gate polysilicon layer 105 form a laminated gate structure.
Wherein, the thickness range of the gate insulating dielectric layer 104 of the medium-high voltage CMOS is
Therefore, for the medium-high voltage NMOS, the thickness range of the formed shielding oxide layer 153 is:
for low voltage CMOS, the thickness of the gate insulating dielectric layer is in the range of
Therefore, the thickness range of the shielding oxide layer formed on the surface of the low-voltage CMOS active region is
S14: coating a first photoresist layer 152 on the surface of the device after the step S13 is finished, opening the first photoresist layer 152 at the position of the source region of the device through photoetching development, and forming a source region injection window 200 on the first photoresist layer 152;
through the source region implantation window 200, the source region of the device and a part of the gate structure close to the source region are exposed, and the surface of the medium-high voltage device except the source region implantation window 200 is covered by the first photoresist layer 152, so that ion implantation can be conveniently performed on the source region in the subsequent steps.
S15, referring to FIG. 3B, performing pre-doping implantation into the source region implantation window 200 to form a pre-doped structure 103 in the P-type well region 102 at one side of the gate structure, wherein the pre-doping implantation comprises a low voltage L DD implantation and a halo implantation;
the implantation sequence of the low-pressure L DD implantation and the halo implantation in the pre-doping implantation is not limited, that is, the low-pressure L DD implantation is performed first to form a low-pressure L DD structure, then the halo implantation is performed to form a halo structure on the low-pressure L DD structure, or the halo implantation is performed first to form a halo structure, then the low-pressure L DD implantation is performed to form a low-pressure L DD structure on the halo structure.
For the source implantation window 200 formed in S14 of this embodiment, and the source region and a portion of the gate structure near the source region are exposed through the source implantation window 200, when the low-voltage L DD implantation is performed in S15, arsenic atoms are used as impurity atoms, so that the implantation energy of the impurity atoms is 2KeV to 5KeV, and the implantation dose of the impurity atoms is 2KeV13～214/cm2Performing low-pressure L DD implantation into the source region implantation window 200 to form a L DD structure, and performing halo implantation in S15 with boron atoms as impurity atoms at an implantation energy of 10-25 KeV and an implantation dose of 5KeV12～513/cm2Then, a halo implantation is performed into the source implantation window 200 to form a halo structure.
The relative atomic mass of arsenic atoms used for the low pressure L DD implant is 74.92 due to the low pressure LThe DD implant has very low implant energy and large mass of impurity atoms in the thickness range of
The barrier oxide layer 153 can effectively block the low pressure L DD implant, while the relative atomic mass of the boron atoms used for halo implant is 10.81, the barrier oxide layer 153 has a 10KeV to 25KeV implant energy range, and the halo implant with less impurity atomic mass has little effect.
Therefore, for the low-pressure L DD implantation, only a part of impurity atoms are implanted into the silicon surface, and the impurity atoms in the halo implantation can be completely implanted into the silicon body, so that the halo structure formed by the halo implantation can act on the high-voltage and medium-voltage CMOS devices, that is, the effective channel implantation of the devices can be increased, and the short-channel effect of the devices can be delayed.
S16: the remaining first photoresist layer 152 is removed.
S17: coating a second photoresist layer 154 on the surface of the device after the step S16 is completed, opening the second photoresist layer 154 at the position of the drain region of the device through photolithography development, and forming a drain region injection window 300 on the second photoresist layer 154;
through the drain region implantation window 300, the drain region of the device and a part of the gate structure close to the drain region are exposed, and the surface of the device except the drain region implantation window 300 is covered by the second photoresist layer 154, so that ion implantation is performed on the drain region in the subsequent steps.
S18, referring to FIG. 3C, high voltage L DD implantation is performed into the drain implantation window 300, and a middle-high voltage L DD structure 106 is formed in the P-type well region 102 on the other side of the gate structure;
for the embodiment, S18 forms a drain implantation window 300, through which the drain region and a portion of the gate structure near the drain region of the device are exposed, then step S19, during the high voltage L DD implantation, uses phosphorus atoms as impurity atoms, so that the implantation energy of the impurity atoms is 40KeV to 80KeV, and the implantation dose of the impurity atoms is 5KeV12～513/cm2A medium-high voltage L DD implant is performed into the drain implant window 300, in the first conductivity typeA medium-high voltage L DD structure is formed in the well region.
Since part of the gate structure is exposed in this embodiment, the implantation energy of the impurity atoms for the high voltage L DD implantation cannot exceed 80KeV in order to prevent the high voltage L DD implantation from penetrating the gate structure.
S19: and manufacturing a side wall dielectric layer 107 on the periphery of the gate structure, and injecting to form an N-type heavily doped source 108 and an N-type heavily doped drain 109.
The middle-high voltage CMOS device formed by the method for manufacturing a middle-high voltage CMOS device in the present embodiment includes, with reference to fig. 2:
and a base layer 101, wherein the base layer 101 comprises a P-type substrate and an epitaxial layer formed on the P-type substrate.
And a P-type well region 102, wherein the P-type well region 102 is formed in the substrate layer 101, and the P-type well region 102 is on the surface of the substrate layer 101.
The gate structure is arranged on the substrate layer 101 at the position of the P-type well region 102 and comprises a gate insulating medium layer 104 covering the upper surface of the substrate layer 101, gate polysilicon 105 is arranged on the gate insulating medium layer 104, and a side wall medium layer 107 is arranged on the periphery of the gate structure.
A source region structure arranged in the P-type well region 102 at one side of the gate structure, the source region structure including a pre-doped structure 103 and an N-type heavily doped source 108 formed in the pre-doped structure, wherein the pre-doped structure 103 includes a low-voltage L DD structure and a halo structure, impurity atoms in the low-voltage L DD structure are arsenic atoms, impurity atoms in the low-voltage L DD structure have an implantation energy of 2 KeV-5 KeV and an implantation dose of 2KeV13～214/cm2(ii) a The impurity atoms in the halo structure are boron atoms, the implantation energy of the impurity atoms in the halo structure is 10 KeV-25 KeV, and the implantation dosage is 512～513/cm2For the low-pressure L DD implantation, only part of the impurity atoms are implanted into the silicon surface, and the impurity atoms in the halo implantation can be completely implanted into the silicon body, so that the halo structure formed by the halo implantation can act on the high-voltage and medium-voltage CMOS devices, i.e. the effective channel implantation of the devices can be increased, and the short-channel effect of the devices can be delayed.
The drain region structure is arranged in the P-type well region 101 on the other side of the gate structure and comprises a medium-high voltage L DD structure and an N-type heavily doped drain electrode formed in the medium-high voltage L DD structure, impurity atoms of the medium-high voltage L DD structure in the embodiment are phosphorus atoms, the injection energy of the impurity atoms in the medium-high voltage L DD structure is 40 KeV-80 KeV, and the injection dose is 5KeV12～513/cm2。
Example 2:
the embodiment provides another manufacturing method of a medium-high voltage CMOS device, which comprises the following steps:
s21: referring to fig. 4A, a base layer 101 is provided, and a selective implantation is performed on the base layer 101 to form a P-type well region 102;
wherein the base layer 101 includes a P-type substrate or a P-type epitaxial layer;
optionally, an implantation blocking oxide layer 151 is formed on the upper surface of the substrate layer 101 at the position of the P-type well region 102, then selective implantation is performed on a region where the P-type well region 102 needs to be formed, and finally the P-type well region 102 is formed, and after the P-type well region 102 is formed, the implantation blocking oxide layer 151 is removed, so that subsequent operations can be performed conveniently.
S22: manufacturing a laminated structure of a gate insulating dielectric layer 104 and a gate polycrystalline silicon layer 105 on the substrate layer 101 at the position of the P-type well region 102;
optionally, by a thermal oxidation process, a gate insulating dielectric layer 104 is formed on the upper surface of the substrate layer 101 (i.e., on the upper surface of the P-type epitaxial layer), and then a gate polysilicon layer 105 is deposited on the upper surface of the gate insulating dielectric layer 104.
S23: defining a boundary between the source region and the gate structure, etching to remove the gate polysilicon layer 105 at the position of the source region, and etching a part of the gate insulating dielectric layer 104 when the gate polysilicon layer 105 is etched, so that a source region injection window 200 is formed at the position of the source region; because a part of the gate insulating dielectric layer 104 is etched away when the gate polysilicon layer 105 is etched, the remaining gate insulating dielectric layer 104 at the source region position forms a shielding oxide layer 153;
that is, since the gate polysilicon layer 105 is etched, the gate insulating dielectric layer 104 which is not covered by the polysilicon layer 105 is etched to remove a part of the gate insulating dielectric layer 104, so as to form the shielding oxide layer 153;
wherein, the thickness range of the gate insulating dielectric layer 104 of the medium-high voltage CMOS is
Therefore, for the medium-high voltage NMOS, the thickness range of the formed shielding oxide layer 153 is:
for low voltage CMOS, the thickness of the gate insulating dielectric layer is in the range of
Therefore, the thickness range of the shielding oxide layer formed on the surface of the low-voltage CMOS active region is
S24, referring to FIG. 4B, performing pre-doping implantation into the source region implantation window 200 to form a pre-doped structure 103 in the P-type well region 102 at one side of the gate structure, wherein the pre-doping implantation comprises a low voltage L DD implantation and a halo implantation;
the implantation sequence of the low-pressure L DD implantation and the halo implantation in the pre-doping implantation is not limited, that is, the low-pressure L DD implantation is performed first to form a low-pressure L DD structure, then the halo implantation is performed to form a halo structure on the low-pressure L DD structure, or the halo implantation is performed first to form a halo structure, then the low-pressure L DD implantation is performed to form a low-pressure L DD structure on the halo structure.
For the source implantation window 200 formed in S23 of this embodiment, and the source region and a portion of the gate structure near the source region are exposed through the source implantation window 200, when the low-voltage L DD implantation is performed in S24, arsenic atoms are used as impurity atoms, so that the implantation energy of the impurity atoms is 2KeV to 5KeV, and the implantation dose of the impurity atoms is 2KeV13～214/cm2Performing low-voltage L DD implantation into the source region implantation window 200 to form a low-voltage L DD structure S2When halo implantation is performed in the step 4, boron atoms are used as impurity atoms, the implantation energy of the impurity atoms is 10 KeV-25 KeV, and the implantation dose of the impurity atoms is 512～513/cm2Then, a halo implantation is performed into the source implantation window 200 to form a halo structure.
The arsenic atoms used for the low pressure L DD implant have a relative atomic mass of 74.92 and a thickness in the range of 74.92 due to the low implant energy and high impurity atomic mass of the low pressure L DD implant
The barrier oxide layer 153 can effectively block the low pressure L DD implant, while the relative atomic mass of the boron atoms used for halo implant is 10.81, the barrier oxide layer 153 has a 10KeV to 25KeV implant energy range, and the halo implant with less impurity atomic mass has little effect.
Therefore, for the low-pressure L DD implantation, only a part of impurity atoms are implanted into the silicon surface, and the impurity atoms in the halo implantation can be completely implanted into the silicon body, so that the halo structure formed by the halo implantation can act on the high-voltage and medium-voltage CMOS devices, that is, the effective channel implantation of the devices can be increased, and the short-channel effect of the devices can be delayed.
S25: the surface of the device after completion of S24 is coated with a second photoresist layer 154 and developed by photolithography to open the second photoresist layer 154 at the location of the drain region of the device.
S26: and defining a boundary between the drain region and the gate structure, and etching to remove the gate polysilicon layer 105 at the drain region position, so that a drain region injection window 300 is formed at the drain region position, and since a part of the gate insulating dielectric layer 104 is etched away when the gate polysilicon layer 105 is etched, the remaining gate insulating dielectric layer 104 at the drain region position forms a shielding oxide layer 153.
S27, referring to FIG. 4C, high voltage L DD implantation is performed into the drain implantation window 300, and a middle-high voltage L DD structure 106 is formed in the P-type well region 102 on the other side of the gate structure;
step S27 is to use phosphorus atom as impurity atom to make the impurity atom injection energy 60KeV E when high pressure L DD injection is performed300KeV, and the implantation dose of impurity atoms is 512～513/cm2And performing middle-high voltage L DD injection into the drain region injection window 300 to form a middle-high voltage L DD structure in the first conductive type well region.
Since the gate structure is completely covered by the second photoresist layer 154 when the middle-high voltage L DD implantation is performed in this embodiment, the gate structure is not punched during the middle-high voltage L DD implantation.
S28: and manufacturing a side wall dielectric layer 107 on the periphery of the gate structure, and injecting to form an N-type heavily doped source electrode 108 and an N-type heavily doped source electrode 109.
The middle-high voltage CMOS device formed by the method for manufacturing a middle-high voltage CMOS device in the present embodiment includes, with reference to fig. 2:
the middle-high voltage CMOS device formed by the method for manufacturing a middle-high voltage CMOS device in the present embodiment includes:
a base layer 101, wherein the base layer 101 is a P-type substrate or a P-type epitaxial layer.
And a P-type well region 102, wherein the P-type well region 102 is formed in the substrate layer 101, and the P-type well region 102 is on the surface of the substrate layer 101.
The gate structure is arranged on the substrate layer 101 at the position of the P-type well region 102 and comprises a gate insulating medium layer 104 covering the upper surface of the substrate layer 101, gate polysilicon 105 is arranged on the gate insulating medium layer 104, and a side wall medium layer 107 is arranged on the periphery of the gate structure.
A source region structure arranged in the P-type well region 102 at one side of the gate structure, the source region structure including a pre-doped structure 103 and an N-type heavily doped source 108 formed in the pre-doped structure, wherein the pre-doped structure 103 includes a low-voltage L DD structure and a halo structure, impurity atoms in the low-voltage L DD structure are arsenic atoms, impurity atoms in the low-voltage L DD structure have an implantation energy of 2 KeV-5 KeV and an implantation dose of 2KeV13～214/cm2(ii) a The impurity atoms in the halo structure are boron atoms, the implantation energy of the impurity atoms in the halo structure is 10 KeV-25 KeV, and the implantation dosage is 512～513/cm2For low pressure L DD implant, only a portion of the impurityThe atoms of the substance are injected into the silicon surface, and the impurity atoms in the halo injection can be completely injected into the silicon body, so that the halo structure formed by the halo injection can act on the medium-high voltage CMOS device, namely the effective channel injection of the device can be increased, and the short channel effect of the device is delayed.
The drain region structure is arranged in the P-type well region 101 on the other side of the gate structure and comprises a medium-high voltage L DD structure and an N-type heavily doped drain formed in the medium-high voltage L DD structure, in the embodiment, the impurity atoms of the medium-high voltage L DD structure are phosphorus atoms, the implantation energy of the impurity atoms in the medium-high voltage L DD structure is 60 KeV-300 KeV, and the implantation dose is 5KeV12～513/cm2。
Fig. 5 is a schematic diagram of doping concentration of a medium-high voltage NMOS device provided in the present application, where an abscissa X represents a distance from each position of the device in a transverse direction to an origin, and an ordinate represents a distance from each position of the device in a longitudinal direction to the origin.
Fig. 6 is an enlarged schematic view of portion a of fig. 5, and there are two reference lines L1 and L2 for the doping concentration of portion a of fig. 6.
Fig. 7 is a schematic diagram of impurity atom concentration curves of a device in the present application and a device in the related art on reference lines L and L, respectively, and referring to fig. 7, four curves are respectively, the impurity atom concentration (G11) of a medium-high voltage CMOS device provided in the present application along reference line L1, the impurity atom concentration (G12) of the medium-high voltage CMOS device provided in the present application along reference line L, the impurity atom concentration (G21) of the medium-high voltage CMOS device provided in the related art along reference line L, the impurity atom concentration (G22) of the medium-high voltage device provided in the related art along reference line L, four curves show valleys between 0.30um and 0.35um in the lateral direction and between 0.50um and 0.55um at the valley position, which is the boundary between the source region and the channel of the device, and particularly, as seen from the valley values of the respective curves appearing between 0.30um and 0.35um, the impurity atom concentration provided in the high-voltage CMOS device structure is higher than the impurity atom concentration curve provided in the related art such as z4642, the impurity atom concentration curve Z4642, the impurity atom concentration curve in the trench 4642, which is higher than the Z4642, and the impurity atom concentration curve of the impurity atom concentration curve in the lateral direction which is larger than the impurity atom concentration curve 11, which is provided in the trench 4642, which is larger than the channel 465, and the impurity atom concentration curve which is larger than the impurity atom concentration curve in the lateral direction which is larger than the channel 46.
Curve C in fig. 8 is a breakdown voltage characteristic curve of the device provided in the present application in the off state, and curve D is a breakdown voltage characteristic curve of the device provided in the related art in the off state. From fig. 8, it can be seen that the medium-high voltage CMOS device provided by the present application has a higher breakdown voltage and a smaller leakage current.
Fig. 9 is a comparison graph of metallurgical junctions of the medium and high voltage CMOS devices provided in the present application and the related art, and it can be seen from fig. 9 that the effective channel of the medium and high voltage CMOS device provided in the present application is longer.
The method includes the steps that a low-voltage CMOS device which is small in size, thin in gate oxide layer, large in driving capacity and high in speed is introduced into the same process platform to achieve a logic function, in order to inhibit a short channel effect of the medium-voltage and high-voltage CMOS device, a source-drain asymmetric structure is adopted, pre-doping is conducted on a source region of the device before an N-type heavily doped source electrode 108 is formed, namely L DD and a halo of the low-voltage CMOS device are self-aligned and injected to a source end of the medium-voltage and high-voltage CMOS device, so that a pre-doped structure is formed on the edge of a channel on one side of the source end of the device, and medium-high-voltage L DD self-aligned injection is conducted on a drain region of the device before an N-type heavily doped drain electrode.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (15)
1. A middle and high voltage CMOS device, characterized in that it comprises at least:
a first conductivity type well region formed in a base layer;
the grid structure is arranged on the substrate layer at the position of the first conductivity type well region;
the source region structure is arranged in the first conduction type well region on one side of the grid structure and comprises a pre-doped structure and a second conduction type heavily-doped source electrode formed in the pre-doped structure, wherein the pre-doped structure comprises a low-voltage L DD structure and a halo structure;
the drain region structure is arranged in the first conductivity type well region on the other side of the gate structure and comprises a medium-high voltage L DD structure and a second conductivity type heavily doped drain electrode formed in the medium-high voltage L DD structure.
2. The medium-high voltage CMOS device of claim 1, wherein the impurity atoms in the low voltage L DD structure are arsenic atoms.
3. The medium-high voltage CMOS device according to claim 2, wherein the impurity atom implantation energy of the low-voltage L DD structure is 2KeV to 5KeV, and the implantation dose is 2KeV13～214/cm2。
4. The medium-high voltage CMOS device according to claim 1, wherein the impurity atoms in the halo structure are boron atoms.
5. The medium-high voltage CMOS device according to claim 4, wherein the implantation energy of the impurity atoms in the halo structure is 10KeV to 25KeV, and the implantation dose is 5KeV12～513/cm2。
6. The medium-high voltage CMOS device according to claim 1, wherein the impurity atoms in the medium-high voltage L DD structure are phosphorus atoms.
7. The medium-high voltage CMOS device as claimed in claim 6, wherein the impurity atoms in the medium-high voltage L DD structure are implanted at an energy of 40 KeV-80 KeV and an implant dose of 5KeV12～513/cm2。
8. The medium-high voltage CMOS device as claimed in claim 6, wherein the impurity atoms in the medium-high voltage L DD structure are implanted at an energy of 60 KeV-300 KeV and an implant dose of 5KeV12～513/cm2。
9. A manufacturing method of a medium-high voltage CMOS device is characterized by comprising the following steps:
providing a substrate layer, and performing selective implantation on the substrate layer to form a first conductive type well region;
manufacturing a laminated structure of a gate insulating dielectric layer and a gate polycrystalline silicon layer on the substrate layer at the position of the first conductive type well region;
defining the boundary of a gate structure, and etching and removing a gate polycrystalline silicon layer in an area outside the gate structure; because part of the gate insulating dielectric layer can be etched during the etching of the gate polycrystalline silicon layer, a shielding oxide layer is formed on the rest gate insulating dielectric layer outside the gate structure;
coating a first photoresist layer on the surface of the device, opening the first photoresist layer through a photoetching process, and forming a source region injection window on the first photoresist layer;
carrying out pre-doping injection into the source region injection window to form a pre-doping structure in the first conduction type well region, wherein the pre-doping injection comprises low-pressure L DD injection and halo injection;
removing the residual first photoresist layer;
coating a second photoresist layer on the surface of the device, and opening the second photoresist layer at the position of a drain region of the device through a photoetching process to form a drain region injection window;
performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region;
manufacturing a side wall dielectric layer on the periphery of the grid structure, and injecting to form a second conductive type heavily doped source electrode and a second conductive type heavily doped drain electrode;
and removing the shielding oxide layer and the residual second photoresist layer.
10. A manufacturing method of a medium-high voltage CMOS device is characterized by comprising the following steps:
providing a substrate layer, and performing selective implantation on the substrate layer to form a first conductive type well region;
manufacturing a laminated structure of a gate insulating dielectric layer and a gate polycrystalline silicon layer on the substrate layer at the position of the first conductive type well region;
defining a boundary between the source region and the grid structure, and etching and removing the grid polycrystalline silicon layer at the position of the source region to form a source region injection window at the position of the source region, wherein part of the grid insulating medium layer can be etched during etching of the grid polycrystalline silicon layer, and the rest grid insulating medium layer at the position of the source region forms a shielding oxide layer;
carrying out pre-doping injection into the source region injection window to form a pre-doping structure in the first conduction type well region, wherein the pre-doping injection comprises low-pressure L DD injection and halo injection;
coating a second photoresist layer on the surface of the device, and opening the second photoresist layer at the position of the drain region of the device through a photoetching process;
defining a boundary between the drain region and the gate structure, and etching to remove the gate polysilicon layer at the drain region position, so that a drain region injection window is formed at the drain region position, and because part of the gate insulating dielectric layer is etched during etching of the gate polysilicon layer, a shielding oxide layer is formed on the rest gate insulating dielectric layer at the drain region position;
performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region;
manufacturing a side wall dielectric layer on the periphery of the grid structure, and injecting to form a second conductive type heavily doped source electrode and a second conductive type heavily doped drain electrode;
and removing the shielding oxide layer and the residual second photoresist layer.
11. The method for manufacturing a medium-high voltage CMOS device according to claim 9 or 10, wherein the performing a pre-doping implantation into the source region implantation window comprises:
arsenic atoms are used as impurity atoms, the implantation energy of the impurity atoms is 2 KeV-5 KeV, and the implantation dosage of the impurity atoms is 2KeV13～214/cm2Performing low-pressure L DD injection on the source region injection window to form a low-pressure L DD structure;
boron atoms are used as impurity atoms, the implantation energy of the impurity atoms is 10 KeV-25 KeV, and the implantation dosage of the impurity atoms is 5KeV12～513/cm2And carrying out halo implantation on the source region implantation window to form a halo structure.
12. The method for manufacturing the medium-high voltage CMOS device according to claim 9, wherein a drain region of the device and a part of the gate structure close to the drain region are exposed through the drain region implantation window.
13. The method for manufacturing a medium-high voltage CMOS device according to claim 11, wherein the performing of the medium-high voltage L DD implantation into the drain region implantation window comprises:
phosphorus atoms are used as impurity atoms, the implantation energy of the impurity atoms is 40 KeV-80 KeV, and the implantation dosage of the impurity atoms is 512～513/cm2And performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region.
14. The method for manufacturing a medium-high voltage CMOS device according to claim 10, wherein a drain region of the device is exposed through the drain region implantation window.
15. The method of manufacturing a medium-high voltage CMOS device according to claim 14, wherein phosphorus atoms are used as impurity atoms, the impurity atom implantation energy is 60KeV to 300KeV, and the impurity atom implantation dose is 5KeV12～513/cm3And performing middle-high voltage L DD injection into the drain region injection window to form a middle-high voltage L DD structure in the first conductive type well region.
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